abc76f20cb
creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. --HG-- extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
738 lines
18 KiB
C++
738 lines
18 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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*/
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#include "arch/locked_mem.hh"
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#include "arch/utility.hh"
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#include "base/bigint.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/simple/timing.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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#include "params/TimingSimpleCPU.hh"
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#include "sim/system.hh"
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using namespace std;
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using namespace TheISA;
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Port *
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TimingSimpleCPU::getPort(const std::string &if_name, int idx)
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{
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if (if_name == "dcache_port")
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return &dcachePort;
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else if (if_name == "icache_port")
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return &icachePort;
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else
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panic("No Such Port\n");
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}
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void
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TimingSimpleCPU::init()
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{
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BaseCPU::init();
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#if FULL_SYSTEM
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for (int i = 0; i < threadContexts.size(); ++i) {
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ThreadContext *tc = threadContexts[i];
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// initialize CPU, including PC
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TheISA::initCPU(tc, tc->readCpuId());
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}
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#endif
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}
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Tick
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TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
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{
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panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
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return curTick;
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}
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void
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TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
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{
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//No internal storage to update, jusst return
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return;
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}
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void
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TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
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{
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if (status == RangeChange) {
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if (!snoopRangeSent) {
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snoopRangeSent = true;
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sendStatusChange(Port::RangeChange);
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}
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return;
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}
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panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
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}
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void
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TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
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{
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pkt = _pkt;
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Event::schedule(t);
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}
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TimingSimpleCPU::TimingSimpleCPU(Params *p)
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: BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock),
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cpu_id(p->cpu_id)
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{
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_status = Idle;
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icachePort.snoopRangeSent = false;
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dcachePort.snoopRangeSent = false;
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ifetch_pkt = dcache_pkt = NULL;
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drainEvent = NULL;
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fetchEvent = NULL;
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previousTick = 0;
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changeState(SimObject::Running);
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}
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TimingSimpleCPU::~TimingSimpleCPU()
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{
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}
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void
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TimingSimpleCPU::serialize(ostream &os)
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{
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SimObject::State so_state = SimObject::getState();
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SERIALIZE_ENUM(so_state);
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BaseSimpleCPU::serialize(os);
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}
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void
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TimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
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{
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SimObject::State so_state;
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UNSERIALIZE_ENUM(so_state);
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BaseSimpleCPU::unserialize(cp, section);
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}
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unsigned int
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TimingSimpleCPU::drain(Event *drain_event)
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{
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// TimingSimpleCPU is ready to drain if it's not waiting for
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// an access to complete.
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if (status() == Idle || status() == Running || status() == SwitchedOut) {
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changeState(SimObject::Drained);
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return 0;
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} else {
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changeState(SimObject::Draining);
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drainEvent = drain_event;
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return 1;
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}
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}
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void
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TimingSimpleCPU::resume()
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{
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if (_status != SwitchedOut && _status != Idle) {
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assert(system->getMemoryMode() == Enums::timing);
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// Delete the old event if it existed.
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if (fetchEvent) {
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if (fetchEvent->scheduled())
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fetchEvent->deschedule();
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delete fetchEvent;
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}
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fetchEvent = new FetchEvent(this, nextCycle());
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}
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changeState(SimObject::Running);
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previousTick = curTick;
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}
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void
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TimingSimpleCPU::switchOut()
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{
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assert(status() == Running || status() == Idle);
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_status = SwitchedOut;
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numCycles += curTick - previousTick;
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// If we've been scheduled to resume but are then told to switch out,
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// we'll need to cancel it.
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if (fetchEvent && fetchEvent->scheduled())
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fetchEvent->deschedule();
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}
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void
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TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
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{
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BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);
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// if any of this CPU's ThreadContexts are active, mark the CPU as
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// running and schedule its tick event.
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for (int i = 0; i < threadContexts.size(); ++i) {
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ThreadContext *tc = threadContexts[i];
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if (tc->status() == ThreadContext::Active && _status != Running) {
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_status = Running;
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break;
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}
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}
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if (_status != Running) {
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_status = Idle;
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}
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}
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void
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TimingSimpleCPU::activateContext(int thread_num, int delay)
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{
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assert(thread_num == 0);
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assert(thread);
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assert(_status == Idle);
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notIdleFraction++;
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_status = Running;
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// kick things off by initiating the fetch of the next instruction
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fetchEvent = new FetchEvent(this, nextCycle(curTick + cycles(delay)));
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}
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void
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TimingSimpleCPU::suspendContext(int thread_num)
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{
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assert(thread_num == 0);
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assert(thread);
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assert(_status == Running);
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// just change status to Idle... if status != Running,
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// completeInst() will not initiate fetch of next instruction.
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notIdleFraction--;
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_status = Idle;
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}
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template <class T>
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Fault
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TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
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{
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Request *req =
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new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
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cpu_id, /* thread ID */ 0);
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if (traceData) {
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traceData->setAddr(req->getVaddr());
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}
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// translate to physical address
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Fault fault = thread->translateDataReadReq(req);
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// Now do the access.
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if (fault == NoFault) {
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PacketPtr pkt =
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new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
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pkt->dataDynamic<T>(new T);
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if (!dcachePort.sendTiming(pkt)) {
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_status = DcacheRetry;
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dcache_pkt = pkt;
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} else {
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_status = DcacheWaitResponse;
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// memory system takes ownership of packet
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dcache_pkt = NULL;
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}
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// This will need a new way to tell if it has a dcache attached.
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if (req->isUncacheable())
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recordEvent("Uncached Read");
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} else {
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delete req;
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}
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return fault;
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}
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#ifndef DOXYGEN_SHOULD_SKIP_THIS
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template
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Fault
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TimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
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template
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Fault
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TimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
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template
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Fault
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TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
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template
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Fault
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TimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
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template
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Fault
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TimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
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template
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Fault
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TimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
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#endif //DOXYGEN_SHOULD_SKIP_THIS
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template<>
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Fault
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TimingSimpleCPU::read(Addr addr, double &data, unsigned flags)
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{
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return read(addr, *(uint64_t*)&data, flags);
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}
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template<>
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Fault
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TimingSimpleCPU::read(Addr addr, float &data, unsigned flags)
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{
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return read(addr, *(uint32_t*)&data, flags);
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}
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template<>
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Fault
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TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
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{
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return read(addr, (uint32_t&)data, flags);
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}
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template <class T>
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Fault
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TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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{
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Request *req =
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new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
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cpu_id, /* thread ID */ 0);
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if (traceData) {
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traceData->setAddr(req->getVaddr());
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}
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// translate to physical address
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Fault fault = thread->translateDataWriteReq(req);
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// Now do the access.
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if (fault == NoFault) {
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assert(dcache_pkt == NULL);
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if (req->isSwap())
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dcache_pkt = new Packet(req, MemCmd::SwapReq, Packet::Broadcast);
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else
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dcache_pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
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dcache_pkt->allocate();
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dcache_pkt->set(data);
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bool do_access = true; // flag to suppress cache access
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if (req->isLocked()) {
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do_access = TheISA::handleLockedWrite(thread, req);
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}
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if (req->isCondSwap()) {
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assert(res);
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req->setExtraData(*res);
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}
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if (do_access) {
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if (!dcachePort.sendTiming(dcache_pkt)) {
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_status = DcacheRetry;
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} else {
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_status = DcacheWaitResponse;
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// memory system takes ownership of packet
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dcache_pkt = NULL;
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}
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}
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// This will need a new way to tell if it's hooked up to a cache or not.
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if (req->isUncacheable())
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recordEvent("Uncached Write");
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} else {
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delete req;
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}
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// If the write needs to have a fault on the access, consider calling
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// changeStatus() and changing it to "bad addr write" or something.
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return fault;
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}
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#ifndef DOXYGEN_SHOULD_SKIP_THIS
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template
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Fault
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TimingSimpleCPU::write(Twin32_t data, Addr addr,
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unsigned flags, uint64_t *res);
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template
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Fault
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TimingSimpleCPU::write(Twin64_t data, Addr addr,
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unsigned flags, uint64_t *res);
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template
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Fault
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TimingSimpleCPU::write(uint64_t data, Addr addr,
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unsigned flags, uint64_t *res);
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template
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Fault
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TimingSimpleCPU::write(uint32_t data, Addr addr,
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unsigned flags, uint64_t *res);
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template
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Fault
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TimingSimpleCPU::write(uint16_t data, Addr addr,
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unsigned flags, uint64_t *res);
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template
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Fault
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TimingSimpleCPU::write(uint8_t data, Addr addr,
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unsigned flags, uint64_t *res);
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#endif //DOXYGEN_SHOULD_SKIP_THIS
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template<>
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Fault
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TimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
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{
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return write(*(uint64_t*)&data, addr, flags, res);
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}
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template<>
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Fault
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TimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
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{
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return write(*(uint32_t*)&data, addr, flags, res);
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}
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template<>
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Fault
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TimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
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{
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return write((uint32_t)data, addr, flags, res);
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}
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void
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TimingSimpleCPU::fetch()
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{
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if (!curStaticInst || !curStaticInst->isDelayedCommit())
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checkForInterrupts();
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Request *ifetch_req = new Request();
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ifetch_req->setThreadContext(cpu_id, /* thread ID */ 0);
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Fault fault = setupFetchRequest(ifetch_req);
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ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
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ifetch_pkt->dataStatic(&inst);
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if (fault == NoFault) {
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if (!icachePort.sendTiming(ifetch_pkt)) {
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// Need to wait for retry
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_status = IcacheRetry;
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} else {
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// Need to wait for cache to respond
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_status = IcacheWaitResponse;
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// ownership of packet transferred to memory system
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ifetch_pkt = NULL;
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}
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} else {
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delete ifetch_req;
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delete ifetch_pkt;
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// fetch fault: advance directly to next instruction (fault handler)
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advanceInst(fault);
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}
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numCycles += curTick - previousTick;
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previousTick = curTick;
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}
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void
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TimingSimpleCPU::advanceInst(Fault fault)
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{
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advancePC(fault);
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if (_status == Running) {
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// kick off fetch of next instruction... callback from icache
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// response will cause that instruction to be executed,
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// keeping the CPU running.
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fetch();
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}
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}
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void
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TimingSimpleCPU::completeIfetch(PacketPtr pkt)
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{
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// received a response from the icache: execute the received
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// instruction
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assert(pkt->result == Packet::Success);
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assert(_status == IcacheWaitResponse);
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_status = Running;
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numCycles += curTick - previousTick;
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previousTick = curTick;
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if (getState() == SimObject::Draining) {
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delete pkt->req;
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delete pkt;
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completeDrain();
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return;
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}
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preExecute();
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if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
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// load or store: just send to dcache
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Fault fault = curStaticInst->initiateAcc(this, traceData);
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if (_status != Running) {
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// instruction will complete in dcache response callback
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assert(_status == DcacheWaitResponse || _status == DcacheRetry);
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assert(fault == NoFault);
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} else {
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if (fault == NoFault) {
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// early fail on store conditional: complete now
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assert(dcache_pkt != NULL);
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fault = curStaticInst->completeAcc(dcache_pkt, this,
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traceData);
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delete dcache_pkt->req;
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delete dcache_pkt;
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dcache_pkt = NULL;
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}
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postExecute();
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advanceInst(fault);
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}
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} else {
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// non-memory instruction: execute completely now
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Fault fault = curStaticInst->execute(this, traceData);
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postExecute();
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advanceInst(fault);
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}
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delete pkt->req;
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delete pkt;
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}
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void
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TimingSimpleCPU::IcachePort::ITickEvent::process()
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{
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cpu->completeIfetch(pkt);
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}
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bool
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TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
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{
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if (pkt->isResponse()) {
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// delay processing of returned data until next CPU clock edge
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Tick next_tick = cpu->nextCycle(curTick);
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if (next_tick == curTick)
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cpu->completeIfetch(pkt);
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else
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tickEvent.schedule(pkt, next_tick);
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return true;
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}
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else if (pkt->result == Packet::Nacked) {
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assert(cpu->_status == IcacheWaitResponse);
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pkt->reinitNacked();
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if (!sendTiming(pkt)) {
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cpu->_status = IcacheRetry;
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cpu->ifetch_pkt = pkt;
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}
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}
|
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//Snooping a Coherence Request, do nothing
|
|
return true;
|
|
}
|
|
|
|
void
|
|
TimingSimpleCPU::IcachePort::recvRetry()
|
|
{
|
|
// we shouldn't get a retry unless we have a packet that we're
|
|
// waiting to transmit
|
|
assert(cpu->ifetch_pkt != NULL);
|
|
assert(cpu->_status == IcacheRetry);
|
|
PacketPtr tmp = cpu->ifetch_pkt;
|
|
if (sendTiming(tmp)) {
|
|
cpu->_status = IcacheWaitResponse;
|
|
cpu->ifetch_pkt = NULL;
|
|
}
|
|
}
|
|
|
|
void
|
|
TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
|
|
{
|
|
// received a response from the dcache: complete the load or store
|
|
// instruction
|
|
assert(pkt->result == Packet::Success);
|
|
assert(_status == DcacheWaitResponse);
|
|
_status = Running;
|
|
|
|
numCycles += curTick - previousTick;
|
|
previousTick = curTick;
|
|
|
|
Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
|
|
|
|
if (pkt->isRead() && pkt->req->isLocked()) {
|
|
TheISA::handleLockedRead(thread, pkt->req);
|
|
}
|
|
|
|
delete pkt->req;
|
|
delete pkt;
|
|
|
|
postExecute();
|
|
|
|
if (getState() == SimObject::Draining) {
|
|
advancePC(fault);
|
|
completeDrain();
|
|
|
|
return;
|
|
}
|
|
|
|
advanceInst(fault);
|
|
}
|
|
|
|
|
|
void
|
|
TimingSimpleCPU::completeDrain()
|
|
{
|
|
DPRINTF(Config, "Done draining\n");
|
|
changeState(SimObject::Drained);
|
|
drainEvent->process();
|
|
}
|
|
|
|
void
|
|
TimingSimpleCPU::DcachePort::setPeer(Port *port)
|
|
{
|
|
Port::setPeer(port);
|
|
|
|
#if FULL_SYSTEM
|
|
// Update the ThreadContext's memory ports (Functional/Virtual
|
|
// Ports)
|
|
cpu->tcBase()->connectMemPorts();
|
|
#endif
|
|
}
|
|
|
|
bool
|
|
TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
|
|
{
|
|
if (pkt->isResponse()) {
|
|
// delay processing of returned data until next CPU clock edge
|
|
Tick next_tick = cpu->nextCycle(curTick);
|
|
|
|
if (next_tick == curTick)
|
|
cpu->completeDataAccess(pkt);
|
|
else
|
|
tickEvent.schedule(pkt, next_tick);
|
|
|
|
return true;
|
|
}
|
|
else if (pkt->result == Packet::Nacked) {
|
|
assert(cpu->_status == DcacheWaitResponse);
|
|
pkt->reinitNacked();
|
|
if (!sendTiming(pkt)) {
|
|
cpu->_status = DcacheRetry;
|
|
cpu->dcache_pkt = pkt;
|
|
}
|
|
}
|
|
//Snooping a Coherence Request, do nothing
|
|
return true;
|
|
}
|
|
|
|
void
|
|
TimingSimpleCPU::DcachePort::DTickEvent::process()
|
|
{
|
|
cpu->completeDataAccess(pkt);
|
|
}
|
|
|
|
void
|
|
TimingSimpleCPU::DcachePort::recvRetry()
|
|
{
|
|
// we shouldn't get a retry unless we have a packet that we're
|
|
// waiting to transmit
|
|
assert(cpu->dcache_pkt != NULL);
|
|
assert(cpu->_status == DcacheRetry);
|
|
PacketPtr tmp = cpu->dcache_pkt;
|
|
if (sendTiming(tmp)) {
|
|
cpu->_status = DcacheWaitResponse;
|
|
// memory system takes ownership of packet
|
|
cpu->dcache_pkt = NULL;
|
|
}
|
|
}
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////
|
|
//
|
|
// TimingSimpleCPU Simulation Object
|
|
//
|
|
TimingSimpleCPU *
|
|
TimingSimpleCPUParams::create()
|
|
{
|
|
TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params();
|
|
params->name = name;
|
|
params->numberOfThreads = 1;
|
|
params->max_insts_any_thread = max_insts_any_thread;
|
|
params->max_insts_all_threads = max_insts_all_threads;
|
|
params->max_loads_any_thread = max_loads_any_thread;
|
|
params->max_loads_all_threads = max_loads_all_threads;
|
|
params->progress_interval = progress_interval;
|
|
params->deferRegistration = defer_registration;
|
|
params->clock = clock;
|
|
params->phase = phase;
|
|
params->functionTrace = function_trace;
|
|
params->functionTraceStart = function_trace_start;
|
|
params->system = system;
|
|
params->cpu_id = cpu_id;
|
|
|
|
#if FULL_SYSTEM
|
|
params->itb = itb;
|
|
params->dtb = dtb;
|
|
params->profile = profile;
|
|
params->do_quiesce = do_quiesce;
|
|
params->do_checkpoint_insts = do_checkpoint_insts;
|
|
params->do_statistics_insts = do_statistics_insts;
|
|
#else
|
|
if (workload.size() != 1)
|
|
panic("only one workload allowed");
|
|
params->process = workload[0];
|
|
#endif
|
|
|
|
TimingSimpleCPU *cpu = new TimingSimpleCPU(params);
|
|
return cpu;
|
|
}
|