f7055e9215
Rewrite the HDLCD controller to use the new DMA engine and pixel pump. This fixes several bugs in the current implementation: * Broken/missing interrupt support (VSync, underrun, DMA end) * Fragile resolution changes (changing resolutions used to cause assertion errors). * Support for resolutions with a width that isn't divisible by 32. * The pixel clock can now be set dynamically. This breaks checkpoint compatibility. Checkpoints can be upgraded with the checkpoint conversion script. However, upgraded checkpoints won't contain the state of the current frame. That means that HDLCD controllers restoring from a converted checkpoint immediately start drawing a new frame (i.e, expect timing differences). |
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.. | ||
arm-ccregs.py | ||
arm-contextidr-el2.py | ||
arm-hdlcd-upgrade.py | ||
arm-miscreg-teehbr.py | ||
armv8.py | ||
cpu-pid.py | ||
dvfs-perflevel.py | ||
ide-dma-abort.py | ||
isa-is-simobject.py | ||
memory-per-range.py | ||
multiple-event-queues.py | ||
process-fdmap-rename.py | ||
remove-arm-cpsr-mode-miscreg.py | ||
ruby-block-size-bytes.py | ||
x86-add-tlb.py |