1204 lines
138 KiB
Text
1204 lines
138 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.058203 # Number of seconds simulated
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sim_ticks 58202727500 # Number of ticks simulated
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final_tick 58202727500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 129726 # Simulator instruction rate (inst/s)
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host_op_rate 130372 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 83346935 # Simulator tick rate (ticks/s)
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host_mem_usage 443628 # Number of bytes of host memory used
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host_seconds 698.32 # Real time elapsed on the host
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sim_insts 90589798 # Number of instructions simulated
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sim_ops 91041029 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 44480 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 45376 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.l2cache.prefetcher 930112 # Number of bytes read from this memory
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system.physmem.bytes_read::total 1019968 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 44480 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 44480 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 22912 # Number of bytes written to this memory
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system.physmem.bytes_written::total 22912 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 695 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 709 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.l2cache.prefetcher 14533 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 15937 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 358 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 358 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 764225 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 779620 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.l2cache.prefetcher 15980557 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 17524402 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 764225 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 764225 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 393659 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 393659 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 393659 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 764225 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 779620 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.l2cache.prefetcher 15980557 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 17918061 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 15937 # Number of read requests accepted
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system.physmem.writeReqs 358 # Number of write requests accepted
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system.physmem.readBursts 15937 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 358 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 1010432 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 9536 # Total number of bytes read from write queue
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system.physmem.bytesWritten 21184 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 1019968 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 22912 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 149 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 3 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 1009 # Per bank write bursts
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system.physmem.perBankRdBursts::1 876 # Per bank write bursts
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system.physmem.perBankRdBursts::2 958 # Per bank write bursts
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system.physmem.perBankRdBursts::3 1024 # Per bank write bursts
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system.physmem.perBankRdBursts::4 1064 # Per bank write bursts
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system.physmem.perBankRdBursts::5 1132 # Per bank write bursts
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system.physmem.perBankRdBursts::6 1124 # Per bank write bursts
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system.physmem.perBankRdBursts::7 1103 # Per bank write bursts
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system.physmem.perBankRdBursts::8 1046 # Per bank write bursts
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system.physmem.perBankRdBursts::9 962 # Per bank write bursts
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system.physmem.perBankRdBursts::10 937 # Per bank write bursts
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system.physmem.perBankRdBursts::11 899 # Per bank write bursts
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system.physmem.perBankRdBursts::12 909 # Per bank write bursts
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system.physmem.perBankRdBursts::13 889 # Per bank write bursts
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system.physmem.perBankRdBursts::14 926 # Per bank write bursts
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system.physmem.perBankRdBursts::15 930 # Per bank write bursts
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system.physmem.perBankWrBursts::0 30 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 8 # Per bank write bursts
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system.physmem.perBankWrBursts::3 1 # Per bank write bursts
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system.physmem.perBankWrBursts::4 10 # Per bank write bursts
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system.physmem.perBankWrBursts::5 29 # Per bank write bursts
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system.physmem.perBankWrBursts::6 69 # Per bank write bursts
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system.physmem.perBankWrBursts::7 31 # Per bank write bursts
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system.physmem.perBankWrBursts::8 36 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 7 # Per bank write bursts
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system.physmem.perBankWrBursts::11 0 # Per bank write bursts
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system.physmem.perBankWrBursts::12 7 # Per bank write bursts
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system.physmem.perBankWrBursts::13 27 # Per bank write bursts
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system.physmem.perBankWrBursts::14 45 # Per bank write bursts
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system.physmem.perBankWrBursts::15 31 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 58202569500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 15937 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 358 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 10945 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 2405 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 522 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 349 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 310 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 297 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 305 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 289 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 304 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 62 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 19 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 19 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 19 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 19 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 19 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 19 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 19 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 20 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 19 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 18 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 18 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 18 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 22 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 20 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 18 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 18 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 18 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 1871 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 551.268840 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 315.885566 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 433.770323 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 552 29.50% 29.50% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 218 11.65% 41.15% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 92 4.92% 46.07% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 57 3.05% 49.12% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 63 3.37% 52.49% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 44 2.35% 54.84% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 55 2.94% 57.78% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 42 2.24% 60.02% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 748 39.98% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 1871 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 18 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 874.777778 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::gmean 39.760140 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 3541.219224 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-511 17 94.44% 94.44% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::14848-15359 1 5.56% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 18 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 18 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 18.388889 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 18.356746 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 1.195033 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::18 15 83.33% 83.33% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::19 2 11.11% 94.44% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::23 1 5.56% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::total 18 # Writes before turning the bus around for reads
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system.physmem.totQLat 172783990 # Total ticks spent queuing
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system.physmem.totMemAccLat 468808990 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 78940000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 10944.01 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 29694.01 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 17.36 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.36 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 17.52 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.39 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 0.14 # Data bus utilization in percentage
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system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 16.15 # Average write queue length when enqueuing
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system.physmem.readRowHits 14154 # Number of row buffer hits during reads
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system.physmem.writeRowHits 93 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 89.65 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 26.20 # Row buffer hit rate for writes
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system.physmem.avgGap 3571805.43 # Average gap between requests
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system.physmem.pageHitRate 88.25 # Row buffer hit rate, read and write combined
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system.physmem_0.actEnergy 7658280 # Energy for activate commands per rank (pJ)
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system.physmem_0.preEnergy 4178625 # Energy for precharge commands per rank (pJ)
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system.physmem_0.readEnergy 64638600 # Energy for read commands per rank (pJ)
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system.physmem_0.writeEnergy 1153440 # Energy for write commands per rank (pJ)
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system.physmem_0.refreshEnergy 3801486000 # Energy for refresh commands per rank (pJ)
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system.physmem_0.actBackEnergy 2451888630 # Energy for active background per rank (pJ)
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system.physmem_0.preBackEnergy 32770707750 # Energy for precharge background per rank (pJ)
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system.physmem_0.totalEnergy 39101711325 # Total energy per rank (pJ)
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system.physmem_0.averagePower 671.822097 # Core power per rank (mW)
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system.physmem_0.memoryStateTime::IDLE 54506616189 # Time in different power states
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system.physmem_0.memoryStateTime::REF 1943500000 # Time in different power states
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system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem_0.memoryStateTime::ACT 1752376311 # Time in different power states
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system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.physmem_1.actEnergy 6486480 # Energy for activate commands per rank (pJ)
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system.physmem_1.preEnergy 3539250 # Energy for precharge commands per rank (pJ)
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system.physmem_1.readEnergy 58484400 # Energy for read commands per rank (pJ)
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system.physmem_1.writeEnergy 991440 # Energy for write commands per rank (pJ)
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system.physmem_1.refreshEnergy 3801486000 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 2431326735 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 32788744500 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 39091058805 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 671.639072 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 54537138662 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 1943500000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 1721853838 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu.branchPred.lookups 28259323 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 23281308 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 837964 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 11850778 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 11785443 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 99.448686 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 75758 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 89 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 442 # Number of system calls
|
|
system.cpu.numCycles 116405456 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 749294 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 134993998 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 28259323 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 11861201 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 114761716 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 1679249 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.MiscStallCycles 1000 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 840 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 32304088 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 579 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 116352474 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 1.165469 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 1.319047 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 58780581 50.52% 50.52% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 13944559 11.98% 62.50% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 9221403 7.93% 70.43% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 34405931 29.57% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 116352474 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.242766 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 1.159688 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 8844184 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 64087377 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 33032699 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 9560836 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 827378 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 4101289 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 12349 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 114434840 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 1995518 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 827378 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 15306554 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 49837632 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 110028 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 35408205 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 14862677 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 110902804 # Number of instructions processed by rename
|
|
system.cpu.rename.SquashedInsts 1415247 # Number of squashed instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 11133046 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 1143083 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 1515709 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 570063 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 129962368 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 483290389 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 119478713 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 424 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 22649449 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 4363 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 4358 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 21572068 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 26814283 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 5349560 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 615072 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 351208 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 109694902 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 8246 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 101389982 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 1073881 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 18465721 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 41703174 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 116352474 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.871404 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 0.988585 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 54656656 46.98% 46.98% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 31447896 27.03% 74.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 21997479 18.91% 92.91% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 7054961 6.06% 98.97% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 1195165 1.03% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 317 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 116352474 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 9796147 48.71% 48.71% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 50 0.00% 48.71% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 48.71% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.71% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.71% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.71% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 48.71% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.71% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.71% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.71% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.71% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.71% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.71% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.71% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.71% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 48.71% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.71% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 48.71% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.71% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.71% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.71% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.71% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.71% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 12 0.00% 48.71% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.71% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.71% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.71% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.71% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.71% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 9605529 47.77% 96.48% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 708223 3.52% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 71985557 71.00% 71.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 10710 0.01% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 58 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 123 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 24344215 24.01% 95.02% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 5049315 4.98% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 101389982 # Type of FU issued
|
|
system.cpu.iq.rate 0.871007 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 20109961 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.198343 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 340315821 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 128169527 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 99626078 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 459 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 609 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 115 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 121499704 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 239 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 282708 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 4338372 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 1511 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 1302 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 604716 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 7561 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 130367 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 827378 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 8117043 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 661508 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 109715814 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 26814283 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 5349560 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 4358 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 178487 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 319637 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 1302 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 436579 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 412967 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 849546 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 100128293 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 23807365 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 1261689 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 12666 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 28725194 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 20624883 # Number of branches executed
|
|
system.cpu.iew.exec_stores 4917829 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.860168 # Inst execution rate
|
|
system.cpu.iew.wb_sent 99711182 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 99626193 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 59706016 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 95562461 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.855855 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.624785 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 17390136 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 825718 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 113659456 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.801109 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.737097 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 77211009 67.93% 67.93% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 18641585 16.40% 84.33% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 7152887 6.29% 90.63% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 3463018 3.05% 93.67% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 1652627 1.45% 95.13% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 524640 0.46% 95.59% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 723684 0.64% 96.23% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 178635 0.16% 96.38% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 4111371 3.62% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 113659456 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 90602407 # Number of instructions committed
|
|
system.cpu.commit.committedOps 91053638 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 27220755 # Number of memory references committed
|
|
system.cpu.commit.loads 22475911 # Number of loads committed
|
|
system.cpu.commit.membars 3888 # Number of memory barriers committed
|
|
system.cpu.commit.branches 18732304 # Number of branches committed
|
|
system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 72326352 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 56148 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 63822386 70.09% 70.09% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 91053638 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 4111371 # number cycles where commit BW limit reached
|
|
system.cpu.rob.rob_reads 217986125 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 219581178 # The number of ROB writes
|
|
system.cpu.timesIdled 584 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 52982 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 90589798 # Number of Instructions Simulated
|
|
system.cpu.committedOps 91041029 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 1.284973 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 1.284973 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.778226 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.778226 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 108112973 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 58701982 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 58 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 95 # number of floating regfile writes
|
|
system.cpu.cc_regfile_reads 369069288 # number of cc regfile reads
|
|
system.cpu.cc_regfile_writes 58692619 # number of cc regfile writes
|
|
system.cpu.misc_regfile_reads 28415446 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
|
|
system.cpu.dcache.tags.replacements 5469543 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.788616 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 18297454 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 5470055 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 3.345022 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 35157000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.788616 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999587 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999587 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 342 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 61924995 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 61924995 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 13934183 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 13934183 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 4354974 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 4354974 # number of WriteReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 18289157 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 18289157 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 18289679 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 18289679 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 9550003 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 9550003 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 380007 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 380007 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 9930010 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 9930010 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 9930017 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 9930017 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 88443276736 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 88443276736 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3962066244 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 3962066244 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 297000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 297000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 92405342980 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 92405342980 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 92405342980 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 92405342980 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 23484186 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 23484186 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 529 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 28219167 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 28219167 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 28219696 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 28219696 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.406657 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.406657 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080255 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.080255 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.351889 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.351889 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.351882 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.351882 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9261.073189 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 9261.073189 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10426.298052 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 10426.298052 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19800 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19800 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 9305.664645 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 9305.664645 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 9305.658085 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 9305.658085 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 306020 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 36082 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 120709 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 2278 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.535188 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 15.839333 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 5439051 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 5439051 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4313021 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 4313021 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 146936 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 146936 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 4459957 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 4459957 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 4459957 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 4459957 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5236982 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 5236982 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 233071 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 233071 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 5470053 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 5470053 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 5470057 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 5470057 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40519086258 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 40519086258 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2295163471 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2295163471 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 213000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 213000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42814249729 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 42814249729 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42814462729 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 42814462729 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223000 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223000 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049223 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049223 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193842 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.193842 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193838 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.193838 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7737.106268 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7737.106268 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9847.486264 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9847.486264 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53250 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53250 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7827.026489 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 7827.026489 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7827.059705 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 7827.059705 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 451 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 428.263511 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 32302915 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 910 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 35497.708791 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 428.263511 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.836452 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.836452 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 21 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 332 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.896484 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 64609056 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 64609056 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 32302915 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 32302915 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 32302915 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 32302915 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 32302915 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 32302915 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1158 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1158 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1158 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1158 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1158 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1158 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 62669987 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 62669987 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 62669987 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 62669987 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 62669987 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 62669987 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 32304073 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 32304073 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 32304073 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 32304073 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 32304073 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 32304073 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54119.159758 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 54119.159758 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54119.159758 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 54119.159758 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54119.159758 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 54119.159758 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 19414 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 134 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 238 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 81.571429 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets 26.800000 # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 248 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 248 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 248 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 248 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 248 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 910 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 910 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 910 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 910 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50368733 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 50368733 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50368733 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 50368733 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50368733 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 50368733 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55350.256044 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55350.256044 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55350.256044 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 55350.256044 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55350.256044 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 55350.256044 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 4495585 # number of hwpf issued
|
|
system.cpu.l2cache.prefetcher.pfIdentified 5292074 # number of prefetch candidates identified
|
|
system.cpu.l2cache.prefetcher.pfBufferHit 687825 # number of redundant prefetches already in prefetch queue
|
|
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
|
|
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
|
|
system.cpu.l2cache.prefetcher.pfSpanPage 14072766 # number of prefetches not generated due to page crossing
|
|
system.cpu.l2cache.tags.replacements 493 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 12074.856330 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 10653372 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 15934 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 668.593699 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 11119.543661 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 571.365929 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 202.646634 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 181.300106 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.678683 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.034873 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.012369 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.011066 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.736991 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1022 216 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15225 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::2 13 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::3 3 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::4 191 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 974 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1048 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13130 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.013184 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.929260 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 174809424 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 174809424 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 213 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 5236439 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 5236652 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 5439051 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 5439051 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 232688 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 232688 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 213 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 5469127 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 5469340 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 213 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 5469127 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 5469340 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 697 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 416 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 1113 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 512 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 512 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 697 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 928 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 1625 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 697 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 928 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 1625 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 48506493 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 26932750 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 75439243 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 46498 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 46498 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 37042063 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 37042063 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 48506493 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 63974813 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 112481306 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 48506493 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 63974813 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 112481306 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 910 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 5236855 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 5237765 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 5439051 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 5439051 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 233200 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 233200 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 910 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 5470055 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 5470965 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 910 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 5470055 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 5470965 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.765934 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000079 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.000212 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002196 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.002196 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.765934 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.000170 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.000297 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.765934 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.000170 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.000297 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69593.246772 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64742.187500 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 67780.092543 # average ReadReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 23249 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 23249 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72347.779297 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72347.779297 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69593.246772 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68938.376078 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 69219.265231 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69593.246772 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68938.376078 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 69219.265231 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 358 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 358 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 48 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 50 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 171 # number of ReadExReq MSHR hits
|
|
system.cpu.l2cache.ReadExReq_mshr_hits::total 171 # number of ReadExReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 219 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 221 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 219 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 221 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 695 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 368 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 1063 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 20246 # number of HardPFReq MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_misses::total 20246 # number of HardPFReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 341 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 341 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 695 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 709 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 1404 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 695 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 709 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 20246 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 21650 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 42518507 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 21103750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 63622257 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 830590289 # number of HardPFReq MSHR miss cycles
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 830590289 # number of HardPFReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27502 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27502 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 25988008 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 25988008 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 42518507 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 47091758 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 89610265 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 42518507 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 47091758 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 830590289 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 920200554 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.763736 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000070 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000203 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001462 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001462 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.763736 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.000257 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.763736 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.003957 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61177.707914 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57347.146739 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59851.605833 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41024.908081 # average HardPFReq mshr miss latency
|
|
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 41024.908081 # average HardPFReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13751 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13751 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76211.167155 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76211.167155 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61177.707914 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66419.968970 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63824.975071 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61177.707914 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66419.968970 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41024.908081 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42503.489792 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 5237765 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 5237765 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 5439051 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::HardPFReq 22132 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 233200 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 233200 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1820 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16379167 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 16380987 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58240 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 698182912 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 698241152 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 22134 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 10932150 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 3.002024 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.044949 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::3 10910018 99.80% 99.80% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::4 22132 0.20% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 10932150 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 10894060998 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%)
|
|
system.cpu.toL2Bus.snoopLayer0.occupancy 3000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1497004 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 8205133181 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%)
|
|
system.membus.trans_dist::ReadReq 15596 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 15596 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 358 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 2 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 341 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 341 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32236 # Packet count per connected master and slave (bytes)
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|
system.membus.pkt_count::total 32236 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1042880 # Cumulative packet size per connected master and slave (bytes)
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|
system.membus.pkt_size::total 1042880 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 16297 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 16297 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 16297 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 26854780 # Layer occupancy (ticks)
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|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 83365318 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
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