2303 lines
264 KiB
Text
2303 lines
264 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 1.904438 # Number of seconds simulated
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sim_ticks 1904437574000 # Number of ticks simulated
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final_tick 1904437574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 150033 # Simulator instruction rate (inst/s)
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host_op_rate 150033 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 5049661741 # Simulator tick rate (ticks/s)
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host_mem_usage 379720 # Number of bytes of host memory used
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host_seconds 377.14 # Real time elapsed on the host
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sim_insts 56583768 # Number of instructions simulated
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sim_ops 56583768 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu0.inst 878144 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 24662016 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 107328 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 745792 # Number of bytes read from this memory
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system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
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system.physmem.bytes_read::total 26394240 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 878144 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 107328 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 985472 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 7983616 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7983616 # Number of bytes written to this memory
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system.physmem.num_reads::cpu0.inst 13721 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 385344 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 1677 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 11653 # Number of read requests responded to by this memory
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system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 412410 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 124744 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 124744 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu0.inst 461104 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 12949763 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 56357 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 391607 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 13859336 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 461104 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 56357 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 517461 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 4192112 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 4192112 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 4192112 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 461104 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 12949763 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 56357 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 391607 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::tsunami.ide 504 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 18051448 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 412410 # Number of read requests accepted
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system.physmem.writeReqs 166296 # Number of write requests accepted
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system.physmem.readBursts 412410 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 166296 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 26387648 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue
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system.physmem.bytesWritten 9015296 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 26394240 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 10642944 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 25417 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 4739 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 25681 # Per bank write bursts
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system.physmem.perBankRdBursts::1 26031 # Per bank write bursts
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system.physmem.perBankRdBursts::2 26262 # Per bank write bursts
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system.physmem.perBankRdBursts::3 25929 # Per bank write bursts
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system.physmem.perBankRdBursts::4 25778 # Per bank write bursts
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system.physmem.perBankRdBursts::5 25597 # Per bank write bursts
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system.physmem.perBankRdBursts::6 26273 # Per bank write bursts
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system.physmem.perBankRdBursts::7 25295 # Per bank write bursts
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system.physmem.perBankRdBursts::8 25970 # Per bank write bursts
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system.physmem.perBankRdBursts::9 26150 # Per bank write bursts
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system.physmem.perBankRdBursts::10 25721 # Per bank write bursts
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system.physmem.perBankRdBursts::11 25208 # Per bank write bursts
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system.physmem.perBankRdBursts::12 25640 # Per bank write bursts
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system.physmem.perBankRdBursts::13 25768 # Per bank write bursts
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system.physmem.perBankRdBursts::14 25547 # Per bank write bursts
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system.physmem.perBankRdBursts::15 25457 # Per bank write bursts
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system.physmem.perBankWrBursts::0 9358 # Per bank write bursts
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system.physmem.perBankWrBursts::1 9077 # Per bank write bursts
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system.physmem.perBankWrBursts::2 9200 # Per bank write bursts
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system.physmem.perBankWrBursts::3 8756 # Per bank write bursts
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system.physmem.perBankWrBursts::4 8419 # Per bank write bursts
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system.physmem.perBankWrBursts::5 8251 # Per bank write bursts
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system.physmem.perBankWrBursts::6 9072 # Per bank write bursts
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system.physmem.perBankWrBursts::7 8046 # Per bank write bursts
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system.physmem.perBankWrBursts::8 8692 # Per bank write bursts
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system.physmem.perBankWrBursts::9 8978 # Per bank write bursts
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system.physmem.perBankWrBursts::10 8574 # Per bank write bursts
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system.physmem.perBankWrBursts::11 8968 # Per bank write bursts
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system.physmem.perBankWrBursts::12 8555 # Per bank write bursts
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system.physmem.perBankWrBursts::13 9260 # Per bank write bursts
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system.physmem.perBankWrBursts::14 8896 # Per bank write bursts
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system.physmem.perBankWrBursts::15 8762 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 50 # Number of times write queue was full causing retry
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system.physmem.totGap 1904433039500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 412410 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 166296 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 317706 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 39027 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 30801 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 24670 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 80 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 13 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::15 1213 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 1828 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 3688 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 4340 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::19 5378 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::20 5892 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::21 5750 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 6059 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::23 5976 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::24 6158 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 6391 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::26 7775 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::27 6815 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::28 7719 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::29 9990 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::30 7735 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::31 7720 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 6503 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::33 1166 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::34 710 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::35 1250 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::36 1084 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::37 1301 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::38 880 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::39 1700 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::40 1725 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::41 1711 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::42 1699 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::43 1843 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::44 1941 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::45 2112 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::46 2607 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::47 2803 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::48 2144 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::49 1758 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::50 1391 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::51 1284 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::52 788 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::53 490 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::54 295 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::55 225 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::56 216 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 180 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 125 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 159 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 115 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 88 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::62 52 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 92 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 66375 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 533.371902 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 326.032515 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 416.702689 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 14841 22.36% 22.36% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 11366 17.12% 39.48% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::256-383 5910 8.90% 48.39% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::384-511 2909 4.38% 52.77% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::512-639 2416 3.64% 56.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::640-767 1747 2.63% 59.04% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-895 1634 2.46% 61.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-1023 1312 1.98% 63.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1151 24240 36.52% 100.00% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::total 66375 # Bytes accessed per row activation
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|
system.physmem.rdPerTurnAround::samples 5272 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::mean 78.206942 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::stdev 2891.855588 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::0-8191 5269 99.94% 99.94% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 5272 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 5272 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::mean 26.719272 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::gmean 18.348145 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::stdev 60.306865 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16-31 5026 95.33% 95.33% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-47 55 1.04% 96.38% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::48-63 6 0.11% 96.49% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-79 3 0.06% 96.55% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-95 6 0.11% 96.66% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::96-111 3 0.06% 96.72% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::112-127 3 0.06% 96.78% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-143 6 0.11% 96.89% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::144-159 24 0.46% 97.34% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::160-175 10 0.19% 97.53% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::176-191 9 0.17% 97.70% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::192-207 16 0.30% 98.01% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::208-223 2 0.04% 98.05% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::224-239 3 0.06% 98.10% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::240-255 3 0.06% 98.16% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::256-271 4 0.08% 98.24% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::272-287 1 0.02% 98.25% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::288-303 4 0.08% 98.33% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::304-319 6 0.11% 98.44% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::320-335 11 0.21% 98.65% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::336-351 13 0.25% 98.90% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::352-367 7 0.13% 99.03% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::368-383 10 0.19% 99.22% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::384-399 3 0.06% 99.28% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::400-415 1 0.02% 99.30% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::416-431 1 0.02% 99.32% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::464-479 2 0.04% 99.36% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::480-495 11 0.21% 99.56% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::496-511 3 0.06% 99.62% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::512-527 2 0.04% 99.66% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::528-543 1 0.02% 99.68% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::544-559 5 0.09% 99.77% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::560-575 3 0.06% 99.83% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::640-655 1 0.02% 99.85% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::672-687 2 0.04% 99.89% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::688-703 2 0.04% 99.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::720-735 3 0.06% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::896-911 1 0.02% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 5272 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 4111304500 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 11842060750 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 2061535000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 9971.46 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 28721.46 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 13.86 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 4.73 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 13.86 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 5.59 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.15 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 2.27 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 25.00 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 371693 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 115102 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 90.15 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 81.70 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 3290847.23 # Average gap between requests
|
|
system.physmem.pageHitRate 88.00 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 251551440 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 137255250 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 1613398800 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 454759920 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 124388181840 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 57693505320 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 1092050470500 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 1276589123070 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 670.325620 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 1816548038492 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 63593140000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 24290182758 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 250137720 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 136483875 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 1602190200 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 457604640 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 124388181840 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 57661176915 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 1092078837000 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 1276574612190 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 670.317995 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 1816597555496 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 63593140000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 24242350004 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu0.branchPred.lookups 16050181 # Number of BP lookups
|
|
system.cpu0.branchPred.condPredicted 14012515 # Number of conditional branches predicted
|
|
system.cpu0.branchPred.condIncorrect 321303 # Number of conditional branches incorrect
|
|
system.cpu0.branchPred.BTBLookups 9883832 # Number of BTB lookups
|
|
system.cpu0.branchPred.BTBHits 5384164 # Number of BTB hits
|
|
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu0.branchPred.BTBHitPct 54.474459 # BTB Hit Percentage
|
|
system.cpu0.branchPred.usedRAS 809394 # Number of times the RAS was used to get a target.
|
|
system.cpu0.branchPred.RASInCorrect 17633 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu0.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu0.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu0.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu0.dtb.read_hits 9185685 # DTB read hits
|
|
system.cpu0.dtb.read_misses 31794 # DTB read misses
|
|
system.cpu0.dtb.read_acv 464 # DTB read access violations
|
|
system.cpu0.dtb.read_accesses 674724 # DTB read accesses
|
|
system.cpu0.dtb.write_hits 5856177 # DTB write hits
|
|
system.cpu0.dtb.write_misses 6642 # DTB write misses
|
|
system.cpu0.dtb.write_acv 308 # DTB write access violations
|
|
system.cpu0.dtb.write_accesses 220970 # DTB write accesses
|
|
system.cpu0.dtb.data_hits 15041862 # DTB hits
|
|
system.cpu0.dtb.data_misses 38436 # DTB misses
|
|
system.cpu0.dtb.data_acv 772 # DTB access violations
|
|
system.cpu0.dtb.data_accesses 895694 # DTB accesses
|
|
system.cpu0.itb.fetch_hits 1413849 # ITB hits
|
|
system.cpu0.itb.fetch_misses 27924 # ITB misses
|
|
system.cpu0.itb.fetch_acv 522 # ITB acv
|
|
system.cpu0.itb.fetch_accesses 1441773 # ITB accesses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.read_acv 0 # DTB read access violations
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.write_acv 0 # DTB write access violations
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.data_hits 0 # DTB hits
|
|
system.cpu0.itb.data_misses 0 # DTB misses
|
|
system.cpu0.itb.data_acv 0 # DTB access violations
|
|
system.cpu0.itb.data_accesses 0 # DTB accesses
|
|
system.cpu0.numCycles 115311619 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.fetch.icacheStallCycles 26308115 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu0.fetch.Insts 70327057 # Number of instructions fetch has processed
|
|
system.cpu0.fetch.Branches 16050181 # Number of branches that fetch encountered
|
|
system.cpu0.fetch.predictedBranches 6193558 # Number of branches that fetch has predicted taken
|
|
system.cpu0.fetch.Cycles 81501759 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu0.fetch.SquashCycles 1071492 # Number of cycles fetch has spent squashing
|
|
system.cpu0.fetch.TlbCycles 564 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu0.fetch.MiscStallCycles 28477 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu0.fetch.PendingTrapStallCycles 1405877 # Number of stall cycles due to pending traps
|
|
system.cpu0.fetch.PendingQuiesceStallCycles 453989 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu0.fetch.IcacheWaitRetryStallCycles 199 # Number of stall cycles due to full MSHR
|
|
system.cpu0.fetch.CacheLines 8110639 # Number of cache lines fetched
|
|
system.cpu0.fetch.IcacheSquashes 231031 # Number of outstanding Icache misses that were squashed
|
|
system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu0.fetch.rateDist::samples 110234726 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::mean 0.637976 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::stdev 1.938280 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::0 97059343 88.05% 88.05% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::1 844439 0.77% 88.81% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::2 1832569 1.66% 90.48% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::3 778966 0.71% 91.18% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::4 2587591 2.35% 93.53% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::5 590382 0.54% 94.07% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::6 655112 0.59% 94.66% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::7 842956 0.76% 95.42% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::8 5043368 4.58% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::total 110234726 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.branchRate 0.139190 # Number of branch fetches per cycle
|
|
system.cpu0.fetch.rate 0.609887 # Number of inst fetches per cycle
|
|
system.cpu0.decode.IdleCycles 21404943 # Number of cycles decode is idle
|
|
system.cpu0.decode.BlockedCycles 78060690 # Number of cycles decode is blocked
|
|
system.cpu0.decode.RunCycles 8511786 # Number of cycles decode is running
|
|
system.cpu0.decode.UnblockCycles 1756604 # Number of cycles decode is unblocking
|
|
system.cpu0.decode.SquashCycles 500702 # Number of cycles decode is squashing
|
|
system.cpu0.decode.BranchResolved 518589 # Number of times decode resolved a branch
|
|
system.cpu0.decode.BranchMispred 35397 # Number of times decode detected a branch misprediction
|
|
system.cpu0.decode.DecodedInsts 61724420 # Number of instructions handled by decode
|
|
system.cpu0.decode.SquashedInsts 110442 # Number of squashed instructions handled by decode
|
|
system.cpu0.rename.SquashCycles 500702 # Number of cycles rename is squashing
|
|
system.cpu0.rename.IdleCycles 22241314 # Number of cycles rename is idle
|
|
system.cpu0.rename.BlockCycles 51035680 # Number of cycles rename is blocking
|
|
system.cpu0.rename.serializeStallCycles 18875449 # count of cycles rename stalled for serializing inst
|
|
system.cpu0.rename.RunCycles 9340106 # Number of cycles rename is running
|
|
system.cpu0.rename.UnblockCycles 8241473 # Number of cycles rename is unblocking
|
|
system.cpu0.rename.RenamedInsts 59592973 # Number of instructions processed by rename
|
|
system.cpu0.rename.ROBFullEvents 194522 # Number of times rename has blocked due to ROB full
|
|
system.cpu0.rename.IQFullEvents 2018079 # Number of times rename has blocked due to IQ full
|
|
system.cpu0.rename.LQFullEvents 142482 # Number of times rename has blocked due to LQ full
|
|
system.cpu0.rename.SQFullEvents 4327383 # Number of times rename has blocked due to SQ full
|
|
system.cpu0.rename.RenamedOperands 39868450 # Number of destination operands rename has renamed
|
|
system.cpu0.rename.RenameLookups 72416227 # Number of register rename lookups that rename has made
|
|
system.cpu0.rename.int_rename_lookups 72269697 # Number of integer rename lookups
|
|
system.cpu0.rename.fp_rename_lookups 136600 # Number of floating rename lookups
|
|
system.cpu0.rename.CommittedMaps 34997307 # Number of HB maps that are committed
|
|
system.cpu0.rename.UndoneMaps 4871143 # Number of HB maps that are undone due to squashing
|
|
system.cpu0.rename.serializingInsts 1466604 # count of serializing insts renamed
|
|
system.cpu0.rename.tempSerializingInsts 213801 # count of temporary serializing insts renamed
|
|
system.cpu0.rename.skidInsts 12439963 # count of insts added to the skid buffer
|
|
system.cpu0.memDep0.insertedLoads 9310742 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.insertedStores 6112181 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.conflictingLoads 1342468 # Number of conflicting loads.
|
|
system.cpu0.memDep0.conflictingStores 951279 # Number of conflicting stores.
|
|
system.cpu0.iq.iqInstsAdded 53110388 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu0.iq.iqNonSpecInstsAdded 1887245 # Number of non-speculative instructions added to the IQ
|
|
system.cpu0.iq.iqInstsIssued 52243998 # Number of instructions issued
|
|
system.cpu0.iq.iqSquashedInstsIssued 50112 # Number of squashed instructions issued
|
|
system.cpu0.iq.iqSquashedInstsExamined 6322079 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu0.iq.iqSquashedOperandsExamined 2924940 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu0.iq.iqSquashedNonSpecRemoved 1298251 # Number of squashed non-spec instructions that were removed
|
|
system.cpu0.iq.issued_per_cycle::samples 110234726 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::mean 0.473934 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::stdev 1.210494 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::0 88757561 80.52% 80.52% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::1 9303542 8.44% 88.96% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::2 3888317 3.53% 92.48% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::3 2690563 2.44% 94.92% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::4 2829805 2.57% 97.49% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::5 1399486 1.27% 98.76% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::6 891988 0.81% 99.57% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::7 364157 0.33% 99.90% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::8 109307 0.10% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::total 110234726 # Number of insts issued each cycle
|
|
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntAlu 184539 19.02% 19.02% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntMult 0 0.00% 19.02% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntDiv 0 0.00% 19.02% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 19.02% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 19.02% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 19.02% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatMult 0 0.00% 19.02% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 19.02% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 19.02% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 19.02% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 19.02% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 19.02% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 19.02% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 19.02% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 19.02% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMult 0 0.00% 19.02% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 19.02% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShift 0 0.00% 19.02% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 19.02% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 19.02% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 19.02% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 19.02% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 19.02% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 19.02% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 19.02% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 19.02% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 19.02% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.02% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 19.02% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemRead 463483 47.76% 66.78% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemWrite 322428 33.22% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.FU_type_0::No_OpClass 4481 0.01% 0.01% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntAlu 35873428 68.67% 68.67% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntMult 57323 0.11% 68.78% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.78% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatAdd 30345 0.06% 68.84% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.84% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.84% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.84% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatDiv 2234 0.00% 68.85% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.85% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.85% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.85% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.85% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.85% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.85% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.85% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.85% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.85% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.85% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.85% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.85% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.85% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.85% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.85% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.85% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.85% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.85% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.85% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.85% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.85% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemRead 9533353 18.25% 87.09% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemWrite 5924969 11.34% 98.43% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IprAccess 817865 1.57% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::total 52243998 # Type of FU issued
|
|
system.cpu0.iq.rate 0.453068 # Inst issue rate
|
|
system.cpu0.iq.fu_busy_cnt 970450 # FU busy when requested
|
|
system.cpu0.iq.fu_busy_rate 0.018575 # FU busy rate (busy events/executed inst)
|
|
system.cpu0.iq.int_inst_queue_reads 215148578 # Number of integer instruction queue reads
|
|
system.cpu0.iq.int_inst_queue_writes 61059123 # Number of integer instruction queue writes
|
|
system.cpu0.iq.int_inst_queue_wakeup_accesses 50866456 # Number of integer instruction queue wakeup accesses
|
|
system.cpu0.iq.fp_inst_queue_reads 594706 # Number of floating instruction queue reads
|
|
system.cpu0.iq.fp_inst_queue_writes 278076 # Number of floating instruction queue writes
|
|
system.cpu0.iq.fp_inst_queue_wakeup_accesses 273817 # Number of floating instruction queue wakeup accesses
|
|
system.cpu0.iq.int_alu_accesses 52889876 # Number of integer alu accesses
|
|
system.cpu0.iq.fp_alu_accesses 320091 # Number of floating point alu accesses
|
|
system.cpu0.iew.lsq.thread0.forwLoads 579148 # Number of loads that had data forwarded from stores
|
|
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.squashedLoads 1102308 # Number of loads squashed
|
|
system.cpu0.iew.lsq.thread0.ignoredResponses 4274 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu0.iew.lsq.thread0.memOrderViolation 17841 # Number of memory ordering violations
|
|
system.cpu0.iew.lsq.thread0.squashedStores 488268 # Number of stores squashed
|
|
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu0.iew.lsq.thread0.rescheduledLoads 18769 # Number of loads that were rescheduled
|
|
system.cpu0.iew.lsq.thread0.cacheBlocked 362429 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu0.iew.iewSquashCycles 500702 # Number of cycles IEW is squashing
|
|
system.cpu0.iew.iewBlockCycles 47770294 # Number of cycles IEW is blocking
|
|
system.cpu0.iew.iewUnblockCycles 975694 # Number of cycles IEW is unblocking
|
|
system.cpu0.iew.iewDispatchedInsts 58389413 # Number of instructions dispatched to IQ
|
|
system.cpu0.iew.iewDispSquashedInsts 117266 # Number of squashed instructions skipped by dispatch
|
|
system.cpu0.iew.iewDispLoadInsts 9310742 # Number of dispatched load instructions
|
|
system.cpu0.iew.iewDispStoreInsts 6112181 # Number of dispatched store instructions
|
|
system.cpu0.iew.iewDispNonSpecInsts 1666926 # Number of dispatched non-speculative instructions
|
|
system.cpu0.iew.iewIQFullEvents 38737 # Number of times the IQ has become full, causing a stall
|
|
system.cpu0.iew.iewLSQFullEvents 734939 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu0.iew.memOrderViolationEvents 17841 # Number of memory order violations
|
|
system.cpu0.iew.predictedTakenIncorrect 161758 # Number of branches that were predicted taken incorrectly
|
|
system.cpu0.iew.predictedNotTakenIncorrect 354564 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu0.iew.branchMispredicts 516322 # Number of branch mispredicts detected at execute
|
|
system.cpu0.iew.iewExecutedInsts 51738600 # Number of executed instructions
|
|
system.cpu0.iew.iewExecLoadInsts 9239994 # Number of load instructions executed
|
|
system.cpu0.iew.iewExecSquashedInsts 505398 # Number of squashed instructions skipped in execute
|
|
system.cpu0.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu0.iew.exec_nop 3391780 # number of nop insts executed
|
|
system.cpu0.iew.exec_refs 15116199 # number of memory reference insts executed
|
|
system.cpu0.iew.exec_branches 8225133 # Number of branches executed
|
|
system.cpu0.iew.exec_stores 5876205 # Number of stores executed
|
|
system.cpu0.iew.exec_rate 0.448685 # Inst execution rate
|
|
system.cpu0.iew.wb_sent 51252595 # cumulative count of insts sent to commit
|
|
system.cpu0.iew.wb_count 51140273 # cumulative count of insts written-back
|
|
system.cpu0.iew.wb_producers 26435135 # num instructions producing a value
|
|
system.cpu0.iew.wb_consumers 36676301 # num instructions consuming a value
|
|
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu0.iew.wb_rate 0.443496 # insts written-back per cycle
|
|
system.cpu0.iew.wb_fanout 0.720769 # average fanout of values written-back
|
|
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu0.commit.commitSquashedInsts 6957791 # The number of squashed insts skipped by commit
|
|
system.cpu0.commit.commitNonSpecStalls 588994 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu0.commit.branchMispredicts 471378 # The number of times a branch was mispredicted
|
|
system.cpu0.commit.committed_per_cycle::samples 109009912 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::mean 0.470894 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::stdev 1.405994 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::0 90895183 83.38% 83.38% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::1 7166067 6.57% 89.96% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::2 3956975 3.63% 93.59% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::3 2029230 1.86% 95.45% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::4 1623676 1.49% 96.94% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::5 582620 0.53% 97.47% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::6 429957 0.39% 97.87% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::7 432812 0.40% 98.26% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::8 1893392 1.74% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::total 109009912 # Number of insts commited each cycle
|
|
system.cpu0.commit.committedInsts 51332073 # Number of instructions committed
|
|
system.cpu0.commit.committedOps 51332073 # Number of ops (including micro ops) committed
|
|
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu0.commit.refs 13832347 # Number of memory references committed
|
|
system.cpu0.commit.loads 8208434 # Number of loads committed
|
|
system.cpu0.commit.membars 200823 # Number of memory barriers committed
|
|
system.cpu0.commit.branches 7767218 # Number of branches committed
|
|
system.cpu0.commit.fp_insts 270478 # Number of committed floating point instructions.
|
|
system.cpu0.commit.int_insts 47526784 # Number of committed integer instructions.
|
|
system.cpu0.commit.function_calls 660195 # Number of function calls committed.
|
|
system.cpu0.commit.op_class_0::No_OpClass 2960587 5.77% 5.77% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IntAlu 33426068 65.12% 70.88% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IntMult 56116 0.11% 70.99% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.99% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatAdd 30044 0.06% 71.05% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.05% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.05% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.05% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatDiv 2234 0.00% 71.06% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.06% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.06% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.06% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.06% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.06% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.06% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.06% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.06% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.06% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.06% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.06% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.06% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.06% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.06% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.06% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.06% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.06% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.06% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.06% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.06% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.06% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::MemRead 8409257 16.38% 87.44% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::MemWrite 5629902 10.97% 98.41% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IprAccess 817865 1.59% 100.00% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::total 51332073 # Class of committed instruction
|
|
system.cpu0.commit.bw_lim_events 1893392 # number cycles where commit BW limit reached
|
|
system.cpu0.rob.rob_reads 165216916 # The number of ROB reads
|
|
system.cpu0.rob.rob_writes 117798939 # The number of ROB writes
|
|
system.cpu0.timesIdled 506110 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu0.idleCycles 5076893 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu0.quiesceCycles 3693292578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu0.committedInsts 48375955 # Number of Instructions Simulated
|
|
system.cpu0.committedOps 48375955 # Number of Ops (including micro ops) Simulated
|
|
system.cpu0.cpi 2.383656 # CPI: Cycles Per Instruction
|
|
system.cpu0.cpi_total 2.383656 # CPI: Total CPI of All Threads
|
|
system.cpu0.ipc 0.419524 # IPC: Instructions Per Cycle
|
|
system.cpu0.ipc_total 0.419524 # IPC: Total IPC of All Threads
|
|
system.cpu0.int_regfile_reads 67964697 # number of integer regfile reads
|
|
system.cpu0.int_regfile_writes 37032803 # number of integer regfile writes
|
|
system.cpu0.fp_regfile_reads 135608 # number of floating regfile reads
|
|
system.cpu0.fp_regfile_writes 136877 # number of floating regfile writes
|
|
system.cpu0.misc_regfile_reads 1822860 # number of misc regfile reads
|
|
system.cpu0.misc_regfile_writes 821150 # number of misc regfile writes
|
|
system.cpu0.dcache.tags.replacements 1283357 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 505.867544 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 10588066 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 1283792 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 8.247493 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 26416000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.867544 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988023 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.988023 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 435 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 435 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.849609 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 56965784 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 56965784 # Number of data accesses
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 6531926 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 6531926 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 3699481 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 3699481 # number of WriteReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 164387 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 164387 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 189172 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 189172 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 10231407 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 10231407 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 10231407 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 10231407 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 1592146 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 1592146 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 1718300 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 1718300 # number of WriteReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20836 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 20836 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2478 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 2478 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 3310446 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 3310446 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 3310446 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 3310446 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39294199360 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 39294199360 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 76231824796 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 76231824796 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 326020750 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 326020750 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20798848 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 20798848 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 115526024156 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 115526024156 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 115526024156 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 115526024156 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 8124072 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 8124072 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5417781 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 5417781 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 185223 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 185223 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 191650 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 191650 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 13541853 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 13541853 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 13541853 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 13541853 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.195979 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.195979 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.317159 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.317159 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112491 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112491 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.012930 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.012930 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.244460 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.244460 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.244460 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.244460 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24680.022661 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 24680.022661 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44364.677179 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 44364.677179 # average WriteReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15646.993185 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15646.993185 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8393.401130 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8393.401130 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34897.419911 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 34897.419911 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34897.419911 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 34897.419911 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 4226969 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 4392 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 103766 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 94 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 40.735588 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets 46.723404 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 752753 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 752753 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 572031 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 572031 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1457971 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::total 1457971 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4881 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4881 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu0.data 2030002 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 2030002 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu0.data 2030002 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 2030002 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1020115 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 1020115 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 260329 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 260329 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15955 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15955 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2477 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 2477 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 1280444 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 1280444 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 1280444 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 1280444 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 28982142208 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 28982142208 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11887451669 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11887451669 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 177873500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 177873500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 17082652 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 17082652 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 40869593877 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 40869593877 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 40869593877 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 40869593877 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1464167000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1464167000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2129748498 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2129748498 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3593915498 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3593915498 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125567 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125567 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048051 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048051 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086139 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086139 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.012925 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.012925 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094555 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.094555 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094555 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.094555 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28410.661747 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28410.661747 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45663.186464 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45663.186464 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11148.448762 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11148.448762 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6896.508680 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6896.508680 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31918.298557 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31918.298557 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31918.298557 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31918.298557 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.icache.tags.replacements 911417 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 509.418391 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 7153262 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 911929 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 7.844100 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 28352545250 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.418391 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994958 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.994958 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 9022750 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 9022750 # Number of data accesses
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 7153262 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 7153262 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 7153262 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 7153262 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 7153262 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 7153262 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 957376 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 957376 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 957376 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 957376 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 957376 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 957376 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13452406105 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 13452406105 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 13452406105 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 13452406105 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 13452406105 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 13452406105 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 8110638 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 8110638 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 8110638 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 8110638 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 8110638 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 8110638 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118040 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.118040 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118040 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.118040 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118040 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.118040 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14051.329995 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 14051.329995 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14051.329995 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 14051.329995 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14051.329995 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 14051.329995 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 5687 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 195 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs 29.164103 # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45264 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::total 45264 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu0.inst 45264 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::total 45264 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu0.inst 45264 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::total 45264 # number of overall MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 912112 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 912112 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 912112 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 912112 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 912112 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 912112 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11511971092 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 11511971092 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11511971092 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 11511971092 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11511971092 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 11511971092 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.112459 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.112459 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.112459 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.112459 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.112459 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.112459 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12621.225345 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12621.225345 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12621.225345 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12621.225345 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12621.225345 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12621.225345 # average overall mshr miss latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.branchPred.lookups 3445639 # Number of BP lookups
|
|
system.cpu1.branchPred.condPredicted 3003437 # Number of conditional branches predicted
|
|
system.cpu1.branchPred.condIncorrect 69264 # Number of conditional branches incorrect
|
|
system.cpu1.branchPred.BTBLookups 1910439 # Number of BTB lookups
|
|
system.cpu1.branchPred.BTBHits 836162 # Number of BTB hits
|
|
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu1.branchPred.BTBHitPct 43.768055 # BTB Hit Percentage
|
|
system.cpu1.branchPred.usedRAS 167186 # Number of times the RAS was used to get a target.
|
|
system.cpu1.branchPred.RASInCorrect 4809 # Number of incorrect RAS predictions.
|
|
system.cpu1.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu1.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu1.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu1.dtb.read_hits 1858276 # DTB read hits
|
|
system.cpu1.dtb.read_misses 10905 # DTB read misses
|
|
system.cpu1.dtb.read_acv 64 # DTB read access violations
|
|
system.cpu1.dtb.read_accesses 300263 # DTB read accesses
|
|
system.cpu1.dtb.write_hits 1193771 # DTB write hits
|
|
system.cpu1.dtb.write_misses 2902 # DTB write misses
|
|
system.cpu1.dtb.write_acv 104 # DTB write access violations
|
|
system.cpu1.dtb.write_accesses 125157 # DTB write accesses
|
|
system.cpu1.dtb.data_hits 3052047 # DTB hits
|
|
system.cpu1.dtb.data_misses 13807 # DTB misses
|
|
system.cpu1.dtb.data_acv 168 # DTB access violations
|
|
system.cpu1.dtb.data_accesses 425420 # DTB accesses
|
|
system.cpu1.itb.fetch_hits 529068 # ITB hits
|
|
system.cpu1.itb.fetch_misses 7485 # ITB misses
|
|
system.cpu1.itb.fetch_acv 158 # ITB acv
|
|
system.cpu1.itb.fetch_accesses 536553 # ITB accesses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.read_acv 0 # DTB read access violations
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.write_acv 0 # DTB write access violations
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.data_hits 0 # DTB hits
|
|
system.cpu1.itb.data_misses 0 # DTB misses
|
|
system.cpu1.itb.data_acv 0 # DTB access violations
|
|
system.cpu1.itb.data_accesses 0 # DTB accesses
|
|
system.cpu1.numCycles 14296923 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.fetch.icacheStallCycles 5827989 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu1.fetch.Insts 13624759 # Number of instructions fetch has processed
|
|
system.cpu1.fetch.Branches 3445639 # Number of branches that fetch encountered
|
|
system.cpu1.fetch.predictedBranches 1003348 # Number of branches that fetch has predicted taken
|
|
system.cpu1.fetch.Cycles 7312463 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu1.fetch.SquashCycles 270756 # Number of cycles fetch has spent squashing
|
|
system.cpu1.fetch.TlbCycles 304 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu1.fetch.MiscStallCycles 25051 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu1.fetch.PendingTrapStallCycles 299772 # Number of stall cycles due to pending traps
|
|
system.cpu1.fetch.PendingQuiesceStallCycles 60327 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR
|
|
system.cpu1.fetch.CacheLines 1551048 # Number of cache lines fetched
|
|
system.cpu1.fetch.IcacheSquashes 55046 # Number of outstanding Icache misses that were squashed
|
|
system.cpu1.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu1.fetch.rateDist::samples 13661307 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::mean 0.997325 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::stdev 2.404073 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::0 11273523 82.52% 82.52% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::1 149434 1.09% 83.62% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::2 236962 1.73% 85.35% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::3 182278 1.33% 86.68% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::4 319422 2.34% 89.02% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::5 124907 0.91% 89.94% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::6 138046 1.01% 90.95% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::7 169812 1.24% 92.19% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::8 1066923 7.81% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::total 13661307 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.branchRate 0.241006 # Number of branch fetches per cycle
|
|
system.cpu1.fetch.rate 0.952985 # Number of inst fetches per cycle
|
|
system.cpu1.decode.IdleCycles 4848979 # Number of cycles decode is idle
|
|
system.cpu1.decode.BlockedCycles 6756897 # Number of cycles decode is blocked
|
|
system.cpu1.decode.RunCycles 1724085 # Number of cycles decode is running
|
|
system.cpu1.decode.UnblockCycles 202692 # Number of cycles decode is unblocking
|
|
system.cpu1.decode.SquashCycles 128653 # Number of cycles decode is squashing
|
|
system.cpu1.decode.BranchResolved 104901 # Number of times decode resolved a branch
|
|
system.cpu1.decode.BranchMispred 6833 # Number of times decode detected a branch misprediction
|
|
system.cpu1.decode.DecodedInsts 11127112 # Number of instructions handled by decode
|
|
system.cpu1.decode.SquashedInsts 21450 # Number of squashed instructions handled by decode
|
|
system.cpu1.rename.SquashCycles 128653 # Number of cycles rename is squashing
|
|
system.cpu1.rename.IdleCycles 4991483 # Number of cycles rename is idle
|
|
system.cpu1.rename.BlockCycles 690115 # Number of cycles rename is blocking
|
|
system.cpu1.rename.serializeStallCycles 5206241 # count of cycles rename stalled for serializing inst
|
|
system.cpu1.rename.RunCycles 1784475 # Number of cycles rename is running
|
|
system.cpu1.rename.UnblockCycles 860338 # Number of cycles rename is unblocking
|
|
system.cpu1.rename.RenamedInsts 10551561 # Number of instructions processed by rename
|
|
system.cpu1.rename.ROBFullEvents 3558 # Number of times rename has blocked due to ROB full
|
|
system.cpu1.rename.IQFullEvents 63390 # Number of times rename has blocked due to IQ full
|
|
system.cpu1.rename.LQFullEvents 12017 # Number of times rename has blocked due to LQ full
|
|
system.cpu1.rename.SQFullEvents 381484 # Number of times rename has blocked due to SQ full
|
|
system.cpu1.rename.RenamedOperands 6914568 # Number of destination operands rename has renamed
|
|
system.cpu1.rename.RenameLookups 12620115 # Number of register rename lookups that rename has made
|
|
system.cpu1.rename.int_rename_lookups 12571129 # Number of integer rename lookups
|
|
system.cpu1.rename.fp_rename_lookups 43721 # Number of floating rename lookups
|
|
system.cpu1.rename.CommittedMaps 5829921 # Number of HB maps that are committed
|
|
system.cpu1.rename.UndoneMaps 1084639 # Number of HB maps that are undone due to squashing
|
|
system.cpu1.rename.serializingInsts 430965 # count of serializing insts renamed
|
|
system.cpu1.rename.tempSerializingInsts 39644 # count of temporary serializing insts renamed
|
|
system.cpu1.rename.skidInsts 1821487 # count of insts added to the skid buffer
|
|
system.cpu1.memDep0.insertedLoads 1910201 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.insertedStores 1273290 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.conflictingLoads 221141 # Number of conflicting loads.
|
|
system.cpu1.memDep0.conflictingStores 146764 # Number of conflicting stores.
|
|
system.cpu1.iq.iqInstsAdded 9284732 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu1.iq.iqNonSpecInstsAdded 487174 # Number of non-speculative instructions added to the IQ
|
|
system.cpu1.iq.iqInstsIssued 9053277 # Number of instructions issued
|
|
system.cpu1.iq.iqSquashedInstsIssued 20996 # Number of squashed instructions issued
|
|
system.cpu1.iq.iqSquashedInstsExamined 1498950 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu1.iq.iqSquashedOperandsExamined 731721 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu1.iq.iqSquashedNonSpecRemoved 360528 # Number of squashed non-spec instructions that were removed
|
|
system.cpu1.iq.issued_per_cycle::samples 13661307 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::mean 0.662695 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::stdev 1.384311 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::0 9895925 72.44% 72.44% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::1 1648518 12.07% 84.50% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::2 704790 5.16% 89.66% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::3 494622 3.62% 93.28% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::4 437905 3.21% 96.49% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::5 233549 1.71% 98.20% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::6 155573 1.14% 99.34% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::7 64890 0.47% 99.81% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::8 25535 0.19% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::total 13661307 # Number of insts issued each cycle
|
|
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntAlu 22279 8.85% 8.85% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntMult 0 0.00% 8.85% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.85% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.85% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.85% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.85% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.85% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.85% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.85% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.85% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.85% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.85% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.85% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.85% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.85% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.85% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.85% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.85% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.85% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.85% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.85% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.85% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.85% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.85% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.85% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.85% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.85% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.85% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.85% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemRead 136629 54.29% 63.14% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemWrite 92774 36.86% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.FU_type_0::No_OpClass 2817 0.03% 0.03% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntAlu 5609130 61.96% 61.99% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntMult 14890 0.16% 62.15% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.15% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatAdd 8778 0.10% 62.25% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.25% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.25% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.25% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatDiv 1408 0.02% 62.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemRead 1940639 21.44% 83.70% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemWrite 1217689 13.45% 97.15% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IprAccess 257926 2.85% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::total 9053277 # Type of FU issued
|
|
system.cpu1.iq.rate 0.633233 # Inst issue rate
|
|
system.cpu1.iq.fu_busy_cnt 251682 # FU busy when requested
|
|
system.cpu1.iq.fu_busy_rate 0.027800 # FU busy rate (busy events/executed inst)
|
|
system.cpu1.iq.int_inst_queue_reads 31870123 # Number of integer instruction queue reads
|
|
system.cpu1.iq.int_inst_queue_writes 11194643 # Number of integer instruction queue writes
|
|
system.cpu1.iq.int_inst_queue_wakeup_accesses 8718718 # Number of integer instruction queue wakeup accesses
|
|
system.cpu1.iq.fp_inst_queue_reads 170415 # Number of floating instruction queue reads
|
|
system.cpu1.iq.fp_inst_queue_writes 80450 # Number of floating instruction queue writes
|
|
system.cpu1.iq.fp_inst_queue_wakeup_accesses 78899 # Number of floating instruction queue wakeup accesses
|
|
system.cpu1.iq.int_alu_accesses 9210850 # Number of integer alu accesses
|
|
system.cpu1.iq.fp_alu_accesses 91292 # Number of floating point alu accesses
|
|
system.cpu1.iew.lsq.thread0.forwLoads 92092 # Number of loads that had data forwarded from stores
|
|
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.squashedLoads 283440 # Number of loads squashed
|
|
system.cpu1.iew.lsq.thread0.ignoredResponses 879 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu1.iew.lsq.thread0.memOrderViolation 4333 # Number of memory ordering violations
|
|
system.cpu1.iew.lsq.thread0.squashedStores 136775 # Number of stores squashed
|
|
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu1.iew.lsq.thread0.rescheduledLoads 421 # Number of loads that were rescheduled
|
|
system.cpu1.iew.lsq.thread0.cacheBlocked 73078 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu1.iew.iewSquashCycles 128653 # Number of cycles IEW is squashing
|
|
system.cpu1.iew.iewBlockCycles 295868 # Number of cycles IEW is blocking
|
|
system.cpu1.iew.iewUnblockCycles 364148 # Number of cycles IEW is unblocking
|
|
system.cpu1.iew.iewDispatchedInsts 10275512 # Number of instructions dispatched to IQ
|
|
system.cpu1.iew.iewDispSquashedInsts 29401 # Number of squashed instructions skipped by dispatch
|
|
system.cpu1.iew.iewDispLoadInsts 1910201 # Number of dispatched load instructions
|
|
system.cpu1.iew.iewDispStoreInsts 1273290 # Number of dispatched store instructions
|
|
system.cpu1.iew.iewDispNonSpecInsts 443383 # Number of dispatched non-speculative instructions
|
|
system.cpu1.iew.iewIQFullEvents 3815 # Number of times the IQ has become full, causing a stall
|
|
system.cpu1.iew.iewLSQFullEvents 359581 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu1.iew.memOrderViolationEvents 4333 # Number of memory order violations
|
|
system.cpu1.iew.predictedTakenIncorrect 31404 # Number of branches that were predicted taken incorrectly
|
|
system.cpu1.iew.predictedNotTakenIncorrect 95843 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu1.iew.branchMispredicts 127247 # Number of branch mispredicts detected at execute
|
|
system.cpu1.iew.iewExecutedInsts 8933578 # Number of executed instructions
|
|
system.cpu1.iew.iewExecLoadInsts 1876162 # Number of load instructions executed
|
|
system.cpu1.iew.iewExecSquashedInsts 119698 # Number of squashed instructions skipped in execute
|
|
system.cpu1.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu1.iew.exec_nop 503606 # number of nop insts executed
|
|
system.cpu1.iew.exec_refs 3078439 # number of memory reference insts executed
|
|
system.cpu1.iew.exec_branches 1318456 # Number of branches executed
|
|
system.cpu1.iew.exec_stores 1202277 # Number of stores executed
|
|
system.cpu1.iew.exec_rate 0.624860 # Inst execution rate
|
|
system.cpu1.iew.wb_sent 8830913 # cumulative count of insts sent to commit
|
|
system.cpu1.iew.wb_count 8797617 # cumulative count of insts written-back
|
|
system.cpu1.iew.wb_producers 4148200 # num instructions producing a value
|
|
system.cpu1.iew.wb_consumers 5856949 # num instructions consuming a value
|
|
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu1.iew.wb_rate 0.615350 # insts written-back per cycle
|
|
system.cpu1.iew.wb_fanout 0.708253 # average fanout of values written-back
|
|
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu1.commit.commitSquashedInsts 1592161 # The number of squashed insts skipped by commit
|
|
system.cpu1.commit.commitNonSpecStalls 126646 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu1.commit.branchMispredicts 116539 # The number of times a branch was mispredicted
|
|
system.cpu1.commit.committed_per_cycle::samples 13369044 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::mean 0.644454 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::stdev 1.620421 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::0 10245809 76.64% 76.64% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::1 1446725 10.82% 87.46% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::2 518907 3.88% 91.34% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::3 315988 2.36% 93.70% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::4 242120 1.81% 95.52% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::5 97246 0.73% 96.24% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::6 91600 0.69% 96.93% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::7 106270 0.79% 97.72% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::8 304379 2.28% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::total 13369044 # Number of insts commited each cycle
|
|
system.cpu1.commit.committedInsts 8615735 # Number of instructions committed
|
|
system.cpu1.commit.committedOps 8615735 # Number of ops (including micro ops) committed
|
|
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu1.commit.refs 2763276 # Number of memory references committed
|
|
system.cpu1.commit.loads 1626761 # Number of loads committed
|
|
system.cpu1.commit.membars 39485 # Number of memory barriers committed
|
|
system.cpu1.commit.branches 1225974 # Number of branches committed
|
|
system.cpu1.commit.fp_insts 77544 # Number of committed floating point instructions.
|
|
system.cpu1.commit.int_insts 7995429 # Number of committed integer instructions.
|
|
system.cpu1.commit.function_calls 135018 # Number of function calls committed.
|
|
system.cpu1.commit.op_class_0::No_OpClass 410738 4.77% 4.77% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IntAlu 5119196 59.42% 64.18% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IntMult 14466 0.17% 64.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatAdd 8774 0.10% 64.45% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.45% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.45% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.45% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatDiv 1408 0.02% 64.47% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.47% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.47% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.47% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.47% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.47% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.47% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.47% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.47% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.47% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.47% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.47% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.47% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.47% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.47% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.47% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.47% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.47% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.47% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.47% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.47% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.47% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::MemRead 1666246 19.34% 83.81% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::MemWrite 1136981 13.20% 97.01% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IprAccess 257926 2.99% 100.00% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::total 8615735 # Class of committed instruction
|
|
system.cpu1.commit.bw_lim_events 304379 # number cycles where commit BW limit reached
|
|
system.cpu1.rob.rob_reads 23176968 # The number of ROB reads
|
|
system.cpu1.rob.rob_writes 20704388 # The number of ROB writes
|
|
system.cpu1.timesIdled 112605 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu1.idleCycles 635616 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu1.quiesceCycles 3794578226 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu1.committedInsts 8207813 # Number of Instructions Simulated
|
|
system.cpu1.committedOps 8207813 # Number of Ops (including micro ops) Simulated
|
|
system.cpu1.cpi 1.741868 # CPI: Cycles Per Instruction
|
|
system.cpu1.cpi_total 1.741868 # CPI: Total CPI of All Threads
|
|
system.cpu1.ipc 0.574096 # IPC: Instructions Per Cycle
|
|
system.cpu1.ipc_total 0.574096 # IPC: Total IPC of All Threads
|
|
system.cpu1.int_regfile_reads 11535994 # number of integer regfile reads
|
|
system.cpu1.int_regfile_writes 6250844 # number of integer regfile writes
|
|
system.cpu1.fp_regfile_reads 43175 # number of floating regfile reads
|
|
system.cpu1.fp_regfile_writes 42684 # number of floating regfile writes
|
|
system.cpu1.misc_regfile_reads 891820 # number of misc regfile reads
|
|
system.cpu1.misc_regfile_writes 203240 # number of misc regfile writes
|
|
system.cpu1.dcache.tags.replacements 102439 # number of replacements
|
|
system.cpu1.dcache.tags.tagsinuse 489.756832 # Cycle average of tags in use
|
|
system.cpu1.dcache.tags.total_refs 2417231 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.tags.sampled_refs 102951 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.tags.avg_refs 23.479432 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.tags.warmup_cycle 1034185261500 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.tags.occ_blocks::cpu1.data 489.756832 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.956556 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_percent::total 0.956556 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 224 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu1.dcache.tags.tag_accesses 11476458 # Number of tag accesses
|
|
system.cpu1.dcache.tags.data_accesses 11476458 # Number of data accesses
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 1494681 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 1494681 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 855193 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 855193 # number of WriteReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 29899 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::total 29899 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 28520 # number of StoreCondReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::total 28520 # number of StoreCondReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 2349874 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 2349874 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 2349874 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 2349874 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 181396 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 181396 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 244262 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 244262 # number of WriteReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4731 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::total 4731 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2607 # number of StoreCondReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::total 2607 # number of StoreCondReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 425658 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 425658 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 425658 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 425658 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2290258065 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.ReadReq_miss_latency::total 2290258065 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9952106154 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::total 9952106154 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 46237999 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::total 46237999 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 22188385 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::total 22188385 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::cpu1.data 12242364219 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::total 12242364219 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::cpu1.data 12242364219 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::total 12242364219 # number of overall miss cycles
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 1676077 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 1676077 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 1099455 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 1099455 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 34630 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::total 34630 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 31127 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::total 31127 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 2775532 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 2775532 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 2775532 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 2775532 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.108227 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.108227 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.222166 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.222166 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.136616 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.136616 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.083754 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.083754 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.153361 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.153361 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.153361 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.153361 # miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12625.736317 # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12625.736317 # average ReadReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 40743.571059 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total 40743.571059 # average WriteReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9773.409216 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9773.409216 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8511.079785 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8511.079785 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 28761.034020 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::total 28761.034020 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 28761.034020 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::total 28761.034020 # average overall miss latency
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 574336 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 346 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 18255 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 8 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 31.461846 # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets 43.250000 # average number of cycles each access was blocked
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.writebacks::writebacks 70134 # number of writebacks
|
|
system.cpu1.dcache.writebacks::total 70134 # number of writebacks
|
|
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 110614 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_hits::total 110614 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 203686 # number of WriteReq MSHR hits
|
|
system.cpu1.dcache.WriteReq_mshr_hits::total 203686 # number of WriteReq MSHR hits
|
|
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 700 # number of LoadLockedReq MSHR hits
|
|
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 700 # number of LoadLockedReq MSHR hits
|
|
system.cpu1.dcache.demand_mshr_hits::cpu1.data 314300 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.demand_mshr_hits::total 314300 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.overall_mshr_hits::cpu1.data 314300 # number of overall MSHR hits
|
|
system.cpu1.dcache.overall_mshr_hits::total 314300 # number of overall MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 70782 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_misses::total 70782 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 40576 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::total 40576 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4031 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4031 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2607 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::total 2607 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::cpu1.data 111358 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::total 111358 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::cpu1.data 111358 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::total 111358 # number of overall MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 815361518 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 815361518 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1580599049 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1580599049 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 32399501 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 32399501 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 18277115 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 18277115 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2395960567 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::total 2395960567 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2395960567 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::total 2395960567 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 29330000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 29330000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 630993000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 630993000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 660323000 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 660323000 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042231 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042231 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036906 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036906 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.116402 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.116402 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.083754 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.083754 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040121 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total 0.040121 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040121 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total 0.040121 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11519.334266 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11519.334266 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38954.038077 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 38954.038077 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8037.583974 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8037.583974 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7010.784427 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7010.784427 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21515.836913 # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21515.836913 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21515.836913 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21515.836913 # average overall mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.icache.tags.replacements 211356 # number of replacements
|
|
system.cpu1.icache.tags.tagsinuse 472.195820 # Cycle average of tags in use
|
|
system.cpu1.icache.tags.total_refs 1331062 # Total number of references to valid blocks.
|
|
system.cpu1.icache.tags.sampled_refs 211865 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.tags.avg_refs 6.282595 # Average number of references to valid blocks.
|
|
system.cpu1.icache.tags.warmup_cycle 1880244277250 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.tags.occ_blocks::cpu1.inst 472.195820 # Average occupied blocks per requestor
|
|
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.922257 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_percent::total 0.922257 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::2 392 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id
|
|
system.cpu1.icache.tags.tag_accesses 1762968 # Number of tag accesses
|
|
system.cpu1.icache.tags.data_accesses 1762968 # Number of data accesses
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 1331062 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 1331062 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 1331062 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 1331062 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 1331062 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 1331062 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 219986 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 219986 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 219986 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 219986 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 219986 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 219986 # number of overall misses
|
|
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2974295730 # number of ReadReq miss cycles
|
|
system.cpu1.icache.ReadReq_miss_latency::total 2974295730 # number of ReadReq miss cycles
|
|
system.cpu1.icache.demand_miss_latency::cpu1.inst 2974295730 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_latency::total 2974295730 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.overall_miss_latency::cpu1.inst 2974295730 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_latency::total 2974295730 # number of overall miss cycles
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 1551048 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 1551048 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 1551048 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 1551048 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 1551048 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 1551048 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.141831 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.141831 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.141831 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.141831 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.141831 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.141831 # miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13520.386434 # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total 13520.386434 # average ReadReq miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13520.386434 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::total 13520.386434 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13520.386434 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::total 13520.386434 # average overall miss latency
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 613 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 40 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.325000 # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8066 # number of ReadReq MSHR hits
|
|
system.cpu1.icache.ReadReq_mshr_hits::total 8066 # number of ReadReq MSHR hits
|
|
system.cpu1.icache.demand_mshr_hits::cpu1.inst 8066 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.demand_mshr_hits::total 8066 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.overall_mshr_hits::cpu1.inst 8066 # number of overall MSHR hits
|
|
system.cpu1.icache.overall_mshr_hits::total 8066 # number of overall MSHR hits
|
|
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 211920 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_misses::total 211920 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::cpu1.inst 211920 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::total 211920 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::cpu1.inst 211920 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::total 211920 # number of overall MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2567742004 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::total 2567742004 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2567742004 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::total 2567742004 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2567742004 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::total 2567742004 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.136630 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.136630 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.136630 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::total 0.136630 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.136630 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::total 0.136630 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12116.562873 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12116.562873 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12116.562873 # average overall mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::total 12116.562873 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12116.562873 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::total 12116.562873 # average overall mshr miss latency
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.iobus.trans_dist::ReadReq 7375 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 7375 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 54477 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 12925 # Transaction distribution
|
|
system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11660 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 172 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18142 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 40244 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 123704 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 46640 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 149 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9071 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 72837 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 2734485 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 11011000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer22.occupancy 148000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 13500000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 5167000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer29.occupancy 242105442 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 27319000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 42037503 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 41698 # number of replacements
|
|
system.iocache.tags.tagsinuse 0.483577 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 1711318407000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::tsunami.ide 0.483577 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::tsunami.ide 0.030224 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.030224 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 375570 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 375570 # Number of data accesses
|
|
system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 178 # number of ReadReq misses
|
|
system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses
|
|
system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses
|
|
system.iocache.demand_misses::tsunami.ide 178 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 178 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::tsunami.ide 178 # number of overall misses
|
|
system.iocache.overall_misses::total 178 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::tsunami.ide 22300881 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 22300881 # number of ReadReq miss cycles
|
|
system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8783600058 # number of WriteInvalidateReq miss cycles
|
|
system.iocache.WriteInvalidateReq_miss_latency::total 8783600058 # number of WriteInvalidateReq miss cycles
|
|
system.iocache.demand_miss_latency::tsunami.ide 22300881 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 22300881 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::tsunami.ide 22300881 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 22300881 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::tsunami.ide 178 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 178 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::tsunami.ide 178 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 178 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125285.848315 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 125285.848315 # average ReadReq miss latency
|
|
system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211388.141558 # average WriteInvalidateReq miss latency
|
|
system.iocache.WriteInvalidateReq_avg_miss_latency::total 211388.141558 # average WriteInvalidateReq miss latency
|
|
system.iocache.demand_avg_miss_latency::tsunami.ide 125285.848315 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 125285.848315 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::tsunami.ide 125285.848315 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 125285.848315 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 73351 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 10036 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs 7.308788 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks::writebacks 41520 # number of writebacks
|
|
system.iocache.writebacks::total 41520 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses
|
|
system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
|
|
system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
|
|
system.iocache.demand_mshr_misses::tsunami.ide 178 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 178 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::tsunami.ide 178 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 178 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12879885 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 12879885 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6622894060 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6622894060 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::tsunami.ide 12879885 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 12879885 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::tsunami.ide 12879885 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 12879885 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses
|
|
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
|
|
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72358.904494 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 72358.904494 # average ReadReq mshr miss latency
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159388.093473 # average WriteInvalidateReq mshr miss latency
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159388.093473 # average WriteInvalidateReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72358.904494 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 72358.904494 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72358.904494 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 72358.904494 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.tags.replacements 346915 # number of replacements
|
|
system.l2c.tags.tagsinuse 65246.496404 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 2614060 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 412065 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 6.343805 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 7589002750 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 53536.501359 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 5301.488199 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 6124.882413 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 215.988746 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 67.635688 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.816902 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.080894 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.093458 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.003296 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.001032 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.995583 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1024 65150 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 223 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 2446 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 5392 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::3 7744 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::4 49345 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.994110 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 27379617 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 27379617 # Number of data accesses
|
|
system.l2c.ReadReq_hits::cpu0.inst 898215 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.data 742471 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.inst 210198 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.data 63927 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 1914811 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::writebacks 822887 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 822887 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 176 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 246 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 422 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu0.data 53 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu1.data 30 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 83 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 152332 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 25116 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 177448 # number of ReadExReq hits
|
|
system.l2c.demand_hits::cpu0.inst 898215 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 894803 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 210198 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 89043 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 2092259 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.inst 898215 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 894803 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 210198 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 89043 # number of overall hits
|
|
system.l2c.overall_hits::total 2092259 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.inst 13731 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.data 273058 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.inst 1686 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.data 819 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 289294 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_misses::cpu0.data 2683 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 1043 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 3726 # number of UpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu0.data 349 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu1.data 386 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 735 # number of SCUpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 112818 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 10944 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 123762 # number of ReadExReq misses
|
|
system.l2c.demand_misses::cpu0.inst 13731 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 385876 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 1686 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 11763 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 413056 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.inst 13731 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 385876 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 1686 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 11763 # number of overall misses
|
|
system.l2c.overall_misses::total 413056 # number of overall misses
|
|
system.l2c.ReadReq_miss_latency::cpu0.inst 1146699750 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.data 19948507750 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.inst 143666750 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.data 75193250 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::total 21314067500 # number of ReadReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu0.data 1596458 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 5835814 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::total 7432272 # number of UpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1194963 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 187494 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::total 1382457 # number of SCUpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 9983790515 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 1229173205 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 11212963720 # number of ReadExReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 1146699750 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 29932298265 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 143666750 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 1304366455 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 32527031220 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 1146699750 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 29932298265 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 143666750 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 1304366455 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 32527031220 # number of overall miss cycles
|
|
system.l2c.ReadReq_accesses::cpu0.inst 911946 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.data 1015529 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.inst 211884 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.data 64746 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 2204105 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::writebacks 822887 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 822887 # number of Writeback accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 2859 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 1289 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 4148 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu0.data 402 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu1.data 416 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 818 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 265150 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 36060 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 301210 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.inst 911946 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 1280679 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 211884 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 100806 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 2505315 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 911946 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 1280679 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 211884 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 100806 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 2505315 # number of overall (read+write) accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.inst 0.015057 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.data 0.268883 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.inst 0.007957 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.data 0.012649 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::total 0.131252 # miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.938440 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.809154 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.898264 # miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.868159 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.927885 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::total 0.898533 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.425487 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.303494 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.410883 # miss rate for ReadExReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.015057 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.301306 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.007957 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.116689 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.164872 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.015057 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.301306 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.007957 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.116689 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.164872 # miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 83511.743500 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.data 73055.935918 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 85211.595492 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.data 91811.050061 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::total 73676.147794 # average ReadReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 595.027208 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5595.219559 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 1994.705314 # average UpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3423.962751 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 485.735751 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::total 1880.893878 # average SCUpgradeReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 88494.659673 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 112314.803088 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 90601.022285 # average ReadExReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.inst 83511.743500 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.data 77569.732932 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 85211.595492 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 110887.227323 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 78747.267247 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.inst 83511.743500 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.data 77569.732932 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 85211.595492 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 110887.227323 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 78747.267247 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.writebacks::writebacks 83224 # number of writebacks
|
|
system.l2c.writebacks::total 83224 # number of writebacks
|
|
system.l2c.ReadReq_mshr_hits::cpu0.inst 9 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu1.inst 9 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::total 19 # number of ReadReq MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu0.inst 9 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::total 19 # number of demand (read+write) MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu0.inst 9 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::total 19 # number of overall MSHR hits
|
|
system.l2c.ReadReq_mshr_misses::cpu0.inst 13722 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu0.data 273058 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.inst 1677 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.data 818 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::total 289275 # number of ReadReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu0.data 2683 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 1043 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 3726 # number of UpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 349 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 386 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::total 735 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu0.data 112818 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 10944 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 123762 # number of ReadExReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.inst 13722 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.data 385876 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 1677 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 11762 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 413037 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.inst 13722 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.data 385876 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 1677 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 11762 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 413037 # number of overall MSHR misses
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 974652500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 16545106250 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 122062750 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 65122250 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::total 17706943750 # number of ReadReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 47889169 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 18491538 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 66380707 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6218348 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 6847885 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::total 13066233 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8604034485 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1094197795 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 9698232280 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.inst 974652500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.data 25149140735 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 122062750 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 1159320045 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 27405176030 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.inst 974652500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.data 25149140735 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 122062750 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 1159320045 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 27405176030 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1365620000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27118000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 1392738000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1999167500 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 591543000 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::total 2590710500 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3364787500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 618661000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::total 3983448500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015047 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.268883 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007915 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.012634 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.131244 # mshr miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.938440 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.809154 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.898264 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.868159 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.927885 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.898533 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.425487 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.303494 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.410883 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015047 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.301306 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007915 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.116680 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.164864 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015047 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.301306 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007915 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.116680 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.164864 # mshr miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71028.457951 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60591.911792 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72786.374478 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 79611.552567 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 61211.455363 # average ReadReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17849.112561 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17729.183126 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17815.541331 # average UpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17817.616046 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17740.634715 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17777.187755 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 76264.731559 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99981.523666 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 78361.955043 # average ReadExReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71028.457951 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 65174.151113 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72786.374478 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 98564.873746 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 66350.414200 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71028.457951 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 65174.151113 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72786.374478 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98564.873746 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 66350.414200 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadReq 296650 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 296572 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 12925 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 12925 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 124744 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 9402 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 5001 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 4742 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 123808 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 123481 # Transaction distribution
|
|
system.membus.trans_dist::BadAddressError 78 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40244 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 927766 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 156 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 968166 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1092983 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 72837 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31719616 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::total 31792453 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 37110021 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 10437 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 594010 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 594010 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 594010 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 36342500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 1279237311 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 100000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 2197321028 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 42525497 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.trans_dist::ReadReq 2231372 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 2231278 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 12925 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 12925 # Transaction distribution
|
|
system.toL2Bus.trans_dist::Writeback 822887 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteInvalidateReq 41587 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 9543 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeReq 5084 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 14627 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 302295 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 302295 # Transaction distribution
|
|
system.toL2Bus.trans_dist::BadAddressError 78 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1824058 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3369862 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 423804 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 296769 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 5914493 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58364544 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 130195442 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13560576 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10962579 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 213083141 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 72565 # Total snoops (count)
|
|
system.toL2Bus.snoop_fanout::samples 3405571 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 3.012264 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 0.110061 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::3 3363806 98.77% 98.77% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::4 41765 1.23% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 3405571 # Request fanout histogram
|
|
system.toL2Bus.reqLayer0.occupancy 2521355915 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks)
|
|
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 1371805405 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 2024294017 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.respLayer2.occupancy 318303496 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer3.occupancy 173244936 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 6519 # number of quiesce instructions executed
|
|
system.cpu0.kern.inst.hwrei 185119 # number of hwrei instructions executed
|
|
system.cpu0.kern.ipl_count::0 65685 40.48% 40.48% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::21 132 0.08% 40.56% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::22 1924 1.19% 41.75% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::30 154 0.09% 41.84% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::31 94359 58.16% 100.00% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::total 162254 # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_good::0 64617 49.22% 49.22% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::21 132 0.10% 49.32% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::22 1924 1.47% 50.78% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::30 154 0.12% 50.90% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::31 64464 49.10% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::total 131291 # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_ticks::0 1861341200000 97.74% 97.74% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::21 60253000 0.00% 97.75% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::22 540538500 0.03% 97.78% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::30 69963500 0.00% 97.78% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::31 42290129000 2.22% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::total 1904302084000 # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_used::0 0.983741 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::31 0.683178 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::total 0.809170 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.syscall::2 6 2.79% 2.79% # number of syscalls executed
|
|
system.cpu0.kern.syscall::3 18 8.37% 11.16% # number of syscalls executed
|
|
system.cpu0.kern.syscall::4 3 1.40% 12.56% # number of syscalls executed
|
|
system.cpu0.kern.syscall::6 29 13.49% 26.05% # number of syscalls executed
|
|
system.cpu0.kern.syscall::12 1 0.47% 26.51% # number of syscalls executed
|
|
system.cpu0.kern.syscall::15 1 0.47% 26.98% # number of syscalls executed
|
|
system.cpu0.kern.syscall::17 9 4.19% 31.16% # number of syscalls executed
|
|
system.cpu0.kern.syscall::19 6 2.79% 33.95% # number of syscalls executed
|
|
system.cpu0.kern.syscall::20 4 1.86% 35.81% # number of syscalls executed
|
|
system.cpu0.kern.syscall::23 2 0.93% 36.74% # number of syscalls executed
|
|
system.cpu0.kern.syscall::24 4 1.86% 38.60% # number of syscalls executed
|
|
system.cpu0.kern.syscall::33 7 3.26% 41.86% # number of syscalls executed
|
|
system.cpu0.kern.syscall::41 2 0.93% 42.79% # number of syscalls executed
|
|
system.cpu0.kern.syscall::45 35 16.28% 59.07% # number of syscalls executed
|
|
system.cpu0.kern.syscall::47 4 1.86% 60.93% # number of syscalls executed
|
|
system.cpu0.kern.syscall::48 7 3.26% 64.19% # number of syscalls executed
|
|
system.cpu0.kern.syscall::54 9 4.19% 68.37% # number of syscalls executed
|
|
system.cpu0.kern.syscall::58 1 0.47% 68.84% # number of syscalls executed
|
|
system.cpu0.kern.syscall::59 5 2.33% 71.16% # number of syscalls executed
|
|
system.cpu0.kern.syscall::71 32 14.88% 86.05% # number of syscalls executed
|
|
system.cpu0.kern.syscall::73 3 1.40% 87.44% # number of syscalls executed
|
|
system.cpu0.kern.syscall::74 9 4.19% 91.63% # number of syscalls executed
|
|
system.cpu0.kern.syscall::87 1 0.47% 92.09% # number of syscalls executed
|
|
system.cpu0.kern.syscall::90 1 0.47% 92.56% # number of syscalls executed
|
|
system.cpu0.kern.syscall::92 7 3.26% 95.81% # number of syscalls executed
|
|
system.cpu0.kern.syscall::97 2 0.93% 96.74% # number of syscalls executed
|
|
system.cpu0.kern.syscall::98 2 0.93% 97.67% # number of syscalls executed
|
|
system.cpu0.kern.syscall::132 2 0.93% 98.60% # number of syscalls executed
|
|
system.cpu0.kern.syscall::144 1 0.47% 99.07% # number of syscalls executed
|
|
system.cpu0.kern.syscall::147 2 0.93% 100.00% # number of syscalls executed
|
|
system.cpu0.kern.syscall::total 215 # number of syscalls executed
|
|
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu0.kern.callpal::wripir 255 0.15% 0.15% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrmces 1 0.00% 0.15% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrfen 1 0.00% 0.15% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.15% # number of callpals executed
|
|
system.cpu0.kern.callpal::swpctx 3502 2.05% 2.20% # number of callpals executed
|
|
system.cpu0.kern.callpal::tbi 43 0.03% 2.23% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrent 7 0.00% 2.23% # number of callpals executed
|
|
system.cpu0.kern.callpal::swpipl 155594 91.14% 93.38% # number of callpals executed
|
|
system.cpu0.kern.callpal::rdps 6351 3.72% 97.10% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrkgp 1 0.00% 97.10% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrusp 3 0.00% 97.10% # number of callpals executed
|
|
system.cpu0.kern.callpal::rdusp 7 0.00% 97.10% # number of callpals executed
|
|
system.cpu0.kern.callpal::whami 2 0.00% 97.10% # number of callpals executed
|
|
system.cpu0.kern.callpal::rti 4450 2.61% 99.71% # number of callpals executed
|
|
system.cpu0.kern.callpal::callsys 347 0.20% 99.91% # number of callpals executed
|
|
system.cpu0.kern.callpal::imb 148 0.09% 100.00% # number of callpals executed
|
|
system.cpu0.kern.callpal::total 170714 # number of callpals executed
|
|
system.cpu0.kern.mode_switch::kernel 6908 # number of protection mode switches
|
|
system.cpu0.kern.mode_switch::user 1181 # number of protection mode switches
|
|
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
|
|
system.cpu0.kern.mode_good::kernel 1181
|
|
system.cpu0.kern.mode_good::user 1181
|
|
system.cpu0.kern.mode_good::idle 0
|
|
system.cpu0.kern.mode_switch_good::kernel 0.170961 # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_switch_good::total 0.292001 # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_ticks::kernel 1901823094000 99.90% 99.90% # number of ticks spent at the given mode
|
|
system.cpu0.kern.mode_ticks::user 1927479500 0.10% 100.00% # number of ticks spent at the given mode
|
|
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
|
|
system.cpu0.kern.swap_context 3503 # number of times the context was actually changed
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 2448 # number of quiesce instructions executed
|
|
system.cpu1.kern.inst.hwrei 54000 # number of hwrei instructions executed
|
|
system.cpu1.kern.ipl_count::0 16487 36.42% 36.42% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::22 1922 4.25% 40.66% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::30 255 0.56% 41.23% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::31 26607 58.77% 100.00% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::total 45271 # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_good::0 16178 47.20% 47.20% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::22 1922 5.61% 52.80% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::30 255 0.74% 53.55% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::31 15923 46.45% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::total 34278 # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_ticks::0 1872287559000 98.31% 98.31% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::22 533777500 0.03% 98.34% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::30 116465000 0.01% 98.35% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::31 31498958000 1.65% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::total 1904436759500 # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_used::0 0.981258 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used::31 0.598452 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used::total 0.757173 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.syscall::2 2 1.80% 1.80% # number of syscalls executed
|
|
system.cpu1.kern.syscall::3 12 10.81% 12.61% # number of syscalls executed
|
|
system.cpu1.kern.syscall::4 1 0.90% 13.51% # number of syscalls executed
|
|
system.cpu1.kern.syscall::6 13 11.71% 25.23% # number of syscalls executed
|
|
system.cpu1.kern.syscall::17 6 5.41% 30.63% # number of syscalls executed
|
|
system.cpu1.kern.syscall::19 4 3.60% 34.23% # number of syscalls executed
|
|
system.cpu1.kern.syscall::20 2 1.80% 36.04% # number of syscalls executed
|
|
system.cpu1.kern.syscall::23 2 1.80% 37.84% # number of syscalls executed
|
|
system.cpu1.kern.syscall::24 2 1.80% 39.64% # number of syscalls executed
|
|
system.cpu1.kern.syscall::33 4 3.60% 43.24% # number of syscalls executed
|
|
system.cpu1.kern.syscall::45 19 17.12% 60.36% # number of syscalls executed
|
|
system.cpu1.kern.syscall::47 2 1.80% 62.16% # number of syscalls executed
|
|
system.cpu1.kern.syscall::48 3 2.70% 64.86% # number of syscalls executed
|
|
system.cpu1.kern.syscall::54 1 0.90% 65.77% # number of syscalls executed
|
|
system.cpu1.kern.syscall::59 2 1.80% 67.57% # number of syscalls executed
|
|
system.cpu1.kern.syscall::71 22 19.82% 87.39% # number of syscalls executed
|
|
system.cpu1.kern.syscall::74 7 6.31% 93.69% # number of syscalls executed
|
|
system.cpu1.kern.syscall::90 2 1.80% 95.50% # number of syscalls executed
|
|
system.cpu1.kern.syscall::92 2 1.80% 97.30% # number of syscalls executed
|
|
system.cpu1.kern.syscall::132 2 1.80% 99.10% # number of syscalls executed
|
|
system.cpu1.kern.syscall::144 1 0.90% 100.00% # number of syscalls executed
|
|
system.cpu1.kern.syscall::total 111 # number of syscalls executed
|
|
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu1.kern.callpal::wripir 154 0.33% 0.33% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrfen 1 0.00% 0.33% # number of callpals executed
|
|
system.cpu1.kern.callpal::swpctx 1023 2.18% 2.52% # number of callpals executed
|
|
system.cpu1.kern.callpal::tbi 10 0.02% 2.54% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrent 7 0.01% 2.55% # number of callpals executed
|
|
system.cpu1.kern.callpal::swpipl 40053 85.39% 87.95% # number of callpals executed
|
|
system.cpu1.kern.callpal::rdps 2403 5.12% 93.07% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrkgp 1 0.00% 93.07% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrusp 4 0.01% 93.08% # number of callpals executed
|
|
system.cpu1.kern.callpal::rdusp 2 0.00% 93.08% # number of callpals executed
|
|
system.cpu1.kern.callpal::whami 3 0.01% 93.09% # number of callpals executed
|
|
system.cpu1.kern.callpal::rti 3040 6.48% 99.57% # number of callpals executed
|
|
system.cpu1.kern.callpal::callsys 168 0.36% 99.93% # number of callpals executed
|
|
system.cpu1.kern.callpal::imb 32 0.07% 100.00% # number of callpals executed
|
|
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
|
|
system.cpu1.kern.callpal::total 46904 # number of callpals executed
|
|
system.cpu1.kern.mode_switch::kernel 1413 # number of protection mode switches
|
|
system.cpu1.kern.mode_switch::user 554 # number of protection mode switches
|
|
system.cpu1.kern.mode_switch::idle 2352 # number of protection mode switches
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|
system.cpu1.kern.mode_good::kernel 733
|
|
system.cpu1.kern.mode_good::user 554
|
|
system.cpu1.kern.mode_good::idle 179
|
|
system.cpu1.kern.mode_switch_good::kernel 0.518754 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good::idle 0.076105 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good::total 0.339430 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_ticks::kernel 4023798000 0.21% 0.21% # number of ticks spent at the given mode
|
|
system.cpu1.kern.mode_ticks::user 775821000 0.04% 0.25% # number of ticks spent at the given mode
|
|
system.cpu1.kern.mode_ticks::idle 1899637132500 99.75% 100.00% # number of ticks spent at the given mode
|
|
system.cpu1.kern.swap_context 1024 # number of times the context was actually changed
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|
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---------- End Simulation Statistics ----------
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