gem5/util/tlm/examples/master_port/tlm.py
Christian Menard 55f5c4dd8a misc: Clean up and complete the gem5<->SystemC-TLM bridge [2/10]
The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
 * Add the Master Port.  Add an example application that isslustrates its
 * use.

Testing Done: A simple example application consisting of a TLM traffic
generator and a gem5 memory is part of the patch.

Reviewed at http://reviews.gem5.org/r/3528/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
2017-02-09 19:15:33 -05:00

75 lines
2.7 KiB
Python

#
# Copyright (c) 2016, Dresden University of Technology (TU Dresden)
# All rights reserved.
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# modification, are permitted provided that the following conditions are
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# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
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# 2. Redistributions in binary form must reproduce the above copyright
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# 3. Neither the name of the copyright holder nor the names of its
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# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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#
# Authors: Christian Menard
#
import m5
from m5.objects import *
import os
# Base System Architecture:
# +-----+ ^
# | TLM | | TLM World
# +--+--+ | (see main.cc)
# | v
# +----------v-----------+ External Port (see sc_master_port.*)
# | Membus | ^
# +----------+-----------+ |
# | | gem5 World
# +---v----+ |
# | Memory | |
# +--------+ v
#
# Create a system with a Crossbar and a simple Memory:
system = System()
system.membus = IOXBar(width = 16)
system.physmem = SimpleMemory(range = AddrRange('512MB'))
system.clk_domain = SrcClockDomain(clock = '1.5GHz',
voltage_domain = VoltageDomain(voltage = '1V'))
# Create a external TLM port:
system.tlm = ExternalMaster()
system.tlm.port_type = "tlm_master"
system.tlm.port_data = "memory"
# Route the connections:
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
system.tlm.port = system.membus.slave
system.mem_mode = 'timing'
# Start the simulation:
root = Root(full_system = False, system = system)
m5.instantiate()
m5.simulate()