a217eba078
This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
188 lines
20 KiB
Text
188 lines
20 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.054141 # Number of seconds simulated
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sim_ticks 54141000000 # Number of ticks simulated
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final_tick 54141000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1737374 # Simulator instruction rate (inst/s)
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host_op_rate 1746027 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1038196846 # Simulator tick rate (ticks/s)
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host_mem_usage 439336 # Number of bytes of host memory used
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host_seconds 52.15 # Real time elapsed on the host
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sim_insts 90602407 # Number of instructions simulated
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sim_ops 91053638 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 431323080 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 90016598 # Number of bytes read from this memory
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system.physmem.bytes_read::total 521339678 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 431323080 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 431323080 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::cpu.data 18908138 # Number of bytes written to this memory
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system.physmem.bytes_written::total 18908138 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 107830770 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 22461532 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 130292302 # Number of read requests responded to by this memory
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system.physmem.num_writes::cpu.data 4738868 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 4738868 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 7966662603 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 1662632718 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 9629295321 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 7966662603 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 7966662603 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 349238802 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 349238802 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 7966662603 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 2011871521 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 9978534124 # Total bandwidth to/from this memory (bytes/s)
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system.membus.throughput 9978534124 # Throughput (bytes/s)
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system.membus.data_through_bus 540247816 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 442 # Number of system calls
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system.cpu.numCycles 108282001 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 90602407 # Number of instructions committed
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system.cpu.committedOps 91053638 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
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system.cpu.num_func_calls 112245 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls
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system.cpu.num_int_insts 72326352 # number of integer instructions
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system.cpu.num_fp_insts 48 # number of float instructions
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system.cpu.num_int_register_reads 124257699 # number of times the integer registers were read
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system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
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system.cpu.num_cc_register_reads 271814240 # number of times the CC registers were read
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system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written
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system.cpu.num_mem_refs 27220755 # number of memory refs
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system.cpu.num_load_insts 22475911 # Number of load instructions
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system.cpu.num_store_insts 4744844 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 108282001 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.Branches 18732304 # Number of branches fetched
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system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
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system.cpu.op_class::IntAlu 63822828 70.09% 70.09% # Class of executed instruction
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system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction
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system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction
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system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction
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system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
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system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
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system.cpu.op_class::total 91054080 # Class of executed instruction
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---------- End Simulation Statistics ----------
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