1364 lines
26 KiB
INI
1364 lines
26 KiB
INI
[root]
|
|
type=Root
|
|
children=system
|
|
eventq_index=0
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|
full_system=true
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|
sim_quantum=0
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time_sync_enable=false
|
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time_sync_period=100000000000
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time_sync_spin_threshold=100000000
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|
|
[system]
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type=LinuxArmSystem
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children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
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atags_addr=256
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boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
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boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
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boot_release_addr=65528
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cache_line_size=64
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clk_domain=system.clk_domain
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dtb_filename=
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early_kernel_symbols=false
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enable_context_switch_stats_dump=false
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eventq_index=0
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flags_addr=268435504
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gic_cpu_addr=520093952
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have_generic_timer=false
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have_large_asid_64=false
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have_lpae=false
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have_security=false
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have_virtualization=false
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highest_el_is_64=false
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init_param=0
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kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
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kernel_addr_check=true
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load_addr_mask=268435455
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load_offset=0
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machine_type=RealView_PBX
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mem_mode=timing
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mem_ranges=0:134217727
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memories=system.physmem system.realview.nvmem
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multi_proc=true
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num_work_ids=16
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panic_on_oops=true
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panic_on_panic=true
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phys_addr_range_64=40
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readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
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reset_addr_64=0
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symbolfile=
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work_begin_ckpt_count=0
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work_begin_cpu_id_exit=-1
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work_begin_exit_count=0
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work_cpus_ckpt_count=0
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work_end_ckpt_count=0
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work_end_exit_count=0
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work_item_id=-1
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system_port=system.membus.slave[0]
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[system.bridge]
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type=Bridge
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clk_domain=system.clk_domain
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delay=50000
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eventq_index=0
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ranges=268435456:520093695 1073741824:1610612735
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req_size=16
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resp_size=16
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master=system.iobus.slave[0]
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slave=system.membus.master[0]
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[system.cf0]
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type=IdeDisk
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children=image
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delay=1000000
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driveID=master
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eventq_index=0
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image=system.cf0.image
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[system.cf0.image]
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type=CowDiskImage
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children=child
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child=system.cf0.image.child
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eventq_index=0
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image_file=
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read_only=false
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table_size=65536
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[system.cf0.image.child]
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type=RawDiskImage
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eventq_index=0
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image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
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read_only=true
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[system.clk_domain]
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type=SrcClockDomain
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clock=1000
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domain_id=-1
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eventq_index=0
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init_perf_level=0
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voltage_domain=system.voltage_domain
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[system.cpu]
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type=DerivO3CPU
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children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
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LFSTSize=1024
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LQEntries=32
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LSQCheckLoads=true
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LSQDepCheckShift=4
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SQEntries=32
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SSITSize=1024
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activity=0
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backComSize=5
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branchPred=system.cpu.branchPred
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cachePorts=200
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checker=Null
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clk_domain=system.cpu_clk_domain
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commitToDecodeDelay=1
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commitToFetchDelay=1
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commitToIEWDelay=1
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commitToRenameDelay=1
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commitWidth=8
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cpu_id=0
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decodeToFetchDelay=1
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decodeToRenameDelay=1
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decodeWidth=8
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dispatchWidth=8
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do_checkpoint_insts=true
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do_quiesce=true
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do_statistics_insts=true
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dstage2_mmu=system.cpu.dstage2_mmu
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dtb=system.cpu.dtb
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eventq_index=0
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fetchBufferSize=64
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fetchToDecodeDelay=1
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fetchTrapLatency=1
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fetchWidth=8
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forwardComSize=5
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fuPool=system.cpu.fuPool
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function_trace=false
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function_trace_start=0
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iewToCommitDelay=1
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iewToDecodeDelay=1
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iewToFetchDelay=1
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iewToRenameDelay=1
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interrupts=system.cpu.interrupts
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isa=system.cpu.isa
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issueToExecuteDelay=1
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issueWidth=8
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istage2_mmu=system.cpu.istage2_mmu
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itb=system.cpu.itb
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max_insts_all_threads=0
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max_insts_any_thread=0
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max_loads_all_threads=0
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max_loads_any_thread=0
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needsTSO=false
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numIQEntries=64
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numPhysCCRegs=0
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numPhysFloatRegs=256
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numPhysIntRegs=256
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numROBEntries=192
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numRobs=1
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numThreads=1
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profile=0
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progress_interval=0
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renameToDecodeDelay=1
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renameToFetchDelay=1
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renameToIEWDelay=2
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renameToROBDelay=1
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renameWidth=8
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simpoint_start_insts=
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smtCommitPolicy=RoundRobin
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smtFetchPolicy=SingleThread
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smtIQPolicy=Partitioned
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smtIQThreshold=100
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smtLSQPolicy=Partitioned
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smtLSQThreshold=100
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smtNumFetchingThreads=1
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smtROBPolicy=Partitioned
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smtROBThreshold=100
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socket_id=0
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squashWidth=8
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store_set_clear_period=250000
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switched_out=false
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system=system
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tracer=system.cpu.tracer
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trapLatency=13
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wbDepth=1
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wbWidth=8
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workload=
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dcache_port=system.cpu.dcache.cpu_side
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icache_port=system.cpu.icache.cpu_side
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[system.cpu.branchPred]
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type=BranchPredictor
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BTBEntries=4096
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BTBTagSize=16
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RASSize=16
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choiceCtrBits=2
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choicePredictorSize=8192
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eventq_index=0
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globalCtrBits=2
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globalPredictorSize=8192
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instShiftAmt=2
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localCtrBits=2
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localHistoryTableSize=2048
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localPredictorSize=2048
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numThreads=1
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predType=tournament
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[system.cpu.dcache]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=4
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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sequential_access=false
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size=32768
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system=system
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tags=system.cpu.dcache.tags
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu.dcache_port
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mem_side=system.cpu.toL2Bus.slave[1]
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[system.cpu.dcache.tags]
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type=LRU
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assoc=4
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block_size=64
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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hit_latency=2
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sequential_access=false
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size=32768
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[system.cpu.dstage2_mmu]
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type=ArmStage2MMU
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children=stage2_tlb
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eventq_index=0
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stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
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tlb=system.cpu.dtb
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[system.cpu.dstage2_mmu.stage2_tlb]
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type=ArmTLB
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children=walker
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eventq_index=0
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is_stage2=true
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size=32
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walker=system.cpu.dstage2_mmu.stage2_tlb.walker
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[system.cpu.dstage2_mmu.stage2_tlb.walker]
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type=ArmTableWalker
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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is_stage2=true
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num_squash_per_cycle=2
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sys=system
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port=system.cpu.toL2Bus.slave[5]
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[system.cpu.dtb]
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type=ArmTLB
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children=walker
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eventq_index=0
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is_stage2=false
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size=64
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walker=system.cpu.dtb.walker
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[system.cpu.dtb.walker]
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type=ArmTableWalker
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clk_domain=system.cpu_clk_domain
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eventq_index=0
|
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is_stage2=false
|
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num_squash_per_cycle=2
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sys=system
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port=system.cpu.toL2Bus.slave[3]
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[system.cpu.fuPool]
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type=FUPool
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children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
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FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
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eventq_index=0
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[system.cpu.fuPool.FUList0]
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type=FUDesc
|
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children=opList
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count=6
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eventq_index=0
|
|
opList=system.cpu.fuPool.FUList0.opList
|
|
|
|
[system.cpu.fuPool.FUList0.opList]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=IntAlu
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList1]
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type=FUDesc
|
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children=opList0 opList1
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count=2
|
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eventq_index=0
|
|
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
|
|
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[system.cpu.fuPool.FUList1.opList0]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=IntMult
|
|
opLat=3
|
|
|
|
[system.cpu.fuPool.FUList1.opList1]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=19
|
|
opClass=IntDiv
|
|
opLat=20
|
|
|
|
[system.cpu.fuPool.FUList2]
|
|
type=FUDesc
|
|
children=opList0 opList1 opList2
|
|
count=4
|
|
eventq_index=0
|
|
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
|
|
|
[system.cpu.fuPool.FUList2.opList0]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=FloatAdd
|
|
opLat=2
|
|
|
|
[system.cpu.fuPool.FUList2.opList1]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=FloatCmp
|
|
opLat=2
|
|
|
|
[system.cpu.fuPool.FUList2.opList2]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=FloatCvt
|
|
opLat=2
|
|
|
|
[system.cpu.fuPool.FUList3]
|
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type=FUDesc
|
|
children=opList0 opList1 opList2
|
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count=2
|
|
eventq_index=0
|
|
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
|
|
|
[system.cpu.fuPool.FUList3.opList0]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=FloatMult
|
|
opLat=4
|
|
|
|
[system.cpu.fuPool.FUList3.opList1]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=12
|
|
opClass=FloatDiv
|
|
opLat=12
|
|
|
|
[system.cpu.fuPool.FUList3.opList2]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=24
|
|
opClass=FloatSqrt
|
|
opLat=24
|
|
|
|
[system.cpu.fuPool.FUList4]
|
|
type=FUDesc
|
|
children=opList
|
|
count=0
|
|
eventq_index=0
|
|
opList=system.cpu.fuPool.FUList4.opList
|
|
|
|
[system.cpu.fuPool.FUList4.opList]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=MemRead
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5]
|
|
type=FUDesc
|
|
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
|
count=4
|
|
eventq_index=0
|
|
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
|
|
|
[system.cpu.fuPool.FUList5.opList00]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdAdd
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList01]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdAddAcc
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList02]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdAlu
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList03]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdCmp
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList04]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdCvt
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList05]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdMisc
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList06]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdMult
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList07]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdMultAcc
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList08]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdShift
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList09]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdShiftAcc
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList10]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdSqrt
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList11]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdFloatAdd
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList12]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdFloatAlu
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList13]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdFloatCmp
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList14]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdFloatCvt
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList15]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdFloatDiv
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList16]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdFloatMisc
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList17]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdFloatMult
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList18]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdFloatMultAcc
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList5.opList19]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=SimdFloatSqrt
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList6]
|
|
type=FUDesc
|
|
children=opList
|
|
count=0
|
|
eventq_index=0
|
|
opList=system.cpu.fuPool.FUList6.opList
|
|
|
|
[system.cpu.fuPool.FUList6.opList]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=MemWrite
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList7]
|
|
type=FUDesc
|
|
children=opList0 opList1
|
|
count=4
|
|
eventq_index=0
|
|
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
|
|
|
[system.cpu.fuPool.FUList7.opList0]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=MemRead
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList7.opList1]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=1
|
|
opClass=MemWrite
|
|
opLat=1
|
|
|
|
[system.cpu.fuPool.FUList8]
|
|
type=FUDesc
|
|
children=opList
|
|
count=1
|
|
eventq_index=0
|
|
opList=system.cpu.fuPool.FUList8.opList
|
|
|
|
[system.cpu.fuPool.FUList8.opList]
|
|
type=OpDesc
|
|
eventq_index=0
|
|
issueLat=3
|
|
opClass=IprAccess
|
|
opLat=3
|
|
|
|
[system.cpu.icache]
|
|
type=BaseCache
|
|
children=tags
|
|
addr_ranges=0:18446744073709551615
|
|
assoc=1
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
forward_snoops=true
|
|
hit_latency=2
|
|
is_top_level=true
|
|
max_miss_count=0
|
|
mshrs=4
|
|
prefetch_on_access=false
|
|
prefetcher=Null
|
|
response_latency=2
|
|
sequential_access=false
|
|
size=32768
|
|
system=system
|
|
tags=system.cpu.icache.tags
|
|
tgts_per_mshr=20
|
|
two_queue=false
|
|
write_buffers=8
|
|
cpu_side=system.cpu.icache_port
|
|
mem_side=system.cpu.toL2Bus.slave[0]
|
|
|
|
[system.cpu.icache.tags]
|
|
type=LRU
|
|
assoc=1
|
|
block_size=64
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
hit_latency=2
|
|
sequential_access=false
|
|
size=32768
|
|
|
|
[system.cpu.interrupts]
|
|
type=ArmInterrupts
|
|
eventq_index=0
|
|
|
|
[system.cpu.isa]
|
|
type=ArmISA
|
|
eventq_index=0
|
|
fpsid=1090793632
|
|
id_aa64afr0_el1=0
|
|
id_aa64afr1_el1=0
|
|
id_aa64dfr0_el1=1052678
|
|
id_aa64dfr1_el1=0
|
|
id_aa64isar0_el1=0
|
|
id_aa64isar1_el1=0
|
|
id_aa64mmfr0_el1=15728642
|
|
id_aa64mmfr1_el1=0
|
|
id_aa64pfr0_el1=17
|
|
id_aa64pfr1_el1=0
|
|
id_isar0=34607377
|
|
id_isar1=34677009
|
|
id_isar2=555950401
|
|
id_isar3=17899825
|
|
id_isar4=268501314
|
|
id_isar5=0
|
|
id_mmfr0=270536963
|
|
id_mmfr1=0
|
|
id_mmfr2=19070976
|
|
id_mmfr3=34611729
|
|
id_pfr0=49
|
|
id_pfr1=4113
|
|
midr=1091551472
|
|
system=system
|
|
|
|
[system.cpu.istage2_mmu]
|
|
type=ArmStage2MMU
|
|
children=stage2_tlb
|
|
eventq_index=0
|
|
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
|
tlb=system.cpu.itb
|
|
|
|
[system.cpu.istage2_mmu.stage2_tlb]
|
|
type=ArmTLB
|
|
children=walker
|
|
eventq_index=0
|
|
is_stage2=true
|
|
size=32
|
|
walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
|
|
|
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
|
type=ArmTableWalker
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
is_stage2=true
|
|
num_squash_per_cycle=2
|
|
sys=system
|
|
port=system.cpu.toL2Bus.slave[4]
|
|
|
|
[system.cpu.itb]
|
|
type=ArmTLB
|
|
children=walker
|
|
eventq_index=0
|
|
is_stage2=false
|
|
size=64
|
|
walker=system.cpu.itb.walker
|
|
|
|
[system.cpu.itb.walker]
|
|
type=ArmTableWalker
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
is_stage2=false
|
|
num_squash_per_cycle=2
|
|
sys=system
|
|
port=system.cpu.toL2Bus.slave[2]
|
|
|
|
[system.cpu.l2cache]
|
|
type=BaseCache
|
|
children=tags
|
|
addr_ranges=0:18446744073709551615
|
|
assoc=8
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
forward_snoops=true
|
|
hit_latency=20
|
|
is_top_level=false
|
|
max_miss_count=0
|
|
mshrs=20
|
|
prefetch_on_access=false
|
|
prefetcher=Null
|
|
response_latency=20
|
|
sequential_access=false
|
|
size=4194304
|
|
system=system
|
|
tags=system.cpu.l2cache.tags
|
|
tgts_per_mshr=12
|
|
two_queue=false
|
|
write_buffers=8
|
|
cpu_side=system.cpu.toL2Bus.master[0]
|
|
mem_side=system.membus.slave[1]
|
|
|
|
[system.cpu.l2cache.tags]
|
|
type=LRU
|
|
assoc=8
|
|
block_size=64
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
hit_latency=20
|
|
sequential_access=false
|
|
size=4194304
|
|
|
|
[system.cpu.toL2Bus]
|
|
type=CoherentBus
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
header_cycles=1
|
|
system=system
|
|
use_default_range=false
|
|
width=32
|
|
master=system.cpu.l2cache.cpu_side
|
|
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
|
|
|
|
[system.cpu.tracer]
|
|
type=ExeTracer
|
|
eventq_index=0
|
|
|
|
[system.cpu_clk_domain]
|
|
type=SrcClockDomain
|
|
clock=500
|
|
domain_id=-1
|
|
eventq_index=0
|
|
init_perf_level=0
|
|
voltage_domain=system.voltage_domain
|
|
|
|
[system.dvfs_handler]
|
|
type=DVFSHandler
|
|
domains=
|
|
enable=false
|
|
eventq_index=0
|
|
sys_clk_domain=system.clk_domain
|
|
transition_latency=100000000
|
|
|
|
[system.intrctrl]
|
|
type=IntrControl
|
|
eventq_index=0
|
|
sys=system
|
|
|
|
[system.iobus]
|
|
type=NoncoherentBus
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
header_cycles=1
|
|
use_default_range=false
|
|
width=8
|
|
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
|
|
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
|
|
|
|
[system.iocache]
|
|
type=BaseCache
|
|
children=tags
|
|
addr_ranges=0:134217727
|
|
assoc=8
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
forward_snoops=false
|
|
hit_latency=50
|
|
is_top_level=true
|
|
max_miss_count=0
|
|
mshrs=20
|
|
prefetch_on_access=false
|
|
prefetcher=Null
|
|
response_latency=50
|
|
sequential_access=false
|
|
size=1024
|
|
system=system
|
|
tags=system.iocache.tags
|
|
tgts_per_mshr=12
|
|
two_queue=false
|
|
write_buffers=8
|
|
cpu_side=system.iobus.master[25]
|
|
mem_side=system.membus.slave[2]
|
|
|
|
[system.iocache.tags]
|
|
type=LRU
|
|
assoc=8
|
|
block_size=64
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
hit_latency=50
|
|
sequential_access=false
|
|
size=1024
|
|
|
|
[system.membus]
|
|
type=CoherentBus
|
|
children=badaddr_responder
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
header_cycles=1
|
|
system=system
|
|
use_default_range=false
|
|
width=8
|
|
default=system.membus.badaddr_responder.pio
|
|
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
|
|
slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
|
|
|
|
[system.membus.badaddr_responder]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
fake_mem=false
|
|
pio_addr=0
|
|
pio_latency=100000
|
|
pio_size=8
|
|
ret_bad_addr=true
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=warn
|
|
pio=system.membus.default
|
|
|
|
[system.physmem]
|
|
type=DRAMCtrl
|
|
activation_limit=4
|
|
addr_mapping=RoRaBaChCo
|
|
banks_per_rank=8
|
|
burst_length=8
|
|
channels=1
|
|
clk_domain=system.clk_domain
|
|
conf_table_reported=true
|
|
device_bus_width=8
|
|
device_rowbuffer_size=1024
|
|
devices_per_rank=8
|
|
eventq_index=0
|
|
in_addr_map=true
|
|
max_accesses_per_row=16
|
|
mem_sched_policy=frfcfs
|
|
min_writes_per_switch=16
|
|
null=false
|
|
page_policy=open_adaptive
|
|
range=0:134217727
|
|
ranks_per_channel=2
|
|
read_buffer_size=32
|
|
static_backend_latency=10000
|
|
static_frontend_latency=10000
|
|
tBURST=5000
|
|
tCK=1250
|
|
tCL=13750
|
|
tRAS=35000
|
|
tRCD=13750
|
|
tREFI=7800000
|
|
tRFC=260000
|
|
tRP=13750
|
|
tRRD=6000
|
|
tRTP=7500
|
|
tRTW=2500
|
|
tWR=15000
|
|
tWTR=7500
|
|
tXAW=30000
|
|
write_buffer_size=64
|
|
write_high_thresh_perc=85
|
|
write_low_thresh_perc=50
|
|
port=system.membus.master[6]
|
|
|
|
[system.realview]
|
|
type=RealView
|
|
children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
|
eventq_index=0
|
|
intrctrl=system.intrctrl
|
|
max_mem_size=268435456
|
|
mem_start_addr=0
|
|
pci_cfg_base=0
|
|
system=system
|
|
|
|
[system.realview.a9scu]
|
|
type=A9SCU
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
pio_addr=520093696
|
|
pio_latency=100000
|
|
system=system
|
|
pio=system.membus.master[4]
|
|
|
|
[system.realview.aaci_fake]
|
|
type=AmbaFake
|
|
amba_id=0
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
ignore_access=false
|
|
pio_addr=268451840
|
|
pio_latency=100000
|
|
system=system
|
|
pio=system.iobus.master[21]
|
|
|
|
[system.realview.cf_ctrl]
|
|
type=IdeController
|
|
BAR0=402653184
|
|
BAR0LegacyIO=true
|
|
BAR0Size=16
|
|
BAR1=402653440
|
|
BAR1LegacyIO=true
|
|
BAR1Size=1
|
|
BAR2=1
|
|
BAR2LegacyIO=false
|
|
BAR2Size=8
|
|
BAR3=1
|
|
BAR3LegacyIO=false
|
|
BAR3Size=4
|
|
BAR4=1
|
|
BAR4LegacyIO=false
|
|
BAR4Size=16
|
|
BAR5=1
|
|
BAR5LegacyIO=false
|
|
BAR5Size=0
|
|
BIST=0
|
|
CacheLineSize=0
|
|
CapabilityPtr=0
|
|
CardbusCIS=0
|
|
ClassCode=1
|
|
Command=1
|
|
DeviceID=28945
|
|
ExpansionROM=0
|
|
HeaderType=0
|
|
InterruptLine=31
|
|
InterruptPin=1
|
|
LatencyTimer=0
|
|
MSICAPBaseOffset=0
|
|
MSICAPCapId=0
|
|
MSICAPMaskBits=0
|
|
MSICAPMsgAddr=0
|
|
MSICAPMsgCtrl=0
|
|
MSICAPMsgData=0
|
|
MSICAPMsgUpperAddr=0
|
|
MSICAPNextCapability=0
|
|
MSICAPPendingBits=0
|
|
MSIXCAPBaseOffset=0
|
|
MSIXCAPCapId=0
|
|
MSIXCAPNextCapability=0
|
|
MSIXMsgCtrl=0
|
|
MSIXPbaOffset=0
|
|
MSIXTableOffset=0
|
|
MaximumLatency=0
|
|
MinimumGrant=0
|
|
PMCAPBaseOffset=0
|
|
PMCAPCapId=0
|
|
PMCAPCapabilities=0
|
|
PMCAPCtrlStatus=0
|
|
PMCAPNextCapability=0
|
|
PXCAPBaseOffset=0
|
|
PXCAPCapId=0
|
|
PXCAPCapabilities=0
|
|
PXCAPDevCap2=0
|
|
PXCAPDevCapabilities=0
|
|
PXCAPDevCtrl=0
|
|
PXCAPDevCtrl2=0
|
|
PXCAPDevStatus=0
|
|
PXCAPLinkCap=0
|
|
PXCAPLinkCtrl=0
|
|
PXCAPLinkStatus=0
|
|
PXCAPNextCapability=0
|
|
ProgIF=133
|
|
Revision=0
|
|
Status=640
|
|
SubClassCode=1
|
|
SubsystemID=0
|
|
SubsystemVendorID=0
|
|
VendorID=32902
|
|
clk_domain=system.clk_domain
|
|
config_latency=20000
|
|
ctrl_offset=2
|
|
disks=system.cf0
|
|
eventq_index=0
|
|
io_shift=1
|
|
pci_bus=2
|
|
pci_dev=7
|
|
pci_func=0
|
|
pio_latency=30000
|
|
platform=system.realview
|
|
system=system
|
|
config=system.iobus.master[8]
|
|
dma=system.iobus.slave[2]
|
|
pio=system.iobus.master[7]
|
|
|
|
[system.realview.clcd]
|
|
type=Pl111
|
|
amba_id=1315089
|
|
clk_domain=system.clk_domain
|
|
enable_capture=true
|
|
eventq_index=0
|
|
gic=system.realview.gic
|
|
int_num=55
|
|
pio_addr=268566528
|
|
pio_latency=10000
|
|
pixel_clock=41667
|
|
system=system
|
|
vnc=system.vncserver
|
|
dma=system.iobus.slave[1]
|
|
pio=system.iobus.master[4]
|
|
|
|
[system.realview.dmac_fake]
|
|
type=AmbaFake
|
|
amba_id=0
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
ignore_access=false
|
|
pio_addr=268632064
|
|
pio_latency=100000
|
|
system=system
|
|
pio=system.iobus.master[9]
|
|
|
|
[system.realview.flash_fake]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
fake_mem=true
|
|
pio_addr=1073741824
|
|
pio_latency=100000
|
|
pio_size=536870912
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[24]
|
|
|
|
[system.realview.gic]
|
|
type=Pl390
|
|
clk_domain=system.clk_domain
|
|
cpu_addr=520093952
|
|
cpu_pio_delay=10000
|
|
dist_addr=520097792
|
|
dist_pio_delay=10000
|
|
eventq_index=0
|
|
int_latency=10000
|
|
it_lines=128
|
|
msix_addr=0
|
|
platform=system.realview
|
|
system=system
|
|
pio=system.membus.master[2]
|
|
|
|
[system.realview.gpio0_fake]
|
|
type=AmbaFake
|
|
amba_id=0
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
ignore_access=false
|
|
pio_addr=268513280
|
|
pio_latency=100000
|
|
system=system
|
|
pio=system.iobus.master[16]
|
|
|
|
[system.realview.gpio1_fake]
|
|
type=AmbaFake
|
|
amba_id=0
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
ignore_access=false
|
|
pio_addr=268517376
|
|
pio_latency=100000
|
|
system=system
|
|
pio=system.iobus.master[17]
|
|
|
|
[system.realview.gpio2_fake]
|
|
type=AmbaFake
|
|
amba_id=0
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
ignore_access=false
|
|
pio_addr=268521472
|
|
pio_latency=100000
|
|
system=system
|
|
pio=system.iobus.master[18]
|
|
|
|
[system.realview.kmi0]
|
|
type=Pl050
|
|
amba_id=1314896
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
gic=system.realview.gic
|
|
int_delay=1000000
|
|
int_num=52
|
|
is_mouse=false
|
|
pio_addr=268460032
|
|
pio_latency=100000
|
|
system=system
|
|
vnc=system.vncserver
|
|
pio=system.iobus.master[5]
|
|
|
|
[system.realview.kmi1]
|
|
type=Pl050
|
|
amba_id=1314896
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
gic=system.realview.gic
|
|
int_delay=1000000
|
|
int_num=53
|
|
is_mouse=true
|
|
pio_addr=268464128
|
|
pio_latency=100000
|
|
system=system
|
|
vnc=system.vncserver
|
|
pio=system.iobus.master[6]
|
|
|
|
[system.realview.l2x0_fake]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
fake_mem=false
|
|
pio_addr=520101888
|
|
pio_latency=100000
|
|
pio_size=4095
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.membus.master[3]
|
|
|
|
[system.realview.local_cpu_timer]
|
|
type=CpuLocalTimer
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
gic=system.realview.gic
|
|
int_num_timer=29
|
|
int_num_watchdog=30
|
|
pio_addr=520095232
|
|
pio_latency=100000
|
|
system=system
|
|
pio=system.membus.master[5]
|
|
|
|
[system.realview.mmc_fake]
|
|
type=AmbaFake
|
|
amba_id=0
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
ignore_access=false
|
|
pio_addr=268455936
|
|
pio_latency=100000
|
|
system=system
|
|
pio=system.iobus.master[22]
|
|
|
|
[system.realview.nvmem]
|
|
type=SimpleMemory
|
|
bandwidth=73.000000
|
|
clk_domain=system.clk_domain
|
|
conf_table_reported=false
|
|
eventq_index=0
|
|
in_addr_map=true
|
|
latency=30000
|
|
latency_var=0
|
|
null=false
|
|
range=2147483648:2214592511
|
|
port=system.membus.master[1]
|
|
|
|
[system.realview.realview_io]
|
|
type=RealViewCtrl
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
idreg=0
|
|
pio_addr=268435456
|
|
pio_latency=100000
|
|
proc_id0=201326592
|
|
proc_id1=201327138
|
|
system=system
|
|
pio=system.iobus.master[1]
|
|
|
|
[system.realview.rtc]
|
|
type=PL031
|
|
amba_id=3412017
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
gic=system.realview.gic
|
|
int_delay=100000
|
|
int_num=42
|
|
pio_addr=268529664
|
|
pio_latency=100000
|
|
system=system
|
|
time=Thu Jan 1 00:00:00 2009
|
|
pio=system.iobus.master[23]
|
|
|
|
[system.realview.sci_fake]
|
|
type=AmbaFake
|
|
amba_id=0
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
ignore_access=false
|
|
pio_addr=268492800
|
|
pio_latency=100000
|
|
system=system
|
|
pio=system.iobus.master[20]
|
|
|
|
[system.realview.smc_fake]
|
|
type=AmbaFake
|
|
amba_id=0
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
ignore_access=false
|
|
pio_addr=269357056
|
|
pio_latency=100000
|
|
system=system
|
|
pio=system.iobus.master[13]
|
|
|
|
[system.realview.sp810_fake]
|
|
type=AmbaFake
|
|
amba_id=0
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
ignore_access=true
|
|
pio_addr=268439552
|
|
pio_latency=100000
|
|
system=system
|
|
pio=system.iobus.master[14]
|
|
|
|
[system.realview.ssp_fake]
|
|
type=AmbaFake
|
|
amba_id=0
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
ignore_access=false
|
|
pio_addr=268488704
|
|
pio_latency=100000
|
|
system=system
|
|
pio=system.iobus.master[19]
|
|
|
|
[system.realview.timer0]
|
|
type=Sp804
|
|
amba_id=1316868
|
|
clk_domain=system.clk_domain
|
|
clock0=1000000
|
|
clock1=1000000
|
|
eventq_index=0
|
|
gic=system.realview.gic
|
|
int_num0=36
|
|
int_num1=36
|
|
pio_addr=268505088
|
|
pio_latency=100000
|
|
system=system
|
|
pio=system.iobus.master[2]
|
|
|
|
[system.realview.timer1]
|
|
type=Sp804
|
|
amba_id=1316868
|
|
clk_domain=system.clk_domain
|
|
clock0=1000000
|
|
clock1=1000000
|
|
eventq_index=0
|
|
gic=system.realview.gic
|
|
int_num0=37
|
|
int_num1=37
|
|
pio_addr=268509184
|
|
pio_latency=100000
|
|
system=system
|
|
pio=system.iobus.master[3]
|
|
|
|
[system.realview.uart]
|
|
type=Pl011
|
|
clk_domain=system.clk_domain
|
|
end_on_eot=false
|
|
eventq_index=0
|
|
gic=system.realview.gic
|
|
int_delay=100000
|
|
int_num=44
|
|
pio_addr=268472320
|
|
pio_latency=100000
|
|
platform=system.realview
|
|
system=system
|
|
terminal=system.terminal
|
|
pio=system.iobus.master[0]
|
|
|
|
[system.realview.uart1_fake]
|
|
type=AmbaFake
|
|
amba_id=0
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
ignore_access=false
|
|
pio_addr=268476416
|
|
pio_latency=100000
|
|
system=system
|
|
pio=system.iobus.master[10]
|
|
|
|
[system.realview.uart2_fake]
|
|
type=AmbaFake
|
|
amba_id=0
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
ignore_access=false
|
|
pio_addr=268480512
|
|
pio_latency=100000
|
|
system=system
|
|
pio=system.iobus.master[11]
|
|
|
|
[system.realview.uart3_fake]
|
|
type=AmbaFake
|
|
amba_id=0
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
ignore_access=false
|
|
pio_addr=268484608
|
|
pio_latency=100000
|
|
system=system
|
|
pio=system.iobus.master[12]
|
|
|
|
[system.realview.watchdog_fake]
|
|
type=AmbaFake
|
|
amba_id=0
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
ignore_access=false
|
|
pio_addr=268500992
|
|
pio_latency=100000
|
|
system=system
|
|
pio=system.iobus.master[15]
|
|
|
|
[system.terminal]
|
|
type=Terminal
|
|
eventq_index=0
|
|
intr_control=system.intrctrl
|
|
number=0
|
|
output=true
|
|
port=3456
|
|
|
|
[system.vncserver]
|
|
type=VncServer
|
|
eventq_index=0
|
|
frame_capture=false
|
|
number=0
|
|
port=5900
|
|
|
|
[system.voltage_domain]
|
|
type=VoltageDomain
|
|
eventq_index=0
|
|
voltage=1.000000
|
|
|