904 lines
100 KiB
Text
904 lines
100 KiB
Text
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---------- Begin Simulation Statistics ----------
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|
sim_seconds 1.858691 # Number of seconds simulated
|
|
sim_ticks 1858690543500 # Number of ticks simulated
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
host_inst_rate 131020 # Simulator instruction rate (inst/s)
|
|
host_tick_rate 4587017100 # Simulator tick rate (ticks/s)
|
|
host_mem_usage 315160 # Number of bytes of host memory used
|
|
host_seconds 405.21 # Real time elapsed on the host
|
|
sim_insts 53090369 # Number of instructions simulated
|
|
system.l2c.replacements 391395 # number of replacements
|
|
system.l2c.tagsinuse 34960.020004 # Cycle average of tags in use
|
|
system.l2c.total_refs 2406151 # Total number of references to valid blocks.
|
|
system.l2c.sampled_refs 424265 # Sample count of references to valid blocks.
|
|
system.l2c.avg_refs 5.671340 # Average number of references to valid blocks.
|
|
system.l2c.warmup_cycle 5621019000 # Cycle when the warmup percentage was hit.
|
|
system.l2c.occ_blocks::0 12378.384666 # Average occupied blocks per context
|
|
system.l2c.occ_blocks::1 22581.635338 # Average occupied blocks per context
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|
system.l2c.occ_percent::0 0.188879 # Average percentage of cache occupancy
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|
system.l2c.occ_percent::1 0.344568 # Average percentage of cache occupancy
|
|
system.l2c.ReadReq_hits::0 1801346 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 1801346 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::0 835143 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 835143 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::0 15 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 15 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::0 2 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::0 183109 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 183109 # number of ReadExReq hits
|
|
system.l2c.demand_hits::0 1984455 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::1 0 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 1984455 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::0 1984455 # number of overall hits
|
|
system.l2c.overall_hits::1 0 # number of overall hits
|
|
system.l2c.overall_hits::total 1984455 # number of overall hits
|
|
system.l2c.ReadReq_misses::0 308108 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 308108 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_misses::0 34 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 34 # number of UpgradeReq misses
|
|
system.l2c.ReadExReq_misses::0 116921 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 116921 # number of ReadExReq misses
|
|
system.l2c.demand_misses::0 425029 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::1 0 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 425029 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::0 425029 # number of overall misses
|
|
system.l2c.overall_misses::1 0 # number of overall misses
|
|
system.l2c.overall_misses::total 425029 # number of overall misses
|
|
system.l2c.ReadReq_miss_latency 16037313500 # number of ReadReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency 372000 # number of UpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency 6133457500 # number of ReadExReq miss cycles
|
|
system.l2c.demand_miss_latency 22170771000 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency 22170771000 # number of overall miss cycles
|
|
system.l2c.ReadReq_accesses::0 2109454 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 2109454 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::0 835143 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 835143 # number of Writeback accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::0 49 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 49 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::0 2 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::0 300030 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 300030 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::0 2409484 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 2409484 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::0 2409484 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 2409484 # number of overall (read+write) accesses
|
|
system.l2c.ReadReq_miss_rate::0 0.146061 # miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::0 0.693878 # miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::0 0.389698 # miss rate for ReadExReq accesses
|
|
system.l2c.demand_miss_rate::0 0.176398 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::0 0.176398 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_miss_latency::0 52050.948044 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::0 10941.176471 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::0 52458.134125 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
|
|
system.l2c.demand_avg_miss_latency::0 52162.960645 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total inf # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::0 52162.960645 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total inf # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.writebacks 117784 # number of writebacks
|
|
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.l2c.ReadReq_mshr_misses 308108 # number of ReadReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses 34 # number of UpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses 116921 # number of ReadExReq MSHR misses
|
|
system.l2c.demand_mshr_misses 425029 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses 425029 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.l2c.ReadReq_mshr_miss_latency 12333770000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency 1420000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency 4711661500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency 17045431500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency 17045431500 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency 810039500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency 1115188998 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency 1925228498 # number of overall MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::0 0.146061 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::0 0.693878 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::0 0.389698 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
|
|
system.l2c.demand_mshr_miss_rate::0 0.176398 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::0 0.176398 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_mshr_miss_latency 40030.671063 # average ReadReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency 41764.705882 # average UpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency 40297.820751 # average ReadExReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency 40104.161128 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency 40104.161128 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
|
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.iocache.replacements 41685 # number of replacements
|
|
system.iocache.tagsinuse 1.266648 # Cycle average of tags in use
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
|
|
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.warmup_cycle 1708339298000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.occ_blocks::1 1.266648 # Average occupied blocks per context
|
|
system.iocache.occ_percent::1 0.079165 # Average percentage of cache occupancy
|
|
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
|
|
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
|
|
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
|
|
system.iocache.overall_hits::0 0 # number of overall hits
|
|
system.iocache.overall_hits::1 0 # number of overall hits
|
|
system.iocache.overall_hits::total 0 # number of overall hits
|
|
system.iocache.ReadReq_misses::1 173 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
|
|
system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses
|
|
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
|
|
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::1 41725 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::0 0 # number of overall misses
|
|
system.iocache.overall_misses::1 41725 # number of overall misses
|
|
system.iocache.overall_misses::total 41725 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency 19939998 # number of ReadReq miss cycles
|
|
system.iocache.WriteReq_miss_latency 5722104806 # number of WriteReq miss cycles
|
|
system.iocache.demand_miss_latency 5742044804 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency 5742044804 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
|
|
system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::1 115260.104046 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::1 137709.491866 # average WriteReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
|
|
system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::1 137616.412319 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total inf # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::1 137616.412319 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total inf # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 64599068 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 10462 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs 6174.638501 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks 41512 # number of writebacks
|
|
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses
|
|
system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
|
|
system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.iocache.ReadReq_mshr_miss_latency 10943998 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_latency 3561252994 # number of WriteReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency 3572196992 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency 3572196992 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
|
|
system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency 63260.104046 # average ReadReq mshr miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency 85705.934588 # average WriteReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency 85612.869790 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency 85612.869790 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 10172213 # DTB read hits
|
|
system.cpu.dtb.read_misses 43494 # DTB read misses
|
|
system.cpu.dtb.read_acv 580 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 956567 # DTB read accesses
|
|
system.cpu.dtb.write_hits 6637652 # DTB write hits
|
|
system.cpu.dtb.write_misses 9272 # DTB write misses
|
|
system.cpu.dtb.write_acv 322 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 335213 # DTB write accesses
|
|
system.cpu.dtb.data_hits 16809865 # DTB hits
|
|
system.cpu.dtb.data_misses 52766 # DTB misses
|
|
system.cpu.dtb.data_acv 902 # DTB access violations
|
|
system.cpu.dtb.data_accesses 1291780 # DTB accesses
|
|
system.cpu.itb.fetch_hits 1342789 # ITB hits
|
|
system.cpu.itb.fetch_misses 39758 # ITB misses
|
|
system.cpu.itb.fetch_acv 1040 # ITB acv
|
|
system.cpu.itb.fetch_accesses 1382547 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.numCycles 117561370 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.BPredUnit.lookups 14512096 # Number of BP lookups
|
|
system.cpu.BPredUnit.condPredicted 12124763 # Number of conditional branches predicted
|
|
system.cpu.BPredUnit.condIncorrect 534985 # Number of conditional branches incorrect
|
|
system.cpu.BPredUnit.BTBLookups 13082442 # Number of BTB lookups
|
|
system.cpu.BPredUnit.BTBHits 6780681 # Number of BTB hits
|
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.BPredUnit.usedRAS 985415 # Number of times the RAS was used to get a target.
|
|
system.cpu.BPredUnit.RASInCorrect 44835 # Number of incorrect RAS predictions.
|
|
system.cpu.fetch.icacheStallCycles 29301348 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 74523128 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 14512096 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 7766096 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 14456496 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 2475230 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.BlockedCycles 37352483 # Number of cycles fetch has spent blocked
|
|
system.cpu.fetch.MiscStallCycles 32620 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 262284 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.PendingQuiesceStallCycles 336025 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 123 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 9183314 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 332127 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 83379045 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 0.893787 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 2.210786 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 68922549 82.66% 82.66% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 1028480 1.23% 83.90% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 2035774 2.44% 86.34% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 998762 1.20% 87.53% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 2982144 3.58% 91.11% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 700003 0.84% 91.95% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 807750 0.97% 92.92% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 1076941 1.29% 94.21% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 4826642 5.79% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 83379045 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.123443 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 0.633908 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 30625799 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 36960246 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 13171913 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 1025264 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 1595822 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 618911 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 42154 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 72819380 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 127184 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 1595822 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 31874108 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 12944384 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 19864625 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 12330385 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 4769719 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 68803114 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 4210 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 997602 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 1469982 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RenamedOperands 46108022 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 83655268 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 83175686 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 479582 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 38259780 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 7848234 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 1700711 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 251216 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 12962201 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 10843547 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 7060604 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 2097425 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 2214211 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 60377206 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 2118999 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 58263583 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 82757 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 9009938 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 4851831 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 1451256 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 83379045 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.698780 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.313076 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 56881095 68.22% 68.22% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 11965083 14.35% 82.57% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 5985120 7.18% 89.75% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 3573465 4.29% 94.03% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 2606291 3.13% 97.16% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 1333403 1.60% 98.76% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 786052 0.94% 99.70% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 188914 0.23% 99.93% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 59622 0.07% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 83379045 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 66647 11.94% 11.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 11.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 11.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 11.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 11.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 11.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 311938 55.88% 67.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 179673 32.18% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 39837502 68.37% 68.39% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 63640 0.11% 68.50% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.50% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 25605 0.04% 68.54% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.54% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.54% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.54% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 10651640 18.28% 86.83% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 6721971 11.54% 98.37% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 952308 1.63% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 58263583 # Type of FU issued
|
|
system.cpu.iq.rate 0.495601 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 558258 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.009582 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 199861715 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 71197744 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 56697880 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 685510 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 334104 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 327554 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 58457489 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 357071 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 546714 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1730283 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 13242 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 28963 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 668160 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 18982 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 168763 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 1595822 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 9001389 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 625458 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 66156357 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 866739 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 10843547 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 7060604 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 1871783 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 491434 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 13753 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 28963 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 389249 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 383472 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 772721 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 57555020 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 10245935 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 708562 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 3660152 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 16908045 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 9133755 # Number of branches executed
|
|
system.cpu.iew.exec_stores 6662110 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.489574 # Inst execution rate
|
|
system.cpu.iew.wb_sent 57159115 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 57025434 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 28218942 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 38051860 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.485069 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.741592 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitCommittedInsts 56284997 # The number of committed instructions
|
|
system.cpu.commit.commitSquashedInsts 9746037 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 667743 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 704725 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 81783223 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.688222 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.561458 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 59869495 73.21% 73.21% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 9271272 11.34% 84.54% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 5260342 6.43% 90.97% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 2449132 2.99% 93.97% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 1675900 2.05% 96.02% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 634046 0.78% 96.79% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 464374 0.57% 97.36% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 783725 0.96% 98.32% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 1374937 1.68% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 81783223 # Number of insts commited each cycle
|
|
system.cpu.commit.count 56284997 # Number of instructions committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 15505708 # Number of memory references committed
|
|
system.cpu.commit.loads 9113264 # Number of loads committed
|
|
system.cpu.commit.membars 227891 # Number of memory barriers committed
|
|
system.cpu.commit.branches 8461884 # Number of branches committed
|
|
system.cpu.commit.fp_insts 324250 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 52123418 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 744517 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 1374937 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 146188247 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 133660667 # The number of ROB writes
|
|
system.cpu.timesIdled 1252693 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 34182325 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 53090369 # Number of Instructions Simulated
|
|
system.cpu.committedInsts_total 53090369 # Number of Instructions Simulated
|
|
system.cpu.cpi 2.214363 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 2.214363 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.451597 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.451597 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 75435318 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 41215589 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 165687 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 167399 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 1995946 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 949866 # number of misc regfile writes
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.cpu.icache.replacements 1005223 # number of replacements
|
|
system.cpu.icache.tagsinuse 509.948854 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 8118172 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 1005732 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 8.071904 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 23367175000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::0 509.948854 # Average occupied blocks per context
|
|
system.cpu.icache.occ_percent::0 0.995994 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::0 8118173 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 8118173 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::0 8118173 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 8118173 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::0 8118173 # number of overall hits
|
|
system.cpu.icache.overall_hits::1 0 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 8118173 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::0 1065140 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1065140 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::0 1065140 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1065140 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::0 1065140 # number of overall misses
|
|
system.cpu.icache.overall_misses::1 0 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1065140 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency 15927800996 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency 15927800996 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency 15927800996 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::0 9183313 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 9183313 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::0 9183313 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 9183313 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::0 9183313 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 9183313 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::0 0.115986 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::0 0.115986 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::0 0.115986 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::0 14953.715940 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::0 14953.715940 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::0 14953.715940 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 1340497 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 122 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 10987.680328 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.writebacks 231 # number of writebacks
|
|
system.cpu.icache.ReadReq_mshr_hits 59195 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits 59195 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits 59195 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses 1005945 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses 1005945 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses 1005945 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 12050423497 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency 12050423497 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency 12050423497 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::0 0.109541 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::0 0.109541 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::0 0.109541 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11979.207111 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 11979.207111 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 11979.207111 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 1403249 # number of replacements
|
|
system.cpu.dcache.tagsinuse 511.995942 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 12177929 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 1403761 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 8.675215 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 19464000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::0 511.995942 # Average occupied blocks per context
|
|
system.cpu.dcache.occ_percent::0 0.999992 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::0 7541924 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 7541924 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::0 4223581 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 4223581 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::0 192169 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 192169 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::0 220074 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 220074 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::0 11765505 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 11765505 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::0 11765505 # number of overall hits
|
|
system.cpu.dcache.overall_hits::1 0 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 11765505 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::0 1785380 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1785380 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::0 1933647 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1933647 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::0 23245 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 23245 # number of LoadLockedReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::0 2 # number of StoreCondReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
|
|
system.cpu.dcache.demand_misses::0 3719027 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 3719027 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::0 3719027 # number of overall misses
|
|
system.cpu.dcache.overall_misses::1 0 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 3719027 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency 38531981000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency 57348648047 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency 361113000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency 28500 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency 95880629047 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency 95880629047 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::0 9327304 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 9327304 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::0 6157228 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 6157228 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::0 215414 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 215414 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::0 220076 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 220076 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::0 15484532 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 15484532 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::0 15484532 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 15484532 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::0 0.191414 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::0 0.314045 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::0 0.107908 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::0 0.000009 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_miss_rate::0 0.240177 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::0 0.240177 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::0 21581.949501 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::0 29658.282017 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15535.082814 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14250 # average StoreCondReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::0 25781.105931 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::0 25781.105931 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 904772827 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 266500 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 99710 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 9074.042995 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 22208.333333 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks 834912 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits 697810 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits 1634824 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits 5710 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits 2332634 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits 2332634 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses 1087570 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses 298823 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses 17535 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses 2 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses 1386393 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses 1386393 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 24793495000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 8488664327 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207086500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency 22000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency 33282159327 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency 33282159327 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904509000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1234461998 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 2138970998 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116601 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048532 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081401 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000009 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::0 0.089534 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::0 0.089534 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22797.148689 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28406.997878 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11809.894497 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 24006.294988 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 24006.294988 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 6434 # number of quiesce instructions executed
|
|
system.cpu.kern.inst.hwrei 211584 # number of hwrei instructions executed
|
|
system.cpu.kern.ipl_count::0 74877 40.96% 40.96% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::21 244 0.13% 41.09% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::22 1882 1.03% 42.12% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::31 105811 57.88% 100.00% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::total 182814 # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_good::0 73510 49.29% 49.29% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::21 244 0.16% 49.45% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::22 1882 1.26% 50.71% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::31 73514 49.29% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::total 149150 # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_ticks::0 1819958547500 97.92% 97.92% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::21 94089500 0.01% 97.92% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::22 384592500 0.02% 97.94% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::31 38252453500 2.06% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::total 1858689683000 # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_used::0 0.981743 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::31 0.694767 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
|
|
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
|
|
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
|
|
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
|
|
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
|
|
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
|
|
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
|
|
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
|
|
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
|
|
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
|
|
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
|
|
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
|
|
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
|
|
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
|
|
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
|
|
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
|
|
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
|
|
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
|
|
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
|
|
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
|
|
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
|
|
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
|
|
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
|
|
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
|
|
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
|
|
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
|
|
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
|
|
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
|
|
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
|
|
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
|
|
system.cpu.kern.syscall::total 326 # number of syscalls executed
|
|
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed
|
|
system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
|
|
system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
|
|
system.cpu.kern.callpal::swpipl 175475 91.19% 93.39% # number of callpals executed
|
|
system.cpu.kern.callpal::rdps 6787 3.53% 96.92% # number of callpals executed
|
|
system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed
|
|
system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed
|
|
system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed
|
|
system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed
|
|
system.cpu.kern.callpal::rti 5216 2.71% 99.64% # number of callpals executed
|
|
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
|
|
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
|
|
system.cpu.kern.callpal::total 192432 # number of callpals executed
|
|
system.cpu.kern.mode_switch::kernel 5955 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::user 1737 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::idle 2101 # number of protection mode switches
|
|
system.cpu.kern.mode_good::kernel 1906
|
|
system.cpu.kern.mode_good::user 1737
|
|
system.cpu.kern.mode_good::idle 169
|
|
system.cpu.kern.mode_switch_good::kernel 0.320067 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::idle 0.080438 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::total 1.400505 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_ticks::kernel 29488985500 1.59% 1.59% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::user 2865820500 0.15% 1.74% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::idle 1826334869000 98.26% 100.00% # number of ticks spent at the given mode
|
|
system.cpu.kern.swap_context 4175 # number of times the context was actually changed
|
|
|
|
---------- End Simulation Statistics ----------
|