7617dcf736
This provides a common initial status for all threads independent of CPU model (unlike the prior situation where CPUs initialized threads to inconsistent states). This mostly matters for SE mode; in FS mode, ISA-specific startupCPU() methods generally handle boot-time initialization of thread contexts (since the right thing to do is ISA-dependent).
1080 lines
26 KiB
C++
1080 lines
26 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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* Nathan Binkert
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*/
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#include "config/full_system.hh"
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#include "config/use_checker.hh"
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#include "arch/isa_traits.hh" // For MachInst
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#include "base/trace.hh"
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#include "cpu/base.hh"
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#include "cpu/simple_thread.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/ozone/cpu.hh"
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#include "cpu/quiesce_event.hh"
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#include "cpu/static_inst.hh"
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#include "sim/sim_object.hh"
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#include "sim/stats.hh"
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#if FULL_SYSTEM
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#include "arch/faults.hh"
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#include "arch/alpha/osfpal.hh"
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#include "arch/tlb.hh"
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#include "arch/types.hh"
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#include "arch/kernel_stats.hh"
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#include "arch/vtophys.hh"
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#include "base/callback.hh"
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#include "cpu/profile.hh"
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#include "sim/faults.hh"
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#include "sim/sim_events.hh"
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#include "sim/sim_exit.hh"
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#include "sim/system.hh"
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#else // !FULL_SYSTEM
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#include "sim/process.hh"
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#endif // FULL_SYSTEM
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#if USE_CHECKER
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#include "cpu/checker/thread_context.hh"
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#endif
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using namespace TheISA;
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template <class Impl>
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OzoneCPU<Impl>::TickEvent::TickEvent(OzoneCPU *c, int w)
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: Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), width(w)
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{
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}
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template <class Impl>
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void
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OzoneCPU<Impl>::TickEvent::process()
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{
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cpu->tick();
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}
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template <class Impl>
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const char *
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OzoneCPU<Impl>::TickEvent::description() const
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{
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return "OzoneCPU tick";
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}
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template <class Impl>
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OzoneCPU<Impl>::OzoneCPU(Params *p)
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#if FULL_SYSTEM
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: BaseCPU(p), thread(this, 0), tickEvent(this, p->width),
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#else
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: BaseCPU(p), thread(this, 0, p->workload[0], 0),
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tickEvent(this, p->width),
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#endif
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#ifndef NDEBUG
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instcount(0),
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#endif
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comm(5, 5)
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{
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frontEnd = new FrontEnd(p);
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backEnd = new BackEnd(p);
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_status = Idle;
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if (p->checker) {
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#if USE_CHECKER
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BaseCPU *temp_checker = p->checker;
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checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
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#if FULL_SYSTEM
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checker->setSystem(p->system);
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#endif
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checkerTC = new CheckerThreadContext<OzoneTC>(&ozoneTC, checker);
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thread.tc = checkerTC;
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tc = checkerTC;
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#else
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panic("Checker enabled but not compiled in!");
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#endif
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} else {
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// If checker is not being used, then the xcProxy points
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// directly to the CPU's ExecContext.
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checker = NULL;
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thread.tc = &ozoneTC;
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tc = &ozoneTC;
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}
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ozoneTC.cpu = this;
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ozoneTC.thread = &thread;
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thread.inSyscall = false;
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itb = p->itb;
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dtb = p->dtb;
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#if FULL_SYSTEM
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// Setup thread state stuff.
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thread.cpu = this;
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thread.setTid(0);
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thread.quiesceEvent = new EndQuiesceEvent(tc);
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system = p->system;
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physmem = p->system->physmem;
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if (p->profile) {
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thread.profile = new FunctionProfile(p->system->kernelSymtab);
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// @todo: This might be better as an ThreadContext instead of OzoneTC
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Callback *cb =
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new MakeCallback<OzoneTC,
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&OzoneTC::dumpFuncProfile>(&ozoneTC);
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registerExitCallback(cb);
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}
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// let's fill with a dummy node for now so we don't get a segfault
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// on the first cycle when there's no node available.
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static ProfileNode dummyNode;
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thread.profileNode = &dummyNode;
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thread.profilePC = 3;
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#else
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thread.cpu = this;
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#endif // !FULL_SYSTEM
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numInst = 0;
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startNumInst = 0;
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threadContexts.push_back(tc);
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frontEnd->setCPU(this);
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backEnd->setCPU(this);
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frontEnd->setTC(tc);
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backEnd->setTC(tc);
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frontEnd->setThreadState(&thread);
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backEnd->setThreadState(&thread);
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frontEnd->setCommBuffer(&comm);
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backEnd->setCommBuffer(&comm);
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frontEnd->setBackEnd(backEnd);
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backEnd->setFrontEnd(frontEnd);
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globalSeqNum = 1;
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lockFlag = 0;
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// Setup rename table, initializing all values to ready.
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for (int i = 0; i < TheISA::TotalNumRegs; ++i) {
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thread.renameTable[i] = new DynInst(this);
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thread.renameTable[i]->setResultReady();
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}
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frontEnd->renameTable.copyFrom(thread.renameTable);
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backEnd->renameTable.copyFrom(thread.renameTable);
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#if FULL_SYSTEM
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Port *mem_port;
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FunctionalPort *phys_port;
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VirtualPort *virt_port;
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phys_port = new FunctionalPort(csprintf("%s-%d-funcport",
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name(), 0));
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mem_port = system->physmem->getPort("functional");
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mem_port->setPeer(phys_port);
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phys_port->setPeer(mem_port);
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virt_port = new VirtualPort(csprintf("%s-%d-vport",
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name(), 0));
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mem_port = system->physmem->getPort("functional");
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mem_port->setPeer(virt_port);
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virt_port->setPeer(mem_port);
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thread.setPhysPort(phys_port);
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thread.setVirtPort(virt_port);
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#endif
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DPRINTF(OzoneCPU, "OzoneCPU: Created Ozone cpu object.\n");
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}
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template <class Impl>
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OzoneCPU<Impl>::~OzoneCPU()
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{
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}
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template <class Impl>
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void
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OzoneCPU<Impl>::switchOut()
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{
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BaseCPU::switchOut();
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switchCount = 0;
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// Front end needs state from back end, so switch out the back end first.
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backEnd->switchOut();
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frontEnd->switchOut();
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}
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template <class Impl>
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void
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OzoneCPU<Impl>::signalSwitched()
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{
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// Only complete the switchout when both the front end and back
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// end have signalled they are ready to switch.
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if (++switchCount == 2) {
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backEnd->doSwitchOut();
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frontEnd->doSwitchOut();
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#if USE_CHECKER
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if (checker)
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checker->switchOut();
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#endif
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_status = SwitchedOut;
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#ifndef NDEBUG
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// Loop through all registers
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for (int i = 0; i < AlphaISA::TotalNumRegs; ++i) {
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assert(thread.renameTable[i] == frontEnd->renameTable[i]);
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assert(thread.renameTable[i] == backEnd->renameTable[i]);
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DPRINTF(OzoneCPU, "Checking if register %i matches.\n", i);
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}
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#endif
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if (tickEvent.scheduled())
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tickEvent.squash();
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}
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assert(switchCount <= 2);
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}
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template <class Impl>
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void
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OzoneCPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
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{
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BaseCPU::takeOverFrom(oldCPU);
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thread.trapPending = false;
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thread.inSyscall = false;
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backEnd->takeOverFrom();
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frontEnd->takeOverFrom();
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frontEnd->renameTable.copyFrom(thread.renameTable);
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backEnd->renameTable.copyFrom(thread.renameTable);
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assert(!tickEvent.scheduled());
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#ifndef NDEBUG
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// Check rename table.
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for (int i = 0; i < TheISA::TotalNumRegs; ++i) {
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assert(thread.renameTable[i]->isResultReady());
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}
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#endif
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// @todo: Fix hardcoded number
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// Clear out any old information in time buffer.
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for (int i = 0; i < 15; ++i) {
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comm.advance();
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}
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// if any of this CPU's ThreadContexts are active, mark the CPU as
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// running and schedule its tick event.
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for (int i = 0; i < threadContexts.size(); ++i) {
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ThreadContext *tc = threadContexts[i];
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if (tc->status() == ThreadContext::Active &&
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_status != Running) {
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_status = Running;
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tickEvent.schedule(curTick);
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}
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}
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// Nothing running, change status to reflect that we're no longer
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// switched out.
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if (_status == SwitchedOut) {
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_status = Idle;
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}
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}
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template <class Impl>
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void
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OzoneCPU<Impl>::activateContext(int thread_num, int delay)
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{
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// Eventually change this in SMT.
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assert(thread_num == 0);
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assert(_status == Idle);
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notIdleFraction++;
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scheduleTickEvent(delay);
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_status = Running;
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#if FULL_SYSTEM
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if (thread.quiesceEvent && thread.quiesceEvent->scheduled())
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thread.quiesceEvent->deschedule();
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#endif
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thread.setStatus(ThreadContext::Active);
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frontEnd->wakeFromQuiesce();
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}
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template <class Impl>
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void
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OzoneCPU<Impl>::suspendContext(int thread_num)
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{
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// Eventually change this in SMT.
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assert(thread_num == 0);
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// @todo: Figure out how to initially set the status properly so
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// this is running.
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// assert(_status == Running);
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notIdleFraction--;
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unscheduleTickEvent();
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_status = Idle;
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}
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template <class Impl>
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void
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OzoneCPU<Impl>::deallocateContext(int thread_num, int delay)
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{
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// for now, these are equivalent
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suspendContext(thread_num);
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}
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template <class Impl>
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void
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OzoneCPU<Impl>::haltContext(int thread_num)
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{
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// for now, these are equivalent
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suspendContext(thread_num);
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}
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template <class Impl>
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void
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OzoneCPU<Impl>::regStats()
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{
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using namespace Stats;
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BaseCPU::regStats();
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thread.numInsts
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.name(name() + ".num_insts")
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.desc("Number of instructions executed")
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;
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thread.numMemRefs
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.name(name() + ".num_refs")
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.desc("Number of memory references")
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;
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notIdleFraction
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.name(name() + ".not_idle_fraction")
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.desc("Percentage of non-idle cycles")
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;
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idleFraction
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.name(name() + ".idle_fraction")
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.desc("Percentage of idle cycles")
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;
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quiesceCycles
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.name(name() + ".quiesce_cycles")
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.desc("Number of cycles spent in quiesce")
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;
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idleFraction = constant(1.0) - notIdleFraction;
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frontEnd->regStats();
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backEnd->regStats();
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}
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template <class Impl>
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void
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OzoneCPU<Impl>::resetStats()
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{
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// startNumInst = numInst;
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notIdleFraction = (_status != Idle);
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}
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template <class Impl>
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void
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OzoneCPU<Impl>::init()
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{
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BaseCPU::init();
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// Mark this as in syscall so it won't need to squash
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thread.inSyscall = true;
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#if FULL_SYSTEM
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for (int i = 0; i < threadContexts.size(); ++i) {
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ThreadContext *tc = threadContexts[i];
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// initialize CPU, including PC
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TheISA::initCPU(tc, tc->contextId());
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}
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#endif
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frontEnd->renameTable.copyFrom(thread.renameTable);
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backEnd->renameTable.copyFrom(thread.renameTable);
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thread.inSyscall = false;
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}
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template <class Impl>
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Port *
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OzoneCPU<Impl>::getPort(const std::string &if_name, int idx)
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{
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if (if_name == "dcache_port")
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return backEnd->getDcachePort();
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else if (if_name == "icache_port")
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return frontEnd->getIcachePort();
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else
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panic("No Such Port\n");
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}
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template <class Impl>
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void
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OzoneCPU<Impl>::serialize(std::ostream &os)
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{
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BaseCPU::serialize(os);
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SERIALIZE_ENUM(_status);
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nameOut(os, csprintf("%s.tc", name()));
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ozoneTC.serialize(os);
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nameOut(os, csprintf("%s.tickEvent", name()));
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tickEvent.serialize(os);
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// Use SimpleThread's ability to checkpoint to make it easier to
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// write out the registers. Also make this static so it doesn't
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// get instantiated multiple times (causes a panic in statistics).
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static SimpleThread temp;
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nameOut(os, csprintf("%s.xc.0", name()));
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temp.copyTC(thread.getTC());
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temp.serialize(os);
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}
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template <class Impl>
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void
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OzoneCPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion)
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{
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BaseCPU::unserialize(cp, section);
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UNSERIALIZE_ENUM(_status);
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ozoneTC.unserialize(cp, csprintf("%s.tc", section));
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tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
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// Use SimpleThread's ability to checkpoint to make it easier to
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// read in the registers. Also make this static so it doesn't
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// get instantiated multiple times (causes a panic in statistics).
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static SimpleThread temp;
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temp.copyTC(thread.getTC());
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temp.unserialize(cp, csprintf("%s.xc.0", section));
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thread.getTC()->copyArchRegs(temp.getTC());
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}
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template <class Impl>
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Fault
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OzoneCPU<Impl>::copySrcTranslate(Addr src)
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{
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panic("Copy not implemented!\n");
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return NoFault;
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#if 0
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static bool no_warn = true;
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int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
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// Only support block sizes of 64 atm.
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assert(blk_size == 64);
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int offset = src & (blk_size - 1);
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// Make sure block doesn't span page
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if (no_warn &&
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(src & TheISA::PageMask) != ((src + blk_size) & TheISA::PageMask) &&
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(src >> 40) != 0xfffffc) {
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warn("Copied block source spans pages %x.", src);
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no_warn = false;
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}
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memReq->reset(src & ~(blk_size - 1), blk_size);
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// translate to physical address
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Fault fault = tc->translateDataReadReq(memReq);
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assert(fault != Alignment_Fault);
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if (fault == NoFault) {
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tc->copySrcAddr = src;
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tc->copySrcPhysAddr = memReq->paddr + offset;
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} else {
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tc->copySrcAddr = 0;
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tc->copySrcPhysAddr = 0;
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}
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return fault;
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#endif
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}
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template <class Impl>
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Fault
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OzoneCPU<Impl>::copy(Addr dest)
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{
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panic("Copy not implemented!\n");
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return NoFault;
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#if 0
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static bool no_warn = true;
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int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
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// Only support block sizes of 64 atm.
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assert(blk_size == 64);
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uint8_t data[blk_size];
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//assert(tc->copySrcAddr);
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int offset = dest & (blk_size - 1);
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// Make sure block doesn't span page
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if (no_warn &&
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(dest & TheISA::PageMask) != ((dest + blk_size) & TheISA::PageMask) &&
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(dest >> 40) != 0xfffffc) {
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no_warn = false;
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warn("Copied block destination spans pages %x. ", dest);
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}
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memReq->reset(dest & ~(blk_size -1), blk_size);
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// translate to physical address
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Fault fault = tc->translateDataWriteReq(memReq);
|
|
|
|
assert(fault != Alignment_Fault);
|
|
|
|
if (fault == NoFault) {
|
|
Addr dest_addr = memReq->paddr + offset;
|
|
// Need to read straight from memory since we have more than 8 bytes.
|
|
memReq->paddr = tc->copySrcPhysAddr;
|
|
tc->mem->read(memReq, data);
|
|
memReq->paddr = dest_addr;
|
|
tc->mem->write(memReq, data);
|
|
if (dcacheInterface) {
|
|
memReq->cmd = Copy;
|
|
memReq->completionEvent = NULL;
|
|
memReq->paddr = tc->copySrcPhysAddr;
|
|
memReq->dest = dest_addr;
|
|
memReq->size = 64;
|
|
memReq->time = curTick;
|
|
dcacheInterface->access(memReq);
|
|
}
|
|
}
|
|
return fault;
|
|
#endif
|
|
}
|
|
|
|
#if FULL_SYSTEM
|
|
template <class Impl>
|
|
Addr
|
|
OzoneCPU<Impl>::dbg_vtophys(Addr addr)
|
|
{
|
|
return vtophys(tc, addr);
|
|
}
|
|
#endif // FULL_SYSTEM
|
|
|
|
#if FULL_SYSTEM
|
|
template <class Impl>
|
|
void
|
|
OzoneCPU<Impl>::wakeup()
|
|
{
|
|
if (_status == Idle) {
|
|
DPRINTF(IPI,"Suspended Processor awoke\n");
|
|
// thread.activate();
|
|
// Hack for now. Otherwise might have to go through the tc, or
|
|
// I need to figure out what's the right thing to call.
|
|
activateContext(thread.threadId(), 1);
|
|
}
|
|
}
|
|
#endif // FULL_SYSTEM
|
|
|
|
/* start simulation, program loaded, processor precise state initialized */
|
|
template <class Impl>
|
|
void
|
|
OzoneCPU<Impl>::tick()
|
|
{
|
|
DPRINTF(OzoneCPU, "\n\nOzoneCPU: Ticking cpu.\n");
|
|
|
|
_status = Running;
|
|
thread.renameTable[ZeroReg]->setIntResult(0);
|
|
thread.renameTable[ZeroReg+TheISA::FP_Base_DepTag]->
|
|
setDoubleResult(0.0);
|
|
|
|
comm.advance();
|
|
frontEnd->tick();
|
|
backEnd->tick();
|
|
|
|
// check for instruction-count-based events
|
|
comInstEventQueue[0]->serviceEvents(numInst);
|
|
|
|
if (!tickEvent.scheduled() && _status == Running)
|
|
tickEvent.schedule(curTick + ticks(1));
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
OzoneCPU<Impl>::squashFromTC()
|
|
{
|
|
thread.inSyscall = true;
|
|
backEnd->generateTCEvent();
|
|
}
|
|
|
|
#if !FULL_SYSTEM
|
|
template <class Impl>
|
|
void
|
|
OzoneCPU<Impl>::syscall(uint64_t &callnum)
|
|
{
|
|
// Not sure this copy is needed, depending on how the TC proxy is made.
|
|
thread.renameTable.copyFrom(backEnd->renameTable);
|
|
|
|
thread.inSyscall = true;
|
|
|
|
thread.funcExeInst++;
|
|
|
|
DPRINTF(OzoneCPU, "FuncExeInst: %i\n", thread.funcExeInst);
|
|
|
|
thread.process->syscall(callnum, tc);
|
|
|
|
thread.funcExeInst--;
|
|
|
|
thread.inSyscall = false;
|
|
|
|
frontEnd->renameTable.copyFrom(thread.renameTable);
|
|
backEnd->renameTable.copyFrom(thread.renameTable);
|
|
}
|
|
#else
|
|
template <class Impl>
|
|
Fault
|
|
OzoneCPU<Impl>::hwrei()
|
|
{
|
|
// Need to move this to ISA code
|
|
// May also need to make this per thread
|
|
|
|
lockFlag = false;
|
|
lockAddrList.clear();
|
|
thread.kernelStats->hwrei();
|
|
|
|
// FIXME: XXX check for interrupts? XXX
|
|
return NoFault;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
OzoneCPU<Impl>::processInterrupts()
|
|
{
|
|
// Check for interrupts here. For now can copy the code that
|
|
// exists within isa_fullsys_traits.hh. Also assume that thread 0
|
|
// is the one that handles the interrupts.
|
|
|
|
// Check if there are any outstanding interrupts
|
|
//Handle the interrupts
|
|
Fault interrupt = this->interrupts->getInterrupt(thread.getTC());
|
|
|
|
if (interrupt != NoFault) {
|
|
this->interrupts->updateIntrInfo(thread.getTC());
|
|
interrupt->invoke(thread.getTC());
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
bool
|
|
OzoneCPU<Impl>::simPalCheck(int palFunc)
|
|
{
|
|
// Need to move this to ISA code
|
|
// May also need to make this per thread
|
|
thread.kernelStats->callpal(palFunc, tc);
|
|
|
|
switch (palFunc) {
|
|
case PAL::halt:
|
|
haltContext(thread.threadId());
|
|
if (--System::numSystemsRunning == 0)
|
|
exitSimLoop("all cpus halted");
|
|
break;
|
|
|
|
case PAL::bpt:
|
|
case PAL::bugchk:
|
|
if (system->breakpoint())
|
|
return false;
|
|
break;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
#endif
|
|
|
|
template <class Impl>
|
|
BaseCPU *
|
|
OzoneCPU<Impl>::OzoneTC::getCpuPtr()
|
|
{
|
|
return cpu;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
OzoneCPU<Impl>::OzoneTC::setStatus(Status new_status)
|
|
{
|
|
thread->setStatus(new_status);
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
OzoneCPU<Impl>::OzoneTC::activate(int delay)
|
|
{
|
|
cpu->activateContext(thread->threadId(), delay);
|
|
}
|
|
|
|
/// Set the status to Suspended.
|
|
template <class Impl>
|
|
void
|
|
OzoneCPU<Impl>::OzoneTC::suspend()
|
|
{
|
|
cpu->suspendContext(thread->threadId());
|
|
}
|
|
|
|
/// Set the status to Halted.
|
|
template <class Impl>
|
|
void
|
|
OzoneCPU<Impl>::OzoneTC::halt()
|
|
{
|
|
cpu->haltContext(thread->threadId());
|
|
}
|
|
|
|
#if FULL_SYSTEM
|
|
template <class Impl>
|
|
void
|
|
OzoneCPU<Impl>::OzoneTC::dumpFuncProfile()
|
|
{
|
|
thread->dumpFuncProfile();
|
|
}
|
|
#endif
|
|
|
|
template <class Impl>
|
|
void
|
|
OzoneCPU<Impl>::OzoneTC::takeOverFrom(ThreadContext *old_context)
|
|
{
|
|
// some things should already be set up
|
|
#if FULL_SYSTEM
|
|
assert(getSystemPtr() == old_context->getSystemPtr());
|
|
#else
|
|
assert(getProcessPtr() == old_context->getProcessPtr());
|
|
#endif
|
|
|
|
// copy over functional state
|
|
setStatus(old_context->status());
|
|
copyArchRegs(old_context);
|
|
setCpuId(old_context->cpuId());
|
|
setContextId(old_context->contextId());
|
|
|
|
thread->setInst(old_context->getInst());
|
|
#if !FULL_SYSTEM
|
|
setFuncExeInst(old_context->readFuncExeInst());
|
|
#else
|
|
EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
|
|
if (other_quiesce) {
|
|
// Point the quiesce event's TC at this TC so that it wakes up
|
|
// the proper CPU.
|
|
other_quiesce->tc = this;
|
|
}
|
|
if (thread->quiesceEvent) {
|
|
thread->quiesceEvent->tc = this;
|
|
}
|
|
|
|
// Copy kernel stats pointer from old context.
|
|
thread->kernelStats = old_context->getKernelStats();
|
|
// storeCondFailures = 0;
|
|
cpu->lockFlag = false;
|
|
#endif
|
|
|
|
old_context->setStatus(ThreadContext::Halted);
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
OzoneCPU<Impl>::OzoneTC::regStats(const std::string &name)
|
|
{
|
|
#if FULL_SYSTEM
|
|
thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
|
|
thread->kernelStats->regStats(name + ".kern");
|
|
#endif
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
OzoneCPU<Impl>::OzoneTC::serialize(std::ostream &os)
|
|
{
|
|
// Once serialization is added, serialize the quiesce event and
|
|
// kernel stats. Will need to make sure there aren't multiple
|
|
// things that serialize them.
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
OzoneCPU<Impl>::OzoneTC::unserialize(Checkpoint *cp, const std::string §ion)
|
|
{ }
|
|
|
|
#if FULL_SYSTEM
|
|
template <class Impl>
|
|
EndQuiesceEvent *
|
|
OzoneCPU<Impl>::OzoneTC::getQuiesceEvent()
|
|
{
|
|
return thread->quiesceEvent;
|
|
}
|
|
|
|
template <class Impl>
|
|
Tick
|
|
OzoneCPU<Impl>::OzoneTC::readLastActivate()
|
|
{
|
|
return thread->lastActivate;
|
|
}
|
|
|
|
template <class Impl>
|
|
Tick
|
|
OzoneCPU<Impl>::OzoneTC::readLastSuspend()
|
|
{
|
|
return thread->lastSuspend;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
OzoneCPU<Impl>::OzoneTC::profileClear()
|
|
{
|
|
thread->profileClear();
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
OzoneCPU<Impl>::OzoneTC::profileSample()
|
|
{
|
|
thread->profileSample();
|
|
}
|
|
#endif
|
|
|
|
template <class Impl>
|
|
int
|
|
OzoneCPU<Impl>::OzoneTC::threadId()
|
|
{
|
|
return thread->threadId();
|
|
}
|
|
|
|
template <class Impl>
|
|
TheISA::MachInst
|
|
OzoneCPU<Impl>::OzoneTC::getInst()
|
|
{
|
|
return thread->getInst();
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
OzoneCPU<Impl>::OzoneTC::copyArchRegs(ThreadContext *tc)
|
|
{
|
|
thread->PC = tc->readPC();
|
|
thread->nextPC = tc->readNextPC();
|
|
|
|
cpu->frontEnd->setPC(thread->PC);
|
|
cpu->frontEnd->setNextPC(thread->nextPC);
|
|
|
|
// First loop through the integer registers.
|
|
for (int i = 0; i < TheISA::NumIntRegs; ++i) {
|
|
/* DPRINTF(OzoneCPU, "Copying over register %i, had data %lli, "
|
|
"now has data %lli.\n",
|
|
i, thread->renameTable[i]->readIntResult(),
|
|
tc->readIntReg(i));
|
|
*/
|
|
thread->renameTable[i]->setIntResult(tc->readIntReg(i));
|
|
}
|
|
|
|
// Then loop through the floating point registers.
|
|
for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
|
|
int fp_idx = i + TheISA::FP_Base_DepTag;
|
|
thread->renameTable[fp_idx]->setIntResult(tc->readFloatRegBits(i));
|
|
}
|
|
|
|
#if !FULL_SYSTEM
|
|
thread->funcExeInst = tc->readFuncExeInst();
|
|
#endif
|
|
|
|
// Need to copy the TC values into the current rename table,
|
|
// copy the misc regs.
|
|
copyMiscRegs(tc, this);
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
OzoneCPU<Impl>::OzoneTC::clearArchRegs()
|
|
{
|
|
panic("Unimplemented!");
|
|
}
|
|
|
|
template <class Impl>
|
|
uint64_t
|
|
OzoneCPU<Impl>::OzoneTC::readIntReg(int reg_idx)
|
|
{
|
|
return thread->renameTable[reg_idx]->readIntResult();
|
|
}
|
|
|
|
template <class Impl>
|
|
TheISA::FloatReg
|
|
OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx, int width)
|
|
{
|
|
int idx = reg_idx + TheISA::FP_Base_DepTag;
|
|
switch(width) {
|
|
case 32:
|
|
return thread->renameTable[idx]->readFloatResult();
|
|
case 64:
|
|
return thread->renameTable[idx]->readDoubleResult();
|
|
default:
|
|
panic("Unsupported width!");
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
double
|
|
OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx)
|
|
{
|
|
int idx = reg_idx + TheISA::FP_Base_DepTag;
|
|
return thread->renameTable[idx]->readFloatResult();
|
|
}
|
|
|
|
template <class Impl>
|
|
uint64_t
|
|
OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx, int width)
|
|
{
|
|
int idx = reg_idx + TheISA::FP_Base_DepTag;
|
|
return thread->renameTable[idx]->readIntResult();
|
|
}
|
|
|
|
template <class Impl>
|
|
uint64_t
|
|
OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx)
|
|
{
|
|
int idx = reg_idx + TheISA::FP_Base_DepTag;
|
|
return thread->renameTable[idx]->readIntResult();
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
OzoneCPU<Impl>::OzoneTC::setIntReg(int reg_idx, uint64_t val)
|
|
{
|
|
thread->renameTable[reg_idx]->setIntResult(val);
|
|
|
|
if (!thread->inSyscall) {
|
|
cpu->squashFromTC();
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val, int width)
|
|
{
|
|
int idx = reg_idx + TheISA::FP_Base_DepTag;
|
|
switch(width) {
|
|
case 32:
|
|
panic("Unimplemented!");
|
|
break;
|
|
case 64:
|
|
thread->renameTable[idx]->setDoubleResult(val);
|
|
break;
|
|
default:
|
|
panic("Unsupported width!");
|
|
}
|
|
|
|
if (!thread->inSyscall) {
|
|
cpu->squashFromTC();
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val)
|
|
{
|
|
int idx = reg_idx + TheISA::FP_Base_DepTag;
|
|
|
|
thread->renameTable[idx]->setDoubleResult(val);
|
|
|
|
if (!thread->inSyscall) {
|
|
cpu->squashFromTC();
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
OzoneCPU<Impl>::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val,
|
|
int width)
|
|
{
|
|
panic("Unimplemented!");
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
OzoneCPU<Impl>::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val)
|
|
{
|
|
panic("Unimplemented!");
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
OzoneCPU<Impl>::OzoneTC::setPC(Addr val)
|
|
{
|
|
thread->PC = val;
|
|
cpu->frontEnd->setPC(val);
|
|
|
|
if (!thread->inSyscall) {
|
|
cpu->squashFromTC();
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
OzoneCPU<Impl>::OzoneTC::setNextPC(Addr val)
|
|
{
|
|
thread->nextPC = val;
|
|
cpu->frontEnd->setNextPC(val);
|
|
|
|
if (!thread->inSyscall) {
|
|
cpu->squashFromTC();
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
TheISA::MiscReg
|
|
OzoneCPU<Impl>::OzoneTC::readMiscRegNoEffect(int misc_reg)
|
|
{
|
|
return thread->miscRegFile.readRegNoEffect(misc_reg);
|
|
}
|
|
|
|
template <class Impl>
|
|
TheISA::MiscReg
|
|
OzoneCPU<Impl>::OzoneTC::readMiscReg(int misc_reg)
|
|
{
|
|
return thread->miscRegFile.readReg(misc_reg, this);
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
OzoneCPU<Impl>::OzoneTC::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
|
|
{
|
|
// Needs to setup a squash event unless we're in syscall mode
|
|
thread->miscRegFile.setRegNoEffect(misc_reg, val);
|
|
|
|
if (!thread->inSyscall) {
|
|
cpu->squashFromTC();
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
OzoneCPU<Impl>::OzoneTC::setMiscReg(int misc_reg, const MiscReg &val)
|
|
{
|
|
// Needs to setup a squash event unless we're in syscall mode
|
|
thread->miscRegFile.setReg(misc_reg, val, this);
|
|
|
|
if (!thread->inSyscall) {
|
|
cpu->squashFromTC();
|
|
}
|
|
}
|