486 lines
16 KiB
C++
486 lines
16 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#include <list>
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#include <string>
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#include "base/refcnt.hh"
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#include "config/the_isa.hh"
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#include "cpu/base_dyn_inst.hh"
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#include "cpu/checker/cpu.hh"
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#include "cpu/simple_thread.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/static_inst.hh"
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#include "sim/sim_object.hh"
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#include "sim/stats.hh"
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#if FULL_SYSTEM
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#include "arch/vtophys.hh"
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#endif // FULL_SYSTEM
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using namespace std;
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//The CheckerCPU does alpha only
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using namespace AlphaISA;
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template <class DynInstPtr>
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void
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Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
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{
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DynInstPtr inst;
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// Either check this instruction, or add it to a list of
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// instructions waiting to be checked. Instructions must be
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// checked in program order, so if a store has committed yet not
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// completed, there may be some instructions that are waiting
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// behind it that have completed and must be checked.
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if (!instList.empty()) {
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if (youngestSN < completed_inst->seqNum) {
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DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%#x to list.\n",
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completed_inst->seqNum, completed_inst->readPC());
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instList.push_back(completed_inst);
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youngestSN = completed_inst->seqNum;
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}
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if (!instList.front()->isCompleted()) {
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return;
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} else {
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inst = instList.front();
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instList.pop_front();
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}
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} else {
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if (!completed_inst->isCompleted()) {
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if (youngestSN < completed_inst->seqNum) {
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DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%#x to list.\n",
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completed_inst->seqNum, completed_inst->readPC());
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instList.push_back(completed_inst);
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youngestSN = completed_inst->seqNum;
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}
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return;
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} else {
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if (youngestSN < completed_inst->seqNum) {
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inst = completed_inst;
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youngestSN = completed_inst->seqNum;
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} else {
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return;
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}
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}
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}
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unverifiedInst = inst;
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// Try to check all instructions that are completed, ending if we
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// run out of instructions to check or if an instruction is not
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// yet completed.
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while (1) {
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DPRINTF(Checker, "Processing instruction [sn:%lli] PC:%#x.\n",
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inst->seqNum, inst->readPC());
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unverifiedResult.integer = inst->readIntResult();
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unverifiedReq = inst->req;
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unverifiedMemData = inst->memData;
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numCycles++;
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Fault fault = NoFault;
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// maintain $r0 semantics
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thread->setIntReg(ZeroReg, 0);
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#ifdef TARGET_ALPHA
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thread->setFloatRegDouble(ZeroReg, 0.0);
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#endif // TARGET_ALPHA
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// Check if any recent PC changes match up with anything we
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// expect to happen. This is mostly to check if traps or
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// PC-based events have occurred in both the checker and CPU.
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if (changedPC) {
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DPRINTF(Checker, "Changed PC recently to %#x\n",
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thread->readPC());
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if (willChangePC) {
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if (newPC == thread->readPC()) {
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DPRINTF(Checker, "Changed PC matches expected PC\n");
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} else {
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warn("%lli: Changed PC does not match expected PC, "
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"changed: %#x, expected: %#x",
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curTick, thread->readPC(), newPC);
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CheckerCPU::handleError();
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}
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willChangePC = false;
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}
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changedPC = false;
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}
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if (changedNextPC) {
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DPRINTF(Checker, "Changed NextPC recently to %#x\n",
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thread->readNextPC());
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changedNextPC = false;
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}
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// Try to fetch the instruction
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#if FULL_SYSTEM
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#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0
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#else
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#define IFETCH_FLAGS(pc) 0
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#endif
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uint64_t fetch_PC = thread->readPC() & ~3;
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// set up memory request for instruction fetch
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memReq = new Request(inst->threadNumber, fetch_PC,
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sizeof(uint32_t),
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IFETCH_FLAGS(thread->readPC()),
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fetch_PC, thread->contextId(),
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inst->threadNumber);
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bool succeeded = itb->translateAtomic(memReq, thread);
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if (!succeeded) {
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if (inst->getFault() == NoFault) {
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// In this case the instruction was not a dummy
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// instruction carrying an ITB fault. In the single
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// threaded case the ITB should still be able to
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// translate this instruction; in the SMT case it's
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// possible that its ITB entry was kicked out.
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warn("%lli: Instruction PC %#x was not found in the ITB!",
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curTick, thread->readPC());
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handleError(inst);
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// go to the next instruction
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thread->setPC(thread->readNextPC());
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thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
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break;
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} else {
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// The instruction is carrying an ITB fault. Handle
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// the fault and see if our results match the CPU on
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// the next tick().
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fault = inst->getFault();
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}
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}
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if (fault == NoFault) {
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PacketPtr pkt = new Packet(memReq, Packet::ReadReq,
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Packet::Broadcast);
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pkt->dataStatic(&machInst);
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icachePort->sendFunctional(pkt);
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delete pkt;
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// keep an instruction count
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numInst++;
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// decode the instruction
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machInst = gtoh(machInst);
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// Checks that the instruction matches what we expected it to be.
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// Checks both the machine instruction and the PC.
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validateInst(inst);
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#if THE_ISA == ALPHA_ISA
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curStaticInst = StaticInst::decode(makeExtMI(machInst,
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thread->readPC()));
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#elif THE_ISA == SPARC_ISA
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curStaticInst = StaticInst::decode(makeExtMI(machInst,
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thread->getTC()));
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#endif
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#if FULL_SYSTEM
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thread->setInst(machInst);
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#endif // FULL_SYSTEM
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fault = inst->getFault();
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}
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// Discard fetch's memReq.
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delete memReq;
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memReq = NULL;
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// Either the instruction was a fault and we should process the fault,
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// or we should just go ahead execute the instruction. This assumes
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// that the instruction is properly marked as a fault.
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if (fault == NoFault) {
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thread->funcExeInst++;
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if (!inst->isUnverifiable())
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fault = curStaticInst->execute(this, NULL);
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// Checks to make sure instrution results are correct.
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validateExecution(inst);
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if (curStaticInst->isLoad()) {
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++numLoad;
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}
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}
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if (fault != NoFault) {
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#if FULL_SYSTEM
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fault->invoke(tc);
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willChangePC = true;
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newPC = thread->readPC();
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DPRINTF(Checker, "Fault, PC is now %#x\n", newPC);
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#endif
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} else {
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#if THE_ISA != MIPS_ISA
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// go to the next instruction
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thread->setPC(thread->readNextPC());
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thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
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#else
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// go to the next instruction
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thread->setPC(thread->readNextPC());
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thread->setNextPC(thread->readNextNPC());
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thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
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#endif
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}
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#if FULL_SYSTEM
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// @todo: Determine if these should happen only if the
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// instruction hasn't faulted. In the SimpleCPU case this may
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// not be true, but in the O3 or Ozone case this may be true.
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Addr oldpc;
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int count = 0;
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do {
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oldpc = thread->readPC();
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system->pcEventQueue.service(tc);
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count++;
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} while (oldpc != thread->readPC());
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if (count > 1) {
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willChangePC = true;
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newPC = thread->readPC();
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DPRINTF(Checker, "PC Event, PC is now %#x\n", newPC);
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}
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#endif
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// @todo: Optionally can check all registers. (Or just those
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// that have been modified).
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validateState();
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if (memReq) {
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delete memReq;
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memReq = NULL;
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}
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// Continue verifying instructions if there's another completed
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// instruction waiting to be verified.
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if (instList.empty()) {
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break;
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} else if (instList.front()->isCompleted()) {
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inst = instList.front();
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instList.pop_front();
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} else {
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break;
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}
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}
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unverifiedInst = NULL;
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}
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template <class DynInstPtr>
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void
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Checker<DynInstPtr>::switchOut()
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{
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instList.clear();
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}
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template <class DynInstPtr>
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void
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Checker<DynInstPtr>::takeOverFrom(BaseCPU *oldCPU)
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{
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}
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template <class DynInstPtr>
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void
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Checker<DynInstPtr>::validateInst(DynInstPtr &inst)
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{
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if (inst->readPC() != thread->readPC()) {
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warn("%lli: PCs do not match! Inst: %#x, checker: %#x",
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curTick, inst->readPC(), thread->readPC());
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if (changedPC) {
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warn("%lli: Changed PCs recently, may not be an error",
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curTick);
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} else {
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handleError(inst);
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}
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}
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MachInst mi = static_cast<MachInst>(inst->staticInst->machInst);
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if (mi != machInst) {
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warn("%lli: Binary instructions do not match! Inst: %#x, "
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"checker: %#x",
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curTick, mi, machInst);
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handleError(inst);
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}
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}
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template <class DynInstPtr>
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void
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Checker<DynInstPtr>::validateExecution(DynInstPtr &inst)
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{
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bool result_mismatch = false;
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if (inst->numDestRegs()) {
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// @todo: Support more destination registers.
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if (inst->isUnverifiable()) {
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// Unverifiable instructions assume they were executed
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// properly by the CPU. Grab the result from the
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// instruction and write it to the register.
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copyResult(inst);
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} else if (result.integer != inst->readIntResult()) {
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result_mismatch = true;
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}
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}
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if (result_mismatch) {
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warn("%lli: Instruction results do not match! (Values may not "
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"actually be integers) Inst: %#x, checker: %#x",
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curTick, inst->readIntResult(), result.integer);
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// It's useful to verify load values from memory, but in MP
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// systems the value obtained at execute may be different than
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// the value obtained at completion. Similarly DMA can
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// present the same problem on even UP systems. Thus there is
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// the option to only warn on loads having a result error.
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if (inst->isLoad() && warnOnlyOnLoadError) {
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copyResult(inst);
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} else {
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handleError(inst);
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}
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}
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if (inst->readNextPC() != thread->readNextPC()) {
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warn("%lli: Instruction next PCs do not match! Inst: %#x, "
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"checker: %#x",
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curTick, inst->readNextPC(), thread->readNextPC());
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handleError(inst);
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}
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// Checking side effect registers can be difficult if they are not
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// checked simultaneously with the execution of the instruction.
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// This is because other valid instructions may have modified
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// these registers in the meantime, and their values are not
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// stored within the DynInst.
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while (!miscRegIdxs.empty()) {
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int misc_reg_idx = miscRegIdxs.front();
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miscRegIdxs.pop();
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if (inst->tcBase()->readMiscRegNoEffect(misc_reg_idx) !=
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thread->readMiscRegNoEffect(misc_reg_idx)) {
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warn("%lli: Misc reg idx %i (side effect) does not match! "
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"Inst: %#x, checker: %#x",
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curTick, misc_reg_idx,
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inst->tcBase()->readMiscRegNoEffect(misc_reg_idx),
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thread->readMiscRegNoEffect(misc_reg_idx));
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handleError(inst);
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}
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}
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}
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template <class DynInstPtr>
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void
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Checker<DynInstPtr>::validateState()
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{
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if (updateThisCycle) {
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warn("%lli: Instruction PC %#x results didn't match up, copying all "
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"registers from main CPU", curTick, unverifiedInst->readPC());
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// Heavy-weight copying of all registers
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thread->copyArchRegs(unverifiedInst->tcBase());
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// Also advance the PC. Hopefully no PC-based events happened.
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#if THE_ISA != MIPS_ISA
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// go to the next instruction
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thread->setPC(thread->readNextPC());
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thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
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#else
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// go to the next instruction
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thread->setPC(thread->readNextPC());
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thread->setNextPC(thread->readNextNPC());
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thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
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#endif
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updateThisCycle = false;
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}
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}
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template <class DynInstPtr>
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void
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Checker<DynInstPtr>::copyResult(DynInstPtr &inst)
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{
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RegIndex idx = inst->destRegIdx(0);
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if (idx < TheISA::FP_Base_DepTag) {
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thread->setIntReg(idx, inst->readIntResult());
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} else if (idx < TheISA::Fpcr_DepTag) {
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thread->setFloatRegBits(idx, inst->readIntResult());
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} else {
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thread->setMiscRegNoEffect(idx, inst->readIntResult());
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}
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}
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template <class DynInstPtr>
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void
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Checker<DynInstPtr>::dumpAndExit(DynInstPtr &inst)
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{
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cprintf("Error detected, instruction information:\n");
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cprintf("PC:%#x, nextPC:%#x\n[sn:%lli]\n[tid:%i]\n"
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"Completed:%i\n",
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inst->readPC(),
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inst->readNextPC(),
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inst->seqNum,
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inst->threadNumber,
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inst->isCompleted());
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inst->dump();
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CheckerCPU::dumpAndExit();
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}
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template <class DynInstPtr>
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void
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Checker<DynInstPtr>::dumpInsts()
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{
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int num = 0;
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InstListIt inst_list_it = --(instList.end());
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cprintf("Inst list size: %i\n", instList.size());
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while (inst_list_it != instList.end())
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{
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cprintf("Instruction:%i\n",
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num);
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cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
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"Completed:%i\n",
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(*inst_list_it)->readPC(),
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(*inst_list_it)->seqNum,
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(*inst_list_it)->threadNumber,
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(*inst_list_it)->isCompleted());
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cprintf("\n");
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inst_list_it--;
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++num;
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}
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}
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