Nilay Vaish cb7782f78d ruby: enable multiple clock domains ... This patch allows ruby to have multiple clock domains. As I understand with this patch, controllers can have different frequencies. The entire network needs to run at a single frequency. The idea is that with in an object, time is treated in terms of cycles. But the messages that are passed from one entity to another should contain the time in Ticks. As of now, this is only true for the message buffers, but not for the links in the network. As I understand the code, all the entities in different networks (simple, garnet-fixed, garnet-flexible) should be clocked at the same frequency. Another problem is that the directory controller has to operate at the same frequency as the ruby system. This is because the memory controller does not make use of the Message Buffer, and instead implements a buffer of its own. So, it has no idea of the frequency at which the directory controller is operating and uses ruby system's frequency for scheduling events.		2013-02-10 21:43:17 -06:00
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AbstractReplacementPolicy.hh	ruby: replace Time with Tick in replacement policy classes	2013-02-10 21:43:08 -06:00
BankedArray.cc	ruby banked array: do away with event scheduling	2012-10-15 17:27:15 -05:00
BankedArray.hh	ruby banked array: do away with event scheduling	2012-10-15 17:27:15 -05:00
Cache.py	ruby: replaces Time with Cycles in many places	2013-02-10 21:26:24 -06:00
CacheMemory.cc	Ruby: Remove RubyEventQueue	2012-08-27 01:00:55 -05:00
CacheMemory.hh	ruby: replaces Time with Cycles in many places	2013-02-10 21:26:24 -06:00
DirectoryMemory.cc	Ruby: remove config information from ruby.stats	2012-07-12 08:39:19 -05:00
DirectoryMemory.hh	Ruby: remove config information from ruby.stats	2012-07-12 08:39:19 -05:00
DirectoryMemory.py	sim: Include object header files in SWIG interfaces	2012-11-02 11:32:01 -05:00
DMASequencer.cc	ruby: enable multiple clock domains	2013-02-10 21:43:17 -06:00
DMASequencer.hh	Ruby: Use uint8_t instead of uint8 everywhere	2012-09-11 09:23:56 -05:00
LRUPolicy.hh	ruby: replace Time with Tick in replacement policy classes	2013-02-10 21:43:08 -06:00
MachineID.hh	ruby: record fully busy cycle with in the controller	2013-02-10 21:26:22 -06:00
MemoryControl.cc	ruby: improved support for functional accesses	2012-10-15 17:51:57 -05:00
MemoryControl.hh	ruby: replace Time with Cycles in Memory Controller	2013-02-10 21:26:25 -06:00
MemoryControl.py	sim: Include object header files in SWIG interfaces	2012-11-02 11:32:01 -05:00
MemoryNode.cc	ruby: style pass	2010-03-22 18:43:53 -07:00
MemoryNode.hh	ruby: replace Time with Cycles in Memory Controller	2013-02-10 21:26:25 -06:00
MemoryVector.hh	Ruby: Use uint32_t instead of uint32 everywhere	2012-09-11 09:24:45 -05:00
PerfectCacheMemory.hh	Ruby: remove config information from ruby.stats	2012-07-12 08:39:19 -05:00
PersistentTable.cc	ruby: get rid of the Map class	2010-06-10 23:17:07 -07:00
PersistentTable.hh	Ruby: remove config information from ruby.stats	2012-07-12 08:39:19 -05:00
PseudoLRUPolicy.hh	ruby: replace Time with Tick in replacement policy classes	2013-02-10 21:43:08 -06:00
RubyMemoryControl.cc	ruby: enable multiple clock domains	2013-02-10 21:43:17 -06:00
RubyMemoryControl.hh	ruby: replace Time with Cycles in Memory Controller	2013-02-10 21:26:25 -06:00
RubyMemoryControl.py	ruby: replaces Time with Cycles in many places	2013-02-10 21:26:24 -06:00
RubyPort.cc	ruby: enable multiple clock domains	2013-02-10 21:43:17 -06:00
RubyPort.hh	ruby: enable multiple clock domains	2013-02-10 21:43:17 -06:00
RubyPortProxy.cc	MEM: Add port proxies instead of non-structural ports	2012-01-17 12:55:08 -06:00
RubyPortProxy.hh	MEM: Add port proxies instead of non-structural ports	2012-01-17 12:55:08 -06:00
RubySystem.py	ruby: convert block size, memory size to unsigned	2013-02-10 21:43:07 -06:00
SConscript	ruby: banked cache array resource model	2012-07-10 22:51:54 -07:00
Sequencer.cc	ruby: enable multiple clock domains	2013-02-10 21:43:17 -06:00
Sequencer.hh	ruby: replace Time with Cycles (final patch in the series)	2013-02-10 21:43:10 -06:00
Sequencer.py	sim: Include object header files in SWIG interfaces	2012-11-02 11:32:01 -05:00
SparseMemory.cc	Ruby Sparse Memory: Add function for collating blocks	2012-01-11 13:29:54 -06:00
SparseMemory.hh	Ruby: remove config information from ruby.stats	2012-07-12 08:39:19 -05:00
System.cc	ruby: convert block size, memory size to unsigned	2013-02-10 21:43:07 -06:00
System.hh	ruby: enable multiple clock domains	2013-02-10 21:43:17 -06:00
TBETable.hh	ruby: replace Time with Cycles (final patch in the series)	2013-02-10 21:43:10 -06:00
TimerTable.cc	ruby: replace Time with Cycles (final patch in the series)	2013-02-10 21:43:10 -06:00
TimerTable.hh	ruby: replace Time with Cycles (final patch in the series)	2013-02-10 21:43:10 -06:00
WireBuffer.cc	ruby: enable multiple clock domains	2013-02-10 21:43:17 -06:00
WireBuffer.hh	ruby: replaces Time with Cycles in many places	2013-02-10 21:26:24 -06:00
WireBuffer.py	sim: Include object header files in SWIG interfaces	2012-11-02 11:32:01 -05:00