76cd4393c0
Objects that are can be serialized are supposed to inherit from the Serializable class. This class is meant to provide a unified API for such objects. However, so far it has mainly been used by SimObjects due to some fundamental design limitations. This changeset redesigns to the serialization interface to make it more generic and hide the underlying checkpoint storage. Specifically: * Add a set of APIs to serialize into a subsection of the current object. Previously, objects that needed this functionality would use ad-hoc solutions using nameOut() and section name generation. In the new world, an object that implements the interface has the methods serializeSection() and unserializeSection() that serialize into a named /subsection/ of the current object. Calling serialize() serializes an object into the current section. * Move the name() method from Serializable to SimObject as it is no longer needed for serialization. The fully qualified section name is generated by the main serialization code on the fly as objects serialize sub-objects. * Add a scoped ScopedCheckpointSection helper class. Some objects need to serialize data structures, that are not deriving from Serializable, into subsections. Previously, this was done using nameOut() and manual section name generation. To simplify this, this changeset introduces a ScopedCheckpointSection() helper class. When this class is instantiated, it adds a new /subsection/ and subsequent serialization calls during the lifetime of this helper class happen inside this section (or a subsection in case of nested sections). * The serialize() call is now const which prevents accidental state manipulation during serialization. Objects that rely on modifying state can use the serializeOld() call instead. The default implementation simply calls serialize(). Note: The old-style calls need to be explicitly called using the serializeOld()/serializeSectionOld() style APIs. These are used by default when serializing SimObjects. * Both the input and output checkpoints now use their own named types. This hides underlying checkpoint implementation from objects that need checkpointing and makes it easier to change the underlying checkpoint storage code.
373 lines
9.7 KiB
C++
373 lines
9.7 KiB
C++
/*
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* Copyright (c) 2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andrew Schultz
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*/
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/** @file
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* Device model for an IDE disk
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*/
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#ifndef __IDE_DISK_HH__
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#define __IDE_DISK_HH__
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#include "base/statistics.hh"
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#include "dev/disk_image.hh"
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#include "dev/ide_atareg.h"
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#include "dev/ide_ctrl.hh"
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#include "dev/ide_wdcreg.h"
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#include "dev/io_device.hh"
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#include "params/IdeDisk.hh"
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#include "sim/eventq.hh"
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class ChunkGenerator;
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#define DMA_BACKOFF_PERIOD 200
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#define MAX_DMA_SIZE 0x20000 // 128K
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#define MAX_SINGLE_DMA_SIZE 0x10000
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#define MAX_MULTSECT (128)
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#define PRD_BASE_MASK 0xfffffffe
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#define PRD_COUNT_MASK 0xfffe
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#define PRD_EOT_MASK 0x8000
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typedef struct PrdEntry {
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uint32_t baseAddr;
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uint16_t byteCount;
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uint16_t endOfTable;
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} PrdEntry_t;
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class PrdTableEntry {
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public:
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PrdEntry_t entry;
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uint32_t getBaseAddr()
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{
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return (entry.baseAddr & PRD_BASE_MASK);
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}
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uint32_t getByteCount()
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{
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return ((entry.byteCount == 0) ? MAX_SINGLE_DMA_SIZE :
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(entry.byteCount & PRD_COUNT_MASK));
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}
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uint16_t getEOT()
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{
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return (entry.endOfTable & PRD_EOT_MASK);
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}
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};
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#define DATA_OFFSET (0)
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#define ERROR_OFFSET (1)
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#define FEATURES_OFFSET (1)
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#define NSECTOR_OFFSET (2)
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#define SECTOR_OFFSET (3)
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#define LCYL_OFFSET (4)
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#define HCYL_OFFSET (5)
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#define SELECT_OFFSET (6)
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#define DRIVE_OFFSET (6)
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#define STATUS_OFFSET (7)
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#define COMMAND_OFFSET (7)
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#define CONTROL_OFFSET (2)
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#define ALTSTAT_OFFSET (2)
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#define SELECT_DEV_BIT 0x10
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#define CONTROL_RST_BIT 0x04
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#define CONTROL_IEN_BIT 0x02
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#define STATUS_BSY_BIT 0x80
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#define STATUS_DRDY_BIT 0x40
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#define STATUS_DRQ_BIT 0x08
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#define STATUS_SEEK_BIT 0x10
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#define STATUS_DF_BIT 0x20
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#define DRIVE_LBA_BIT 0x40
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#define DEV0 (0)
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#define DEV1 (1)
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typedef struct CommandReg {
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uint16_t data;
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uint8_t error;
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uint8_t sec_count;
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uint8_t sec_num;
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uint8_t cyl_low;
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uint8_t cyl_high;
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union {
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uint8_t drive;
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uint8_t head;
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};
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uint8_t command;
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} CommandReg_t;
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typedef enum Events {
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None = 0,
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Transfer,
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ReadWait,
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WriteWait,
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PrdRead,
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DmaRead,
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DmaWrite
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} Events_t;
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typedef enum DevAction {
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ACT_NONE = 0,
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ACT_CMD_WRITE,
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ACT_CMD_COMPLETE,
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ACT_CMD_ERROR,
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ACT_SELECT_WRITE,
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ACT_STAT_READ,
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ACT_DATA_READY,
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ACT_DATA_READ_BYTE,
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ACT_DATA_READ_SHORT,
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ACT_DATA_WRITE_BYTE,
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ACT_DATA_WRITE_SHORT,
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ACT_DMA_READY,
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ACT_DMA_DONE,
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ACT_SRST_SET,
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ACT_SRST_CLEAR
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} DevAction_t;
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typedef enum DevState {
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// Device idle
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Device_Idle_S = 0,
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Device_Idle_SI,
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Device_Idle_NS,
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// Software reset
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Device_Srst,
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// Non-data commands
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Command_Execution,
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// PIO data-in (data to host)
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Prepare_Data_In,
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Data_Ready_INTRQ_In,
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Transfer_Data_In,
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// PIO data-out (data from host)
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Prepare_Data_Out,
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Data_Ready_INTRQ_Out,
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Transfer_Data_Out,
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// DMA protocol
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Prepare_Data_Dma,
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Transfer_Data_Dma,
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Device_Dma_Abort
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} DevState_t;
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typedef enum DmaState {
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Dma_Idle = 0,
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Dma_Start,
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Dma_Transfer
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} DmaState_t;
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class IdeController;
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/**
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* IDE Disk device model
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*/
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class IdeDisk : public SimObject
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{
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protected:
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/** The IDE controller for this disk. */
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IdeController *ctrl;
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/** The image that contains the data of this disk. */
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DiskImage *image;
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protected:
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/** The disk delay in microseconds. */
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int diskDelay;
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private:
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/** Drive identification structure for this disk */
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struct ataparams driveID;
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/** Data buffer for transfers */
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uint8_t *dataBuffer;
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/** Number of bytes in command data transfer */
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uint32_t cmdBytes;
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/** Number of bytes left in command data transfer */
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uint32_t cmdBytesLeft;
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/** Number of bytes left in DRQ block */
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uint32_t drqBytesLeft;
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/** Current sector in access */
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uint32_t curSector;
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/** Command block registers */
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CommandReg_t cmdReg;
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/** Status register */
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uint8_t status;
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/** Interrupt enable bit */
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bool nIENBit;
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/** Device state */
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DevState_t devState;
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/** Dma state */
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DmaState_t dmaState;
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/** Dma transaction is a read */
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bool dmaRead;
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/** PRD table base address */
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uint32_t curPrdAddr;
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/** PRD entry */
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PrdTableEntry curPrd;
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/** Device ID (master=0/slave=1) */
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int devID;
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/** Interrupt pending */
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bool intrPending;
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/** DMA Aborted */
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bool dmaAborted;
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Stats::Scalar dmaReadFullPages;
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Stats::Scalar dmaReadBytes;
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Stats::Scalar dmaReadTxs;
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Stats::Scalar dmaWriteFullPages;
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Stats::Scalar dmaWriteBytes;
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Stats::Scalar dmaWriteTxs;
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public:
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typedef IdeDiskParams Params;
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IdeDisk(const Params *p);
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/**
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* Delete the data buffer.
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*/
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~IdeDisk();
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/**
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* Reset the device state
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*/
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void reset(int id);
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/**
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* Register Statistics
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*/
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void regStats();
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/**
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* Set the controller for this device
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* @param c The IDE controller
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*/
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void setController(IdeController *c) {
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if (ctrl) panic("Cannot change the controller once set!\n");
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ctrl = c;
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}
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// Device register read/write
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void readCommand(const Addr offset, int size, uint8_t *data);
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void readControl(const Addr offset, int size, uint8_t *data);
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void writeCommand(const Addr offset, int size, const uint8_t *data);
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void writeControl(const Addr offset, int size, const uint8_t *data);
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// Start/abort functions
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void startDma(const uint32_t &prdTableBase);
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void abortDma();
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private:
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void startCommand();
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// Interrupt management
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void intrPost();
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void intrClear();
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// DMA stuff
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void doDmaTransfer();
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friend class EventWrapper<IdeDisk, &IdeDisk::doDmaTransfer>;
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EventWrapper<IdeDisk, &IdeDisk::doDmaTransfer> dmaTransferEvent;
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void doDmaDataRead();
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void doDmaRead();
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ChunkGenerator *dmaReadCG;
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friend class EventWrapper<IdeDisk, &IdeDisk::doDmaRead>;
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EventWrapper<IdeDisk, &IdeDisk::doDmaRead> dmaReadWaitEvent;
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void doDmaDataWrite();
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void doDmaWrite();
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ChunkGenerator *dmaWriteCG;
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friend class EventWrapper<IdeDisk, &IdeDisk::doDmaWrite>;
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EventWrapper<IdeDisk, &IdeDisk::doDmaWrite> dmaWriteWaitEvent;
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void dmaPrdReadDone();
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friend class EventWrapper<IdeDisk, &IdeDisk::dmaPrdReadDone>;
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EventWrapper<IdeDisk, &IdeDisk::dmaPrdReadDone> dmaPrdReadEvent;
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void dmaReadDone();
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friend class EventWrapper<IdeDisk, &IdeDisk::dmaReadDone>;
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EventWrapper<IdeDisk, &IdeDisk::dmaReadDone> dmaReadEvent;
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void dmaWriteDone();
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friend class EventWrapper<IdeDisk, &IdeDisk::dmaWriteDone>;
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EventWrapper<IdeDisk, &IdeDisk::dmaWriteDone> dmaWriteEvent;
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// Disk image read/write
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void readDisk(uint32_t sector, uint8_t *data);
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void writeDisk(uint32_t sector, uint8_t *data);
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// State machine management
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void updateState(DevAction_t action);
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// Utility functions
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bool isBSYSet() { return (status & STATUS_BSY_BIT); }
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bool isIENSet() { return nIENBit; }
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bool isDEVSelect();
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void setComplete()
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{
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// clear out the status byte
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status = 0;
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// set the DRDY bit
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status |= STATUS_DRDY_BIT;
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// set the SEEK bit
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status |= STATUS_SEEK_BIT;
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}
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uint32_t getLBABase()
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{
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return (Addr)(((cmdReg.head & 0xf) << 24) | (cmdReg.cyl_high << 16) |
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(cmdReg.cyl_low << 8) | (cmdReg.sec_num));
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}
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inline Addr pciToDma(Addr pciAddr);
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void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
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void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
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};
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#endif // __IDE_DISK_HH__
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