865 lines
30 KiB
C++
865 lines
30 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Ali Saidi
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*/
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#ifndef __ARCH_SPARC_REGFILE_HH__
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#define __ARCH_SPARC_REGFILE_HH__
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#include "arch/sparc/exceptions.hh"
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#include "arch/sparc/faults.hh"
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#include "base/trace.hh"
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#include "sim/byteswap.hh"
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#include "cpu/cpuevent.hh"
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#include "sim/host.hh"
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class Checkpoint;
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namespace SparcISA
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{
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typedef uint8_t RegIndex;
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// MAXTL - maximum trap level
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const int MaxPTL = 2;
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const int MaxTL = 6;
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const int MaxGL = 3;
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const int MaxPGL = 2;
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// NWINDOWS - number of register windows, can be 3 to 32
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const int NWindows = 32;
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const int AsrStart = 0;
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const int PrStart = 32;
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const int HprStart = 64;
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const int MiscStart = 96;
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const uint64_t Bit64 = 0x8000000000000000;
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class IntRegFile
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{
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protected:
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static const int FrameOffsetBits = 3;
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static const int FrameNumBits = 2;
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static const int RegsPerFrame = 1 << FrameOffsetBits;
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static const int FrameNumMask =
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(FrameNumBits == sizeof(int)) ?
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(unsigned int)(-1) :
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(1 << FrameNumBits) - 1;
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static const int FrameOffsetMask =
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(FrameOffsetBits == sizeof(int)) ?
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(unsigned int)(-1) :
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(1 << FrameOffsetBits) - 1;
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IntReg regGlobals[MaxGL][RegsPerFrame];
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IntReg regSegments[2 * NWindows][RegsPerFrame];
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enum regFrame {Globals, Outputs, Locals, Inputs, NumFrames};
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IntReg * regView[NumFrames];
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static const int RegGlobalOffset = 0;
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static const int FrameOffset = MaxGL * RegsPerFrame;
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int offset[NumFrames];
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public:
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int flattenIndex(int reg)
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{
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int flatIndex = offset[reg >> FrameOffsetBits]
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| (reg & FrameOffsetMask);
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DPRINTF(Sparc, "Flattened index %d into %d.\n", reg, flatIndex);
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return flatIndex;
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}
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void clear()
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{
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int x;
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for (x = 0; x < MaxGL; x++)
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memset(regGlobals[x], 0, sizeof(regGlobals[x]));
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for(int x = 0; x < 2 * NWindows; x++)
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bzero(regSegments[x], sizeof(regSegments[x]));
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}
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IntRegFile()
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{
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offset[Globals] = 0;
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regView[Globals] = regGlobals[0];
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setCWP(0);
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clear();
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}
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IntReg readReg(int intReg)
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{
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IntReg val =
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regView[intReg >> FrameOffsetBits][intReg & FrameOffsetMask];
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DPRINTF(Sparc, "Read register %d = 0x%x\n", intReg, val);
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return val;
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}
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Fault setReg(int intReg, const IntReg &val)
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{
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if(intReg)
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DPRINTF(Sparc, "Wrote register %d = 0x%x\n", intReg, val);
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regView[intReg >> FrameOffsetBits][intReg & FrameOffsetMask] = val;
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return NoFault;
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}
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//This doesn't effect the actual CWP register.
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//It's purpose is to adjust the view of the register file
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//to what it would be if CWP = cwp.
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void setCWP(int cwp)
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{
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int index = ((NWindows - cwp) % NWindows) * 2;
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offset[Outputs] = FrameOffset + (index * RegsPerFrame);
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offset[Locals] = FrameOffset + ((index+1) * RegsPerFrame);
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offset[Inputs] = FrameOffset +
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(((index+2) % (NWindows * 2)) * RegsPerFrame);
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regView[Outputs] = regSegments[index];
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regView[Locals] = regSegments[index+1];
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regView[Inputs] = regSegments[(index+2) % (NWindows * 2)];
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DPRINTF(Sparc, "Changed the CWP value to %d\n", cwp);
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}
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void setGlobals(int gl)
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{
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DPRINTF(Sparc, "Now using %d globals", gl);
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regView[Globals] = regGlobals[gl];
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offset[Globals] = RegGlobalOffset + gl * RegsPerFrame;
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}
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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};
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typedef float float32_t;
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typedef double float64_t;
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//FIXME long double refers to a 10 byte float, rather than a
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//16 byte float as required. This data type may have to be emulated.
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typedef double float128_t;
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class FloatRegFile
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{
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public:
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static const int SingleWidth = 32;
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static const int DoubleWidth = 64;
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static const int QuadWidth = 128;
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protected:
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//Since the floating point registers overlap each other,
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//A generic storage space is used. The float to be returned is
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//pulled from the appropriate section of this region.
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char regSpace[SingleWidth / 8 * NumFloatRegs];
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public:
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void clear()
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{
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bzero(regSpace, sizeof(regSpace));
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}
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FloatReg readReg(int floatReg, int width)
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{
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//In each of these cases, we have to copy the value into a temporary
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//variable. This is because we may otherwise try to access an
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//unaligned portion of memory.
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switch(width)
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{
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case SingleWidth:
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float32_t result32;
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memcpy(&result32, regSpace + 4 * floatReg, width);
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return htog(result32);
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case DoubleWidth:
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float64_t result64;
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memcpy(&result64, regSpace + 4 * floatReg, width);
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return htog(result64);
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case QuadWidth:
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float128_t result128;
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memcpy(&result128, regSpace + 4 * floatReg, width);
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return htog(result128);
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default:
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panic("Attempted to read a %d bit floating point register!", width);
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}
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}
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FloatRegBits readRegBits(int floatReg, int width)
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{
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//In each of these cases, we have to copy the value into a temporary
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//variable. This is because we may otherwise try to access an
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//unaligned portion of memory.
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switch(width)
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{
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case SingleWidth:
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uint32_t result32;
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memcpy(&result32, regSpace + 4 * floatReg, width);
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return htog(result32);
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case DoubleWidth:
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uint64_t result64;
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memcpy(&result64, regSpace + 4 * floatReg, width);
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return htog(result64);
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case QuadWidth:
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uint64_t result128;
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memcpy(&result128, regSpace + 4 * floatReg, width);
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return htog(result128);
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default:
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panic("Attempted to read a %d bit floating point register!", width);
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}
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}
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Fault setReg(int floatReg, const FloatReg &val, int width)
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{
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//In each of these cases, we have to copy the value into a temporary
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//variable. This is because we may otherwise try to access an
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//unaligned portion of memory.
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switch(width)
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{
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case SingleWidth:
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uint32_t result32 = gtoh((uint32_t)val);
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memcpy(regSpace + 4 * floatReg, &result32, width);
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case DoubleWidth:
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uint64_t result64 = gtoh((uint64_t)val);
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memcpy(regSpace + 4 * floatReg, &result64, width);
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case QuadWidth:
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uint64_t result128 = gtoh((uint64_t)val);
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memcpy(regSpace + 4 * floatReg, &result128, width);
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default:
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panic("Attempted to read a %d bit floating point register!", width);
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}
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return NoFault;
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}
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Fault setRegBits(int floatReg, const FloatRegBits &val, int width)
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{
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//In each of these cases, we have to copy the value into a temporary
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//variable. This is because we may otherwise try to access an
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//unaligned portion of memory.
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switch(width)
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{
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case SingleWidth:
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uint32_t result32 = gtoh((uint32_t)val);
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memcpy(regSpace + 4 * floatReg, &result32, width);
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case DoubleWidth:
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uint64_t result64 = gtoh((uint64_t)val);
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memcpy(regSpace + 4 * floatReg, &result64, width);
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case QuadWidth:
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uint64_t result128 = gtoh((uint64_t)val);
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memcpy(regSpace + 4 * floatReg, &result128, width);
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default:
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panic("Attempted to read a %d bit floating point register!", width);
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}
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return NoFault;
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}
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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};
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enum MiscRegIndex
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{
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/** Ancillary State Registers */
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MISCREG_Y = AsrStart + 0,
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MISCREG_CCR = AsrStart + 2,
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MISCREG_ASI = AsrStart + 3,
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MISCREG_TICK = AsrStart + 4,
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MISCREG_PC = AsrStart + 5,
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MISCREG_FPRS = AsrStart + 6,
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MISCREG_PCR = AsrStart + 16,
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MISCREG_PIC = AsrStart + 17,
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MISCREG_GSR = AsrStart + 19,
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MISCREG_SOFTINT_SET = AsrStart + 20,
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MISCREG_SOFTINT_CLR = AsrStart + 21,
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MISCREG_SOFTINT = AsrStart + 22,
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MISCREG_TICK_CMPR = AsrStart + 23,
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MISCREG_STICK = AsrStart + 24,
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MISCREG_STICK_CMPR = AsrStart + 25,
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/** Privilged Registers */
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MISCREG_TPC = PrStart + 0,
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MISCREG_TNPC = PrStart + 1,
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MISCREG_TSTATE = PrStart + 2,
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MISCREG_TT = PrStart + 3,
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MISCREG_PRIVTICK = PrStart + 4,
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MISCREG_TBA = PrStart + 5,
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MISCREG_PSTATE = PrStart + 6,
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MISCREG_TL = PrStart + 7,
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MISCREG_PIL = PrStart + 8,
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MISCREG_CWP = PrStart + 9,
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MISCREG_CANSAVE = PrStart + 10,
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MISCREG_CANRESTORE = PrStart + 11,
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MISCREG_CLEANWIN = PrStart + 12,
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MISCREG_OTHERWIN = PrStart + 13,
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MISCREG_WSTATE = PrStart + 14,
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MISCREG_GL = PrStart + 16,
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/** Hyper privileged registers */
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MISCREG_HPSTATE = HprStart + 0,
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MISCREG_HTSTATE = HprStart + 1,
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MISCREG_HINTP = HprStart + 3,
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MISCREG_HTBA = HprStart + 5,
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MISCREG_HVER = HprStart + 6,
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MISCREG_STRAND_STS_REG = HprStart + 16,
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MISCREG_HSTICK_CMPR = HprStart + 31,
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/** Floating Point Status Register */
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MISCREG_FSR = MiscStart + 0
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};
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// The control registers, broken out into fields
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class MiscRegFile
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{
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private:
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/* ASR Registers */
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union {
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uint64_t y; // Y (used in obsolete multiplication)
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struct {
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uint64_t value:32; // The actual value stored in y
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uint64_t :32; // reserved bits
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} yFields;
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};
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union {
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uint8_t ccr; // Condition Code Register
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struct {
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union {
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uint8_t icc:4; // 32-bit condition codes
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struct {
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uint8_t c:1; // Carry
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uint8_t v:1; // Overflow
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uint8_t z:1; // Zero
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uint8_t n:1; // Negative
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} iccFields;
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};
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union {
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uint8_t xcc:4; // 64-bit condition codes
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struct {
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uint8_t c:1; // Carry
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uint8_t v:1; // Overflow
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uint8_t z:1; // Zero
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uint8_t n:1; // Negative
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} xccFields;
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};
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} ccrFields;
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};
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uint8_t asi; // Address Space Identifier
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union {
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uint64_t tick; // Hardware clock-tick counter
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struct {
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int64_t counter:63; // Clock-tick count
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uint64_t npt:1; // Non-priveleged trap
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} tickFields;
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};
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union {
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uint8_t fprs; // Floating-Point Register State
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struct {
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uint8_t dl:1; // Dirty lower
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uint8_t du:1; // Dirty upper
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uint8_t fef:1; // FPRS enable floating-Point
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} fprsFields;
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};
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union {
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uint64_t softint;
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struct {
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uint64_t tm:1;
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uint64_t int_level:14;
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uint64_t sm:1;
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} softintFields;
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};
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union {
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uint64_t tick_cmpr; // Hardware tick compare registers
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struct {
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uint64_t tick_cmpr:63; // Clock-tick count
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uint64_t int_dis:1; // Non-priveleged trap
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} tick_cmprFields;
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};
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union {
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uint64_t stick; // Hardware clock-tick counter
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struct {
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int64_t :63; // Not used, storage in SparcSystem
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uint64_t npt:1; // Non-priveleged trap
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} stickFields;
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};
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union {
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uint64_t stick_cmpr; // Hardware tick compare registers
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struct {
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uint64_t tick_cmpr:63; // Clock-tick count
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uint64_t int_dis:1; // Non-priveleged trap
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} stick_cmprFields;
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};
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/* Privileged Registers */
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uint64_t tpc[MaxTL]; // Trap Program Counter (value from
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// previous trap level)
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uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from
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// previous trap level)
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union {
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uint64_t tstate[MaxTL]; // Trap State
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struct {
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//Values are from previous trap level
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uint64_t cwp:5; // Current Window Pointer
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uint64_t :3; // Reserved bits
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uint64_t pstate:13; // Process State
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uint64_t :3; // Reserved bits
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uint64_t asi:8; // Address Space Identifier
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uint64_t ccr:8; // Condition Code Register
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uint64_t gl:8; // Global level
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} tstateFields[MaxTL];
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};
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uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured
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// on the previous level)
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uint64_t tba; // Trap Base Address
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union {
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uint16_t pstate; // Process State Register
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struct {
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uint16_t :1; // reserved
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uint16_t ie:1; // Interrupt enable
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uint16_t priv:1; // Privelege mode
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uint16_t am:1; // Address mask
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uint16_t pef:1; // PSTATE enable floating-point
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uint16_t :1; // reserved2
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uint16_t mm:2; // Memory Model
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uint16_t tle:1; // Trap little-endian
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uint16_t cle:1; // Current little-endian
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} pstateFields;
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};
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uint8_t tl; // Trap Level
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uint8_t pil; // Process Interrupt Register
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uint8_t cwp; // Current Window Pointer
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uint8_t cansave; // Savable windows
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uint8_t canrestore; // Restorable windows
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uint8_t cleanwin; // Clean windows
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uint8_t otherwin; // Other windows
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union {
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uint8_t wstate; // Window State
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struct {
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uint8_t normal:3; // Bits TT<4:2> are set to on a normal
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// register window trap
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uint8_t other:3; // Bits TT<4:2> are set to on an "otherwin"
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// register window trap
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} wstateFields;
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};
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uint8_t gl; // Global level register
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/** Hyperprivileged Registers */
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union {
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uint64_t hpstate; // Hyperprivileged State Register
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struct {
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uint8_t tlz: 1;
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uint8_t :1;
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uint8_t hpriv:1;
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uint8_t :2;
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uint8_t red:1;
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uint8_t :4;
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uint8_t ibe:1;
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uint8_t id:1;
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} hpstateFields;
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};
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uint64_t htstate[MaxTL]; // Hyperprivileged Trap State Register
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uint64_t hintp;
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uint64_t htba; // Hyperprivileged Trap Base Address register
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union {
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uint64_t hstick_cmpr; // Hardware tick compare registers
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struct {
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uint64_t tick_cmpr:63; // Clock-tick count
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uint64_t int_dis:1; // Non-priveleged trap
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} hstick_cmprFields;
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};
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uint64_t strandStatusReg; // Per strand status register
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/** Floating point misc registers. */
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union {
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uint64_t fsr; // Floating-Point State Register
|
|
struct {
|
|
union {
|
|
uint64_t cexc:5; // Current excpetion
|
|
struct {
|
|
uint64_t nxc:1; // Inexact
|
|
uint64_t dzc:1; // Divide by zero
|
|
uint64_t ufc:1; // Underflow
|
|
uint64_t ofc:1; // Overflow
|
|
uint64_t nvc:1; // Invalid operand
|
|
} cexcFields;
|
|
};
|
|
union {
|
|
uint64_t aexc:5; // Accrued exception
|
|
struct {
|
|
uint64_t nxc:1; // Inexact
|
|
uint64_t dzc:1; // Divide by zero
|
|
uint64_t ufc:1; // Underflow
|
|
uint64_t ofc:1; // Overflow
|
|
uint64_t nvc:1; // Invalid operand
|
|
} aexcFields;
|
|
};
|
|
uint64_t fcc0:2; // Floating-Point condtion codes
|
|
uint64_t :1; // Reserved bits
|
|
uint64_t qne:1; // Deferred trap queue not empty
|
|
// with no queue, it should read 0
|
|
uint64_t ftt:3; // Floating-Point trap type
|
|
uint64_t ver:3; // Version (of the FPU)
|
|
uint64_t :2; // Reserved bits
|
|
uint64_t ns:1; // Nonstandard floating point
|
|
union {
|
|
uint64_t tem:5; // Trap Enable Mask
|
|
struct {
|
|
uint64_t nxm:1; // Inexact
|
|
uint64_t dzm:1; // Divide by zero
|
|
uint64_t ufm:1; // Underflow
|
|
uint64_t ofm:1; // Overflow
|
|
uint64_t nvm:1; // Invalid operand
|
|
} temFields;
|
|
};
|
|
uint64_t :2; // Reserved bits
|
|
uint64_t rd:2; // Rounding direction
|
|
uint64_t fcc1:2; // Floating-Point condition codes
|
|
uint64_t fcc2:2; // Floating-Point condition codes
|
|
uint64_t fcc3:2; // Floating-Point condition codes
|
|
uint64_t :26; // Reserved bits
|
|
} fsrFields;
|
|
};
|
|
|
|
// These need to check the int_dis field and if 0 then
|
|
// set appropriate bit in softint and checkinterrutps on the cpu
|
|
#if FULL_SYSTEM
|
|
/** Process a tick compare event and generate an interrupt on the cpu if
|
|
* appropriate. */
|
|
void processTickCompare(ExecContext *xc);
|
|
void processSTickCompare(ExecContext *xc);
|
|
void processHSTickCompare(ExecContext *xc);
|
|
|
|
typedef CpuEventWrapper<MiscRegFile,
|
|
&MiscRegFile::processTickCompare> TickCompareEvent;
|
|
TickCompareEvent *tickCompare;
|
|
|
|
typedef CpuEventWrapper<MiscRegFile,
|
|
&MiscRegFile::processSTickCompare> STickCompareEvent;
|
|
STickCompareEvent *sTickCompare;
|
|
|
|
typedef CpuEventWrapper<MiscRegFile,
|
|
&MiscRegFile::processHSTickCompare> HSTickCompareEvent;
|
|
HSTickCompareEvent *hSTickCompare;
|
|
|
|
/** Fullsystem only register version of ReadRegWithEffect() */
|
|
MiscReg readFSRegWithEffect(int miscReg, Fault &fault, ExecContext *xc);
|
|
/** Fullsystem only register version of SetRegWithEffect() */
|
|
Fault setFSRegWithEffect(int miscReg, const MiscReg &val,
|
|
ExecContext * xc);
|
|
#endif
|
|
public:
|
|
|
|
void reset()
|
|
{
|
|
pstateFields.pef = 0; //No FPU
|
|
//pstateFields.pef = 1; //FPU
|
|
#if FULL_SYSTEM
|
|
//For SPARC, when a system is first started, there is a power
|
|
//on reset Trap which sets the processor into the following state.
|
|
//Bits that aren't set aren't defined on startup.
|
|
tl = MaxTL;
|
|
gl = MaxGL;
|
|
|
|
tickFields.counter = 0; //The TICK register is unreadable bya
|
|
tickFields.npt = 1; //The TICK register is unreadable by by !priv
|
|
|
|
softint = 0; // Clear all the soft interrupt bits
|
|
tick_cmprFields.int_dis = 1; // disable timer compare interrupts
|
|
tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
|
|
stickFields.npt = 1; //The TICK register is unreadable by by !priv
|
|
stick_cmprFields.int_dis = 1; // disable timer compare interrupts
|
|
stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
|
|
|
|
|
|
tt[tl] = power_on_reset;
|
|
pstate = 0; // fields 0 but pef
|
|
pstateFields.pef = 1;
|
|
|
|
hpstate = 0;
|
|
hpstateFields.red = 1;
|
|
hpstateFields.hpriv = 1;
|
|
hpstateFields.tlz = 0; // this is a guess
|
|
|
|
hintp = 0; // no interrupts pending
|
|
hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
|
|
hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
|
|
|
|
#else
|
|
/* //This sets up the initial state of the processor for usermode processes
|
|
pstateFields.priv = 0; //Process runs in user mode
|
|
pstateFields.ie = 1; //Interrupts are enabled
|
|
fsrFields.rd = 0; //Round to nearest
|
|
fsrFields.tem = 0; //Floating point traps not enabled
|
|
fsrFields.ns = 0; //Non standard mode off
|
|
fsrFields.qne = 0; //Floating point queue is empty
|
|
fsrFields.aexc = 0; //No accrued exceptions
|
|
fsrFields.cexc = 0; //No current exceptions
|
|
|
|
//Register window management registers
|
|
otherwin = 0; //No windows contain info from other programs
|
|
canrestore = 0; //There are no windows to pop
|
|
cansave = MaxTL - 2; //All windows are available to save into
|
|
cleanwin = MaxTL;*/
|
|
#endif
|
|
}
|
|
|
|
MiscRegFile()
|
|
{
|
|
reset();
|
|
}
|
|
|
|
/** read a value out of an either an SE or FS IPR. No checking is done
|
|
* about SE vs. FS as this is mostly used to copy the regfile. Thus more
|
|
* register are copied that are necessary for FS. However this prevents
|
|
* a bunch of ifdefs and is rarely called so is not performance
|
|
* criticial. */
|
|
MiscReg readReg(int miscReg);
|
|
|
|
/** Read a value from an IPR. Only the SE iprs are here and the rest
|
|
* are are readFSRegWithEffect (which is called by readRegWithEffect()).
|
|
* Checking is done for permission based on state bits in the miscreg
|
|
* file. */
|
|
MiscReg readRegWithEffect(int miscReg, Fault &fault, ExecContext *xc);
|
|
|
|
/** write a value into an either an SE or FS IPR. No checking is done
|
|
* about SE vs. FS as this is mostly used to copy the regfile. Thus more
|
|
* register are copied that are necessary for FS. However this prevents
|
|
* a bunch of ifdefs and is rarely called so is not performance
|
|
* criticial.*/
|
|
Fault setReg(int miscReg, const MiscReg &val);
|
|
|
|
/** Write a value into an IPR. Only the SE iprs are here and the rest
|
|
* are are setFSRegWithEffect (which is called by setRegWithEffect()).
|
|
* Checking is done for permission based on state bits in the miscreg
|
|
* file. */
|
|
Fault setRegWithEffect(int miscReg,
|
|
const MiscReg &val, ExecContext * xc);
|
|
|
|
void serialize(std::ostream & os);
|
|
|
|
void unserialize(Checkpoint * cp, const std::string & section);
|
|
|
|
void copyMiscRegs(ExecContext * xc);
|
|
|
|
bool isHyperPriv() { return hpstateFields.hpriv; }
|
|
bool isPriv() { return hpstateFields.hpriv || pstateFields.priv; }
|
|
bool isNonPriv() { return !isPriv(); }
|
|
};
|
|
|
|
typedef union
|
|
{
|
|
IntReg intreg;
|
|
FloatReg fpreg;
|
|
MiscReg ctrlreg;
|
|
} AnyReg;
|
|
|
|
class RegFile
|
|
{
|
|
protected:
|
|
Addr pc; // Program Counter
|
|
Addr npc; // Next Program Counter
|
|
Addr nnpc;
|
|
|
|
public:
|
|
Addr readPC()
|
|
{
|
|
return pc;
|
|
}
|
|
|
|
void setPC(Addr val)
|
|
{
|
|
pc = val;
|
|
}
|
|
|
|
Addr readNextPC()
|
|
{
|
|
return npc;
|
|
}
|
|
|
|
void setNextPC(Addr val)
|
|
{
|
|
npc = val;
|
|
}
|
|
|
|
Addr readNextNPC()
|
|
{
|
|
return nnpc;
|
|
}
|
|
|
|
void setNextNPC(Addr val)
|
|
{
|
|
nnpc = val;
|
|
}
|
|
|
|
protected:
|
|
IntRegFile intRegFile; // integer register file
|
|
FloatRegFile floatRegFile; // floating point register file
|
|
MiscRegFile miscRegFile; // control register file
|
|
|
|
public:
|
|
|
|
void clear()
|
|
{
|
|
intRegFile.clear();
|
|
floatRegFile.clear();
|
|
}
|
|
|
|
int FlattenIntIndex(int reg)
|
|
{
|
|
return intRegFile.flattenIndex(reg);
|
|
}
|
|
|
|
MiscReg readMiscReg(int miscReg)
|
|
{
|
|
return miscRegFile.readReg(miscReg);
|
|
}
|
|
|
|
MiscReg readMiscRegWithEffect(int miscReg,
|
|
Fault &fault, ExecContext *xc)
|
|
{
|
|
return miscRegFile.readRegWithEffect(miscReg, fault, xc);
|
|
}
|
|
|
|
Fault setMiscReg(int miscReg, const MiscReg &val)
|
|
{
|
|
return miscRegFile.setReg(miscReg, val);
|
|
}
|
|
|
|
Fault setMiscRegWithEffect(int miscReg, const MiscReg &val,
|
|
ExecContext * xc)
|
|
{
|
|
return miscRegFile.setRegWithEffect(miscReg, val, xc);
|
|
}
|
|
|
|
FloatReg readFloatReg(int floatReg, int width)
|
|
{
|
|
return floatRegFile.readReg(floatReg, width);
|
|
}
|
|
|
|
FloatReg readFloatReg(int floatReg)
|
|
{
|
|
//Use the "natural" width of a single float
|
|
return floatRegFile.readReg(floatReg, FloatRegFile::SingleWidth);
|
|
}
|
|
|
|
FloatRegBits readFloatRegBits(int floatReg, int width)
|
|
{
|
|
return floatRegFile.readRegBits(floatReg, width);
|
|
}
|
|
|
|
FloatRegBits readFloatRegBits(int floatReg)
|
|
{
|
|
//Use the "natural" width of a single float
|
|
return floatRegFile.readRegBits(floatReg,
|
|
FloatRegFile::SingleWidth);
|
|
}
|
|
|
|
Fault setFloatReg(int floatReg, const FloatReg &val, int width)
|
|
{
|
|
return floatRegFile.setReg(floatReg, val, width);
|
|
}
|
|
|
|
Fault setFloatReg(int floatReg, const FloatReg &val)
|
|
{
|
|
//Use the "natural" width of a single float
|
|
return setFloatReg(floatReg, val, FloatRegFile::SingleWidth);
|
|
}
|
|
|
|
Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
|
|
{
|
|
return floatRegFile.setRegBits(floatReg, val, width);
|
|
}
|
|
|
|
Fault setFloatRegBits(int floatReg, const FloatRegBits &val)
|
|
{
|
|
//Use the "natural" width of a single float
|
|
return floatRegFile.setRegBits(floatReg, val,
|
|
FloatRegFile::SingleWidth);
|
|
}
|
|
|
|
IntReg readIntReg(int intReg)
|
|
{
|
|
return intRegFile.readReg(intReg);
|
|
}
|
|
|
|
Fault setIntReg(int intReg, const IntReg &val)
|
|
{
|
|
return intRegFile.setReg(intReg, val);
|
|
}
|
|
|
|
void serialize(std::ostream &os);
|
|
void unserialize(Checkpoint *cp, const std::string §ion);
|
|
|
|
public:
|
|
|
|
enum ContextParam
|
|
{
|
|
CONTEXT_CWP,
|
|
CONTEXT_GLOBALS
|
|
};
|
|
typedef int ContextVal;
|
|
|
|
void changeContext(ContextParam param, ContextVal val)
|
|
{
|
|
switch(param)
|
|
{
|
|
case CONTEXT_CWP:
|
|
intRegFile.setCWP(val);
|
|
break;
|
|
case CONTEXT_GLOBALS:
|
|
intRegFile.setGlobals(val);
|
|
break;
|
|
default:
|
|
panic("Tried to set illegal context parameter in the SPARC regfile.\n");
|
|
}
|
|
}
|
|
};
|
|
|
|
void copyRegs(ExecContext *src, ExecContext *dest);
|
|
|
|
void copyMiscRegs(ExecContext *src, ExecContext *dest);
|
|
|
|
int InterruptLevel(uint64_t softint);
|
|
|
|
} // namespace SparcISA
|
|
|
|
#endif
|