893533a126
This patch adds a parameter to the BaseCache to enable a read-only cache, for example for the instruction cache, or table-walker cache (not for x86). A number of checks are put in place in the code to ensure a read-only cache does not end up with dirty data. A follow-on patch adds suitable read requests to allow a read-only cache to explicitly ask for clean data.
115 lines
4.8 KiB
Python
115 lines
4.8 KiB
Python
# Copyright (c) 2012 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Andreas Sandberg
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from abc import ABCMeta, abstractmethod
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import m5
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from m5.objects import *
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from m5.proxy import *
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m5.util.addToPath('../configs/common')
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from Benchmarks import SysConfig
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import FSConfig
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from Caches import *
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from base_config import *
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class LinuxX86SystemBuilder(object):
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"""Mix-in that implements create_system.
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This mix-in is intended as a convenient way of adding an
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X86-specific create_system method to a class deriving from one of
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the generic base systems.
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"""
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def __init__(self):
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pass
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def create_system(self):
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mdesc = SysConfig(disk = 'linux-x86.img')
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system = FSConfig.makeLinuxX86System(self.mem_mode,
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numCPUs=self.num_cpus,
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mdesc=mdesc)
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self.init_system(system)
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return system
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class LinuxX86FSSystem(LinuxX86SystemBuilder,
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BaseFSSystem):
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"""Basic X86 full system builder."""
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def __init__(self, **kwargs):
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"""Initialize an X86 system that supports full system simulation.
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Note: Keyword arguments that are not listed below will be
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passed to the BaseFSSystem.
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Keyword Arguments:
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machine_type -- String describing the platform to simulate
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"""
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BaseSystem.__init__(self, **kwargs)
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LinuxX86SystemBuilder.__init__(self)
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def create_caches_private(self, cpu):
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cpu.addPrivateSplitL1Caches(L1_ICache(size='32kB', assoc=1),
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L1_DCache(size='32kB', assoc=4),
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PageTableWalkerCache(),
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PageTableWalkerCache())
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class LinuxX86FSSystemUniprocessor(LinuxX86SystemBuilder,
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BaseFSSystemUniprocessor):
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"""Basic X86 full system builder for uniprocessor systems.
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Note: This class is a specialization of the X86FSSystem and is
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only really needed to provide backwards compatibility for existing
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test cases.
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"""
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def __init__(self, **kwargs):
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BaseFSSystemUniprocessor.__init__(self, **kwargs)
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LinuxX86SystemBuilder.__init__(self)
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def create_caches_private(self, cpu):
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cpu.addTwoLevelCacheHierarchy(L1_ICache(size='32kB', assoc=1),
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L1_DCache(size='32kB', assoc=4),
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L2Cache(size='4MB', assoc=8),
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PageTableWalkerCache(),
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PageTableWalkerCache())
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class LinuxX86FSSwitcheroo(LinuxX86SystemBuilder, BaseFSSwitcheroo):
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"""Uniprocessor X86 system prepared for CPU switching"""
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def __init__(self, **kwargs):
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BaseFSSwitcheroo.__init__(self, **kwargs)
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LinuxX86SystemBuilder.__init__(self)
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