448 lines
48 KiB
Text
448 lines
48 KiB
Text
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---------- Begin Simulation Statistics ----------
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global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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global.BPredUnit.BTBHits 65739146 # Number of BTB hits
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global.BPredUnit.BTBLookups 73253175 # Number of BTB lookups
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global.BPredUnit.RASInCorrect 177 # Number of incorrect RAS predictions.
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global.BPredUnit.condIncorrect 4205990 # Number of conditional branches incorrect
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global.BPredUnit.condPredicted 70175548 # Number of conditional branches predicted
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global.BPredUnit.lookups 76112488 # Number of BP lookups
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global.BPredUnit.usedRAS 1692573 # Number of times the RAS was used to get a target.
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host_inst_rate 131337 # Simulator instruction rate (inst/s)
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host_mem_usage 179084 # Number of bytes of host memory used
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host_seconds 4306.11 # Real time elapsed on the host
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host_tick_rate 38417331 # Simulator tick rate (ticks/s)
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memdepunit.memDep.conflictingLoads 21896719 # Number of conflicting loads.
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memdepunit.memDep.conflictingStores 16284345 # Number of conflicting stores.
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memdepunit.memDep.insertedLoads 127086189 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 43192001 # Number of stores inserted to the mem dependence unit.
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 565552443 # Number of instructions simulated
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sim_seconds 0.165429 # Number of seconds simulated
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sim_ticks 165429421500 # Number of ticks simulated
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system.cpu.commit.COM:branches 62547159 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 20148945 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle.samples 320950455
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system.cpu.commit.COM:committed_per_cycle.min_value 0
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0 102049912 3179.62%
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1 106118520 3306.38%
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2 36548740 1138.77%
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3 11550344 359.88%
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4 9951958 310.08%
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5 22152324 690.21%
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6 10779065 335.85%
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7 1650647 51.43%
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8 20148945 627.79%
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system.cpu.commit.COM:committed_per_cycle.max_value 8
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system.cpu.commit.COM:committed_per_cycle.end_dist
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system.cpu.commit.COM:count 601856963 # Number of instructions committed
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system.cpu.commit.COM:loads 115049510 # Number of loads committed
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs 154862033 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 4205367 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 61707712 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 565552443 # Number of Instructions Simulated
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system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
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system.cpu.cpi 0.585019 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.585019 # CPI: Total CPI of All Threads
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system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits
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system.cpu.dcache.ReadReq_accesses 115038352 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 6257.587595 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3367.177206 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 114105250 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 5838967500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.008111 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 933102 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 716795 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 728344000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.001880 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 216307 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 7448.640662 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7159.473367 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 37241994 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 16456482928 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.056001 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 2209327 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 1872039 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 2414804453 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.008549 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 337288 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs 1999.750000 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets 2750 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 321.245700 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 4 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 4 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 7999 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 11000 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 154489673 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 7094.973483 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 5677.703832 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 151347244 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 22295450428 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.020341 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 3142429 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 2588834 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 3143148453 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.003583 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 553595 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 154489673 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 7094.973483 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 5677.703832 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 151347244 # number of overall hits
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system.cpu.dcache.overall_miss_latency 22295450428 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.020341 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 3142429 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 2588834 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 3143148453 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.003583 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 553595 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.dcache.replacements 468826 # number of replacements
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system.cpu.dcache.sampled_refs 472922 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4095.170465 # Cycle average of tags in use
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system.cpu.dcache.total_refs 151924159 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 50285000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 334126 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 46422286 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 645 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 4161088 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 690019158 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 145191324 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 123829448 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 9907520 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 1984 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 5507398 # Number of cycles decode is unblocking
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system.cpu.dtb.accesses 163087430 # DTB accesses
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system.cpu.dtb.acv 0 # DTB access violations
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system.cpu.dtb.hits 163038163 # DTB hits
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system.cpu.dtb.misses 49267 # DTB misses
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system.cpu.dtb.read_accesses 122338189 # DTB read accesses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_hits 122317544 # DTB read hits
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system.cpu.dtb.read_misses 20645 # DTB read misses
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system.cpu.dtb.write_accesses 40749241 # DTB write accesses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_hits 40720619 # DTB write hits
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system.cpu.dtb.write_misses 28622 # DTB write misses
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system.cpu.fetch.Branches 76112488 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 66025670 # Number of cache lines fetched
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system.cpu.fetch.Cycles 197184214 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 1351502 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 699221634 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 4235220 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.230045 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 66025670 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 67431719 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 2.113353 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist.samples 330857976
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system.cpu.fetch.rateDist.min_value 0
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0 199699470 6035.81%
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1 10371896 313.48%
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2 15863038 479.45%
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3 14602598 441.36%
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4 12358229 373.52%
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5 14818818 447.89%
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6 6010699 181.67%
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7 3341156 100.98%
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8 53792072 1625.84%
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system.cpu.fetch.rateDist.max_value 8
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system.cpu.fetch.rateDist.end_dist
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system.cpu.icache.ReadReq_accesses 66025670 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 9355.263158 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 6819.290466 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 66024644 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 9598500 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000016 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 1026 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 124 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 6151000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 73198.053215 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 66025670 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 9355.263158 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 6819.290466 # average overall mshr miss latency
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system.cpu.icache.demand_hits 66024644 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 9598500 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000016 # miss rate for demand accesses
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system.cpu.icache.demand_misses 1026 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 124 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 6151000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 902 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 66025670 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 9355.263158 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 6819.290466 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 66024644 # number of overall hits
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system.cpu.icache.overall_miss_latency 9598500 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000016 # miss rate for overall accesses
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system.cpu.icache.overall_misses 1026 # number of overall misses
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system.cpu.icache.overall_mshr_hits 124 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 6151000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 902 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.icache.replacements 32 # number of replacements
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system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 769.239178 # Cycle average of tags in use
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system.cpu.icache.total_refs 66024644 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idleCycles 868 # Total number of cycles that the CPU has spent unscheduled due to idling
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system.cpu.iew.EXEC:branches 67336673 # Number of branches executed
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system.cpu.iew.EXEC:nop 43018581 # number of nop insts executed
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system.cpu.iew.EXEC:rate 1.810881 # Inst execution rate
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system.cpu.iew.EXEC:refs 164027135 # number of memory reference insts executed
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system.cpu.iew.EXEC:stores 41145337 # Number of stores executed
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system.cpu.iew.EXEC:swp 0 # number of swp insts executed
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system.cpu.iew.WB:consumers 491694974 # num instructions consuming a value
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system.cpu.iew.WB:count 595952322 # cumulative count of insts written-back
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system.cpu.iew.WB:fanout 0.808476 # average fanout of values written-back
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system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
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system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.iew.WB:producers 397523802 # num instructions producing a value
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system.cpu.iew.WB:rate 1.801228 # insts written-back per cycle
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system.cpu.iew.WB:sent 597113280 # cumulative count of insts sent to commit
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system.cpu.iew.branchMispredicts 4671395 # Number of branch mispredicts detected at execute
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system.cpu.iew.iewBlockCycles 85472 # Number of cycles IEW is blocking
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system.cpu.iew.iewDispLoadInsts 127086189 # Number of dispatched load instructions
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system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions
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system.cpu.iew.iewDispSquashedInsts 3259094 # Number of squashed instructions skipped by dispatch
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system.cpu.iew.iewDispStoreInsts 43192001 # Number of dispatched store instructions
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system.cpu.iew.iewDispatchedInsts 663707703 # Number of instructions dispatched to IQ
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system.cpu.iew.iewExecLoadInsts 122881798 # Number of load instructions executed
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system.cpu.iew.iewExecSquashedInsts 6536173 # Number of squashed instructions skipped in execute
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system.cpu.iew.iewExecutedInsts 599145915 # Number of executed instructions
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system.cpu.iew.iewIQFullEvents 1317 # Number of times the IQ has become full, causing a stall
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
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system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.iewSquashCycles 9907520 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewUnblockCycles 4668 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 4162 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread.0.forwLoads 7269203 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 14266 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 32461 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 5902 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 12036679 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread.0.squashedStores 3379478 # Number of stores squashed
|
|
system.cpu.iew.memOrderViolationEvents 32461 # Number of memory order violations
|
|
system.cpu.iew.predictedNotTakenIncorrect 540781 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.predictedTakenIncorrect 4130614 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.ipc 1.709347 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.709347 # IPC: Total IPC of All Threads
|
|
system.cpu.iq.ISSUE:FU_type_0 605682088 # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|
No_OpClass 0 0.00% # Type of FU issued
|
|
IntAlu 438760030 72.44% # Type of FU issued
|
|
IntMult 6517 0.00% # Type of FU issued
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
FloatAdd 29 0.00% # Type of FU issued
|
|
FloatCmp 5 0.00% # Type of FU issued
|
|
FloatCvt 5 0.00% # Type of FU issued
|
|
FloatMult 4 0.00% # Type of FU issued
|
|
FloatDiv 0 0.00% # Type of FU issued
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
|
MemRead 124950238 20.63% # Type of FU issued
|
|
MemWrite 41965260 6.93% # Type of FU issued
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 6912738 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.011413 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
No_OpClass 0 0.00% # attempts to use FU when none available
|
|
IntAlu 5342591 77.29% # attempts to use FU when none available
|
|
IntMult 72 0.00% # attempts to use FU when none available
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
FloatAdd 0 0.00% # attempts to use FU when none available
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
|
MemRead 924602 13.38% # attempts to use FU when none available
|
|
MemWrite 645473 9.34% # attempts to use FU when none available
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 330857976
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
|
0 90630363 2739.25%
|
|
1 66723730 2016.69%
|
|
2 79382589 2399.30%
|
|
3 36274593 1096.38%
|
|
4 32477730 981.62%
|
|
5 12845074 388.24%
|
|
6 10946309 330.85%
|
|
7 1065447 32.20%
|
|
8 512141 15.48%
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
system.cpu.iq.ISSUE:rate 1.830636 # Inst issue rate
|
|
system.cpu.iq.iqInstsAdded 620689100 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 605682088 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 53858401 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedInstsIssued 17774 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 5 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 29864580 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.itb.accesses 66025708 # ITB accesses
|
|
system.cpu.itb.acv 0 # ITB acv
|
|
system.cpu.itb.hits 66025670 # ITB hits
|
|
system.cpu.itb.misses 38 # ITB misses
|
|
system.cpu.l2cache.ReadExReq_accesses 256615 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 5221.239990 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2221.239990 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_miss_latency 1339848500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_misses 256615 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 570003500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 256615 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_accesses 217209 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 5324.201615 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2324.201615 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_hits 181418 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_miss_latency 190558500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.164777 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_misses 35791 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 83185500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.164777 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_misses 35791 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_accesses 80676 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 5165.743220 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2166.071694 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 416751500 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_misses 80676 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 174750000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 80676 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.Writeback_accesses 334126 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_hits 334126 # number of Writeback hits
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_refs 3.724082 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.demand_accesses 473824 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_avg_miss_latency 5233.842671 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 2233.842671 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_hits 181418 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_miss_latency 1530407000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_rate 0.617119 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_misses 292406 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_miss_latency 653189000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.617119 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_misses 292406 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.overall_accesses 473824 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_avg_miss_latency 5233.842671 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 2233.842671 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_hits 181418 # number of overall hits
|
|
system.cpu.l2cache.overall_miss_latency 1530407000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_rate 0.617119 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_misses 292406 # number of overall misses
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_miss_latency 653189000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.617119 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_misses 292406 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.cpu.l2cache.replacements 85250 # number of replacements
|
|
system.cpu.l2cache.sampled_refs 100885 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.tagsinuse 16355.319881 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 375704 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks 63237 # number of writebacks
|
|
system.cpu.numCycles 330858844 # number of cpu cycles simulated
|
|
system.cpu.rename.RENAME:BlockCycles 11109833 # Number of cycles rename is blocking
|
|
system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed
|
|
system.cpu.rename.RENAME:IQFullEvents 34908767 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.RENAME:IdleCycles 152607206 # Number of cycles rename is idle
|
|
system.cpu.rename.RENAME:LSQFullEvents 316634 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RENAME:RenameLookups 896955924 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RENAME:RenamedInsts 680550426 # Number of instructions processed by rename
|
|
system.cpu.rename.RENAME:RenamedOperands 519573186 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RENAME:RunCycles 116670528 # Number of cycles rename is running
|
|
system.cpu.rename.RENAME:SquashCycles 9907520 # Number of cycles rename is squashing
|
|
system.cpu.rename.RENAME:UnblockCycles 40562533 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RENAME:UndoneMaps 55718297 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.RENAME:serializeStallCycles 356 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed
|
|
system.cpu.rename.RENAME:skidInsts 79715664 # count of insts added to the skid buffer
|
|
system.cpu.rename.RENAME:tempSerializingInsts 25 # count of temporary serializing insts renamed
|
|
system.cpu.timesIdled 189 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|