1eec115c31
CPUs need to test that the memory system is in the right mode in two places, when the CPU is initialized (unless it's switched out) and on a drainResume(). This led to some code duplication in the CPU models. This changeset introduces the verifyMemoryMode() method which is called by BaseCPU::init() if the CPU isn't switched out. The individual CPU models are responsible for calling this method when resuming from a drain as this code is CPU model specific.
481 lines
14 KiB
C++
481 lines
14 KiB
C++
/*
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* Copyright (c) 2011-2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* Copyright (c) 2011 Regents of the University of California
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Nathan Binkert
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* Rick Strong
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*/
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#ifndef __CPU_BASE_HH__
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#define __CPU_BASE_HH__
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#include <vector>
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#include "arch/interrupts.hh"
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#include "arch/isa_traits.hh"
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#include "arch/microcode_rom.hh"
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#include "base/statistics.hh"
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#include "config/the_isa.hh"
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#include "mem/mem_object.hh"
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#include "sim/eventq.hh"
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#include "sim/full_system.hh"
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#include "sim/insttracer.hh"
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struct BaseCPUParams;
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class BranchPred;
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class CheckerCPU;
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class ThreadContext;
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class System;
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class CPUProgressEvent : public Event
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{
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protected:
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Tick _interval;
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Counter lastNumInst;
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BaseCPU *cpu;
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bool _repeatEvent;
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public:
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CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0);
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void process();
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void interval(Tick ival) { _interval = ival; }
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Tick interval() { return _interval; }
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void repeatEvent(bool repeat) { _repeatEvent = repeat; }
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virtual const char *description() const;
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};
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class BaseCPU : public MemObject
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{
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protected:
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// @todo remove me after debugging with legion done
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Tick instCnt;
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// every cpu has an id, put it in the base cpu
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// Set at initialization, only time a cpuId might change is during a
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// takeover (which should be done from within the BaseCPU anyway,
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// therefore no setCpuId() method is provided
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int _cpuId;
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/** instruction side request id that must be placed in all requests */
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MasterID _instMasterId;
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/** data side request id that must be placed in all requests */
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MasterID _dataMasterId;
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/** An intrenal representation of a task identifier within gem5. This is
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* used so the CPU can add which taskId (which is an internal representation
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* of the OS process ID) to each request so components in the memory system
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* can track which process IDs are ultimately interacting with them
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*/
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uint32_t _taskId;
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/** The current OS process ID that is executing on this processor. This is
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* used to generate a taskId */
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uint32_t _pid;
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/** Is the CPU switched out or active? */
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bool _switchedOut;
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/**
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* Define a base class for the CPU ports (instruction and data)
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* that is refined in the subclasses. This class handles the
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* common cases, i.e. the functional accesses and the status
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* changes and address range queries. The default behaviour for
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* both atomic and timing access is to panic and the corresponding
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* subclasses have to override these methods.
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*/
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class CpuPort : public MasterPort
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{
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public:
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/**
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* Create a CPU port with a name and a structural owner.
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*
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* @param _name port name including the owner
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* @param _name structural owner of this port
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*/
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CpuPort(const std::string& _name, MemObject* _owner) :
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MasterPort(_name, _owner)
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{ }
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protected:
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virtual bool recvTimingResp(PacketPtr pkt);
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virtual void recvRetry();
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virtual void recvFunctionalSnoop(PacketPtr pkt);
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};
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public:
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/**
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* Purely virtual method that returns a reference to the data
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* port. All subclasses must implement this method.
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*
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* @return a reference to the data port
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*/
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virtual CpuPort &getDataPort() = 0;
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/**
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* Purely virtual method that returns a reference to the instruction
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* port. All subclasses must implement this method.
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*
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* @return a reference to the instruction port
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*/
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virtual CpuPort &getInstPort() = 0;
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/** Reads this CPU's ID. */
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int cpuId() { return _cpuId; }
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/** Reads this CPU's unique data requestor ID */
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MasterID dataMasterId() { return _dataMasterId; }
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/** Reads this CPU's unique instruction requestor ID */
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MasterID instMasterId() { return _instMasterId; }
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/**
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* Get a master port on this CPU. All CPUs have a data and
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* instruction port, and this method uses getDataPort and
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* getInstPort of the subclasses to resolve the two ports.
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*
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* @param if_name the port name
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* @param idx ignored index
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*
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* @return a reference to the port with the given name
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*/
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BaseMasterPort &getMasterPort(const std::string &if_name,
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PortID idx = InvalidPortID);
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/** Get cpu task id */
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uint32_t taskId() const { return _taskId; }
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/** Set cpu task id */
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void taskId(uint32_t id) { _taskId = id; }
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uint32_t getPid() const { return _pid; }
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void setPid(uint32_t pid) { _pid = pid; }
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inline void workItemBegin() { numWorkItemsStarted++; }
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inline void workItemEnd() { numWorkItemsCompleted++; }
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// @todo remove me after debugging with legion done
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Tick instCount() { return instCnt; }
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TheISA::MicrocodeRom microcodeRom;
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protected:
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TheISA::Interrupts *interrupts;
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public:
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TheISA::Interrupts *
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getInterruptController()
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{
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return interrupts;
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}
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virtual void wakeup() = 0;
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void
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postInterrupt(int int_num, int index)
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{
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interrupts->post(int_num, index);
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if (FullSystem)
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wakeup();
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}
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void
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clearInterrupt(int int_num, int index)
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{
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interrupts->clear(int_num, index);
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}
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void
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clearInterrupts()
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{
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interrupts->clearAll();
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}
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bool
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checkInterrupts(ThreadContext *tc) const
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{
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return FullSystem && interrupts->checkInterrupts(tc);
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}
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class ProfileEvent : public Event
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{
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private:
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BaseCPU *cpu;
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Tick interval;
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public:
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ProfileEvent(BaseCPU *cpu, Tick interval);
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void process();
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};
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ProfileEvent *profileEvent;
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protected:
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std::vector<ThreadContext *> threadContexts;
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Trace::InstTracer * tracer;
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public:
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// Mask to align PCs to MachInst sized boundaries
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static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
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/// Provide access to the tracer pointer
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Trace::InstTracer * getTracer() { return tracer; }
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/// Notify the CPU that the indicated context is now active. The
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/// delay parameter indicates the number of ticks to wait before
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/// executing (typically 0 or 1).
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virtual void activateContext(ThreadID thread_num, Cycles delay) {}
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/// Notify the CPU that the indicated context is now suspended.
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virtual void suspendContext(ThreadID thread_num) {}
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/// Notify the CPU that the indicated context is now deallocated.
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virtual void deallocateContext(ThreadID thread_num) {}
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/// Notify the CPU that the indicated context is now halted.
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virtual void haltContext(ThreadID thread_num) {}
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/// Given a Thread Context pointer return the thread num
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int findContext(ThreadContext *tc);
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/// Given a thread num get tho thread context for it
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ThreadContext *getContext(int tn) { return threadContexts[tn]; }
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public:
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typedef BaseCPUParams Params;
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const Params *params() const
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{ return reinterpret_cast<const Params *>(_params); }
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BaseCPU(Params *params, bool is_checker = false);
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virtual ~BaseCPU();
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virtual void init();
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virtual void startup();
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virtual void regStats();
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virtual void activateWhenReady(ThreadID tid) {};
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void registerThreadContexts();
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/**
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* Prepare for another CPU to take over execution.
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*
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* When this method exits, all internal state should have been
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* flushed. After the method returns, the simulator calls
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* takeOverFrom() on the new CPU with this CPU as its parameter.
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*/
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virtual void switchOut();
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/**
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* Load the state of a CPU from the previous CPU object, invoked
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* on all new CPUs that are about to be switched in.
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*
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* A CPU model implementing this method is expected to initialize
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* its state from the old CPU and connect its memory (unless they
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* are already connected) to the memories connected to the old
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* CPU.
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*
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* @param cpu CPU to initialize read state from.
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*/
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virtual void takeOverFrom(BaseCPU *cpu);
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/**
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* Flush all TLBs in the CPU.
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*
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* This method is mainly used to flush stale translations when
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* switching CPUs. It is also exported to the Python world to
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* allow it to request a TLB flush after draining the CPU to make
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* it easier to compare traces when debugging
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* handover/checkpointing.
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*/
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void flushTLBs();
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/**
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* Determine if the CPU is switched out.
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*
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* @return True if the CPU is switched out, false otherwise.
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*/
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bool switchedOut() const { return _switchedOut; }
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/**
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* Verify that the system is in a memory mode supported by the
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* CPU.
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*
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* Implementations are expected to query the system for the
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* current memory mode and ensure that it is what the CPU model
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* expects. If the check fails, the implementation should
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* terminate the simulation using fatal().
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*/
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virtual void verifyMemoryMode() const { };
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/**
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* Number of threads we're actually simulating (<= SMT_MAX_THREADS).
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* This is a constant for the duration of the simulation.
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*/
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ThreadID numThreads;
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/**
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* Vector of per-thread instruction-based event queues. Used for
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* scheduling events based on number of instructions committed by
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* a particular thread.
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*/
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EventQueue **comInstEventQueue;
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/**
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* Vector of per-thread load-based event queues. Used for
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* scheduling events based on number of loads committed by
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*a particular thread.
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*/
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EventQueue **comLoadEventQueue;
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System *system;
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/**
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* Serialize this object to the given output stream.
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*
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* @note CPU models should normally overload the serializeThread()
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* method instead of the serialize() method as this provides a
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* uniform data format for all CPU models and promotes better code
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* reuse.
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*
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* @param os The stream to serialize to.
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*/
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virtual void serialize(std::ostream &os);
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/**
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* Reconstruct the state of this object from a checkpoint.
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*
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* @note CPU models should normally overload the
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* unserializeThread() method instead of the unserialize() method
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* as this provides a uniform data format for all CPU models and
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* promotes better code reuse.
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* @param cp The checkpoint use.
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* @param section The section name of this object.
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*/
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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/**
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* Serialize a single thread.
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*
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* @param os The stream to serialize to.
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* @param tid ID of the current thread.
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*/
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virtual void serializeThread(std::ostream &os, ThreadID tid) {};
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/**
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* Unserialize one thread.
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*
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* @param cp The checkpoint use.
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* @param section The section name of this thread.
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* @param tid ID of the current thread.
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*/
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virtual void unserializeThread(Checkpoint *cp, const std::string §ion,
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ThreadID tid) {};
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/**
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* Return pointer to CPU's branch predictor (NULL if none).
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* @return Branch predictor pointer.
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*/
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virtual BranchPred *getBranchPred() { return NULL; };
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virtual Counter totalInsts() const = 0;
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virtual Counter totalOps() const = 0;
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// Function tracing
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private:
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bool functionTracingEnabled;
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std::ostream *functionTraceStream;
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Addr currentFunctionStart;
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Addr currentFunctionEnd;
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Tick functionEntryTick;
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void enableFunctionTrace();
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void traceFunctionsInternal(Addr pc);
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private:
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static std::vector<BaseCPU *> cpuList; //!< Static global cpu list
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public:
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void traceFunctions(Addr pc)
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{
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if (functionTracingEnabled)
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traceFunctionsInternal(pc);
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}
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static int numSimulatedCPUs() { return cpuList.size(); }
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static Counter numSimulatedInsts()
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{
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Counter total = 0;
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int size = cpuList.size();
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for (int i = 0; i < size; ++i)
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total += cpuList[i]->totalInsts();
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return total;
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}
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static Counter numSimulatedOps()
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{
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Counter total = 0;
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int size = cpuList.size();
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for (int i = 0; i < size; ++i)
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total += cpuList[i]->totalOps();
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return total;
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}
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public:
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// Number of CPU cycles simulated
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Stats::Scalar numCycles;
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Stats::Scalar numWorkItemsStarted;
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Stats::Scalar numWorkItemsCompleted;
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};
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#endif // __CPU_BASE_HH__
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