6629d9b2bc
Previously there was one per bus, which caused some coherence problems when more than one decided to respond. Now there is just one on the main memory bus. The default bus responder on all other buses is now the downstream cache's cpu_side port. Caches no longer need to do address range filtering; instead, we just have a simple flag to prevent snoops from propagating to the I/O bus.
172 lines
6.2 KiB
Python
172 lines
6.2 KiB
Python
# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ali Saidi
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import optparse, os, sys
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import m5
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if not m5.build_env['FULL_SYSTEM']:
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m5.fatal("This script requires full-system mode (*_FS).")
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from m5.objects import *
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m5.AddToPath('../common')
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from FSConfig import *
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from SysPaths import *
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from Benchmarks import *
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import Simulation
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from Caches import *
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# Get paths we might need. It's expected this file is in m5/configs/example.
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config_path = os.path.dirname(os.path.abspath(__file__))
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config_root = os.path.dirname(config_path)
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parser = optparse.OptionParser()
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# System options
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parser.add_option("--kernel", action="store", type="string")
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parser.add_option("--script", action="store", type="string")
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# Benchmark options
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parser.add_option("--dual", action="store_true",
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help="Simulate two systems attached with an ethernet link")
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parser.add_option("-b", "--benchmark", action="store", type="string",
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dest="benchmark",
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help="Specify the benchmark to run. Available benchmarks: %s"\
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% DefinedBenchmarks)
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# Metafile options
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parser.add_option("--etherdump", action="store", type="string", dest="etherdump",
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help="Specify the filename to dump a pcap capture of the" \
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"ethernet traffic")
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execfile(os.path.join(config_root, "common", "Options.py"))
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(options, args) = parser.parse_args()
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if args:
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print "Error: script doesn't take any positional arguments"
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sys.exit(1)
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# driver system CPU is always simple... note this is an assignment of
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# a class, not an instance.
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DriveCPUClass = AtomicSimpleCPU
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drive_mem_mode = 'atomic'
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# system under test can be any CPU
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(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
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TestCPUClass.clock = '2GHz'
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DriveCPUClass.clock = '2GHz'
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if options.benchmark:
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try:
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bm = Benchmarks[options.benchmark]
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except KeyError:
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print "Error benchmark %s has not been defined." % options.benchmark
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print "Valid benchmarks are: %s" % DefinedBenchmarks
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sys.exit(1)
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else:
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if options.dual:
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bm = [SysConfig(), SysConfig()]
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else:
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bm = [SysConfig()]
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if m5.build_env['TARGET_ISA'] == "alpha":
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test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
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elif m5.build_env['TARGET_ISA'] == "mips":
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test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
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elif m5.build_env['TARGET_ISA'] == "sparc":
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test_sys = makeSparcSystem(test_mem_mode, bm[0])
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elif m5.build_env['TARGET_ISA'] == "x86":
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test_sys = makeLinuxX86System(test_mem_mode, bm[0])
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else:
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m5.fatal("incapable of building non-alpha or non-sparc full system!")
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if options.kernel is not None:
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test_sys.kernel = binary(options.kernel)
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if options.script is not None:
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test_sys.readfile = options.script
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np = options.num_cpus
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if options.l2cache:
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test_sys.l2 = L2Cache(size = '2MB')
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test_sys.tol2bus = Bus()
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test_sys.l2.cpu_side = test_sys.tol2bus.port
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test_sys.l2.mem_side = test_sys.membus.port
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test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
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if options.caches:
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test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
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test_sys.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
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test_sys.iocache = IOCache(addr_range=AddrRange(0, size='8GB'))
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test_sys.iocache.cpu_side = test_sys.iobus.port
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test_sys.iocache.mem_side = test_sys.membus.port
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for i in xrange(np):
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if options.caches:
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test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
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L1Cache(size = '64kB'))
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if options.l2cache:
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test_sys.cpu[i].connectMemPorts(test_sys.tol2bus)
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else:
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test_sys.cpu[i].connectMemPorts(test_sys.membus)
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if options.fastmem:
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test_sys.cpu[i].physmem_port = test_sys.physmem.port
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if m5.build_env['TARGET_ISA'] == 'mips':
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setMipsOptions(TestCPUClass)
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if len(bm) == 2:
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if m5.build_env['TARGET_ISA'] == 'alpha':
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drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
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elif m5.build_env['TARGET_ISA'] == 'mips':
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drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
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elif m5.build_env['TARGET_ISA'] == 'sparc':
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drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
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elif m5.build.env['TARGET_ISA'] == 'x86':
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drive_sys = makeX86System(drive_mem_mode, bm[1])
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drive_sys.cpu = DriveCPUClass(cpu_id=0)
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drive_sys.cpu.connectMemPorts(drive_sys.membus)
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if options.fastmem:
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drive_sys.cpu.physmem_port = drive_sys.physmem.port
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if options.kernel is not None:
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drive_sys.kernel = binary(options.kernel)
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root = makeDualRoot(test_sys, drive_sys, options.etherdump)
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elif len(bm) == 1:
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root = Root(system=test_sys)
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else:
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print "Error I don't know how to create more than 2 systems."
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sys.exit(1)
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Simulation.run(options, root, test_sys, FutureClass)
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