185 lines
8.7 KiB
Python
185 lines
8.7 KiB
Python
# Copyright (c) 2005-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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from m5.SimObject import SimObject
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from m5.params import *
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from m5.proxy import *
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from m5 import build_env
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from Bus import Bus
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from InstTracer import InstTracer
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from ExeTracer import ExeTracer
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import sys
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default_tracer = ExeTracer()
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if build_env['TARGET_ISA'] == 'alpha':
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from AlphaTLB import AlphaDTB, AlphaITB
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elif build_env['TARGET_ISA'] == 'sparc':
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from SparcTLB import SparcDTB, SparcITB
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elif build_env['TARGET_ISA'] == 'x86':
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from X86TLB import X86DTB, X86ITB
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elif build_env['TARGET_ISA'] == 'mips':
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from MipsTLB import MipsTLB,MipsDTB, MipsITB, MipsUTB
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class BaseCPU(SimObject):
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type = 'BaseCPU'
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abstract = True
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system = Param.System(Parent.any, "system object")
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cpu_id = Param.Int("CPU identifier")
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if build_env['FULL_SYSTEM']:
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do_quiesce = Param.Bool(True, "enable quiesce instructions")
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do_checkpoint_insts = Param.Bool(True,
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"enable checkpoint pseudo instructions")
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do_statistics_insts = Param.Bool(True,
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"enable statistics pseudo instructions")
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else:
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workload = VectorParam.Process("processes to run")
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if build_env['TARGET_ISA'] == 'sparc':
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dtb = Param.SparcDTB(SparcDTB(), "Data TLB")
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itb = Param.SparcITB(SparcITB(), "Instruction TLB")
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elif build_env['TARGET_ISA'] == 'alpha':
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dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
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itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
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elif build_env['TARGET_ISA'] == 'x86':
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dtb = Param.X86DTB(X86DTB(), "Data TLB")
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itb = Param.X86ITB(X86ITB(), "Instruction TLB")
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elif build_env['TARGET_ISA'] == 'mips':
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UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
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dtb = Param.MipsDTB(MipsDTB(), "Data TLB")
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itb = Param.MipsITB(MipsITB(), "Instruction TLB")
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tlb = Param.MipsUTB(MipsUTB(), "Unified TLB")
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else:
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print "Don't know what TLB to use for ISA %s" % \
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build_env['TARGET_ISA']
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sys.exit(1)
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max_insts_all_threads = Param.Counter(0,
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"terminate when all threads have reached this inst count")
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max_insts_any_thread = Param.Counter(0,
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"terminate when any thread reaches this inst count")
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max_loads_all_threads = Param.Counter(0,
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"terminate when all threads have reached this load count")
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max_loads_any_thread = Param.Counter(0,
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"terminate when any thread reaches this load count")
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progress_interval = Param.Tick(0,
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"interval to print out the progress message")
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defer_registration = Param.Bool(False,
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"defer registration with system (for sampling)")
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clock = Param.Clock('1t', "clock speed")
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phase = Param.Latency('0ns', "clock phase")
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tracer = Param.InstTracer(default_tracer, "Instruction tracer")
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_mem_ports = []
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if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
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_mem_ports = ["itb.walker.port", "dtb.walker.port"]
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def connectMemPorts(self, bus):
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for p in self._mem_ports:
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if p != 'physmem_port':
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exec('self.%s = bus.port' % p)
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def addPrivateSplitL1Caches(self, ic, dc):
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assert(len(self._mem_ports) < 6)
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self.icache = ic
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self.dcache = dc
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self.icache_port = ic.cpu_side
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self.dcache_port = dc.cpu_side
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self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
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if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
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self._mem_ports += ["itb.walker_port", "dtb.walker_port"]
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def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
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self.addPrivateSplitL1Caches(ic, dc)
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self.toL2Bus = Bus()
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self.connectMemPorts(self.toL2Bus)
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self.l2cache = l2c
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self.l2cache.cpu_side = self.toL2Bus.port
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self._mem_ports = ['l2cache.mem_side']
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if build_env['TARGET_ISA'] == 'mips':
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CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description")
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CP0_IntCtl_IPPCI = Param.Unsigned(0,"No Description")
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CP0_SrsCtl_HSS = Param.Unsigned(0,"No Description")
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CP0_EBase_CPUNum = Param.Unsigned(0,"No Description")
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CP0_PRId_CompanyOptions = Param.Unsigned(0,"Company Options in Processor ID Register")
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CP0_PRId_CompanyID = Param.Unsigned(0,"Company Identifier in Processor ID Register")
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CP0_PRId_ProcessorID = Param.Unsigned(1,"Processor ID (0=>Not MIPS32/64 Processor, 1=>MIPS, 2-255 => Other Company")
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CP0_PRId_Revision = Param.Unsigned(0,"Processor Revision Number in Processor ID Register")
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CP0_Config_BE = Param.Unsigned(0,"Big Endian?")
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CP0_Config_AT = Param.Unsigned(0,"No Description")
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CP0_Config_AR = Param.Unsigned(0,"No Description")
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CP0_Config_MT = Param.Unsigned(0,"No Description")
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CP0_Config_VI = Param.Unsigned(0,"No Description")
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CP0_Config1_M = Param.Unsigned(0,"Config2 Implemented?")
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CP0_Config1_MMU = Param.Unsigned(0,"MMU Type")
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CP0_Config1_IS = Param.Unsigned(0,"No Description")
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CP0_Config1_IL = Param.Unsigned(0,"No Description")
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CP0_Config1_IA = Param.Unsigned(0,"No Description")
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CP0_Config1_DS = Param.Unsigned(0,"No Description")
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CP0_Config1_DL = Param.Unsigned(0,"No Description")
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CP0_Config1_DA = Param.Unsigned(0,"No Description")
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CP0_Config1_C2 = Param.Bool(False,"No Description")
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CP0_Config1_MD = Param.Bool(False,"No Description")
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CP0_Config1_PC = Param.Bool(False,"No Description")
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CP0_Config1_WR = Param.Bool(False,"No Description")
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CP0_Config1_CA = Param.Bool(False,"No Description")
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CP0_Config1_EP = Param.Bool(False,"No Description")
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CP0_Config1_FP = Param.Bool(False,"FPU Implemented?")
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CP0_Config2_M = Param.Bool(False,"Config3 Implemented?")
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CP0_Config2_TU = Param.Unsigned(0,"No Description")
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CP0_Config2_TS = Param.Unsigned(0,"No Description")
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CP0_Config2_TL = Param.Unsigned(0,"No Description")
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CP0_Config2_TA = Param.Unsigned(0,"No Description")
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CP0_Config2_SU = Param.Unsigned(0,"No Description")
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CP0_Config2_SS = Param.Unsigned(0,"No Description")
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CP0_Config2_SL = Param.Unsigned(0,"No Description")
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CP0_Config2_SA = Param.Unsigned(0,"No Description")
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CP0_Config3_M = Param.Bool(False,"Config4 Implemented?")
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CP0_Config3_DSPP = Param.Bool(False,"DSP Extensions Present?")
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CP0_Config3_LPA = Param.Bool(False,"No Description")
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CP0_Config3_VEIC = Param.Bool(False,"No Description")
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CP0_Config3_VInt = Param.Bool(False,"No Description")
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CP0_Config3_SP = Param.Bool(False,"No Description")
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CP0_Config3_MT = Param.Bool(False,"Multithreading Extensions Present?")
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CP0_Config3_SM = Param.Bool(False,"No Description")
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CP0_Config3_TL = Param.Bool(False,"No Description")
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CP0_WatchHi_M = Param.Bool(False,"No Description")
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CP0_PerfCtr_M = Param.Bool(False,"No Description")
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CP0_PerfCtr_W = Param.Bool(False,"No Description")
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CP0_PRId = Param.Unsigned(0,"CP0 Status Register")
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CP0_Config = Param.Unsigned(0,"CP0 Config Register")
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CP0_Config1 = Param.Unsigned(0,"CP0 Config1 Register")
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CP0_Config2 = Param.Unsigned(0,"CP0 Config2 Register")
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CP0_Config3 = Param.Unsigned(0,"CP0 Config3 Register")
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