374 lines
12 KiB
C++
374 lines
12 KiB
C++
/*
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* Copyright (c) 2015 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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* Steve Reinhardt
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*/
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// Todo: Create destructor.
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// Have it so that there's a more meaningful name given to the variable
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// that marks the beginning of the FP registers.
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#ifndef __CPU_O3_RENAME_MAP_HH__
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#define __CPU_O3_RENAME_MAP_HH__
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#include <iostream>
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#include <utility>
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#include <vector>
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#include "arch/types.hh"
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#include "config/the_isa.hh"
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#include "cpu/o3/free_list.hh"
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#include "cpu/o3/regfile.hh"
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#include "cpu/reg_class.hh"
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/**
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* Register rename map for a single class of registers (e.g., integer
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* or floating point). Because the register class is implicitly
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* determined by the rename map instance being accessed, all
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* architectural register index parameters and values in this class
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* are relative (e.g., %fp2 is just index 2).
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*/
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class SimpleRenameMap
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{
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public:
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typedef TheISA::RegIndex RegIndex;
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private:
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/** The acutal arch-to-phys register map */
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std::vector<PhysRegIndex> map;
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/**
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* Pointer to the free list from which new physical registers
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* should be allocated in rename()
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*/
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SimpleFreeList *freeList;
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/**
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* The architectural index of the zero register. This register is
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* mapped but read-only, so we ignore attempts to rename it via
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* the rename() method. If there is no such register for this map
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* table, it should be set to an invalid index so that it never
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* matches.
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*/
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RegIndex zeroReg;
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public:
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SimpleRenameMap();
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~SimpleRenameMap() {};
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/**
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* Because we have an array of rename maps (one per thread) in the CPU,
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* it's awkward to initialize this object via the constructor.
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* Instead, this method is used for initialization.
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*/
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void init(unsigned size, SimpleFreeList *_freeList, RegIndex _zeroReg);
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/**
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* Pair of a physical register and a physical register. Used to
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* return the physical register that a logical register has been
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* renamed to, and the previous physical register that the same
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* logical register was previously mapped to.
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*/
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typedef std::pair<PhysRegIndex, PhysRegIndex> RenameInfo;
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/**
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* Tell rename map to get a new free physical register to remap
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* the specified architectural register.
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* @param arch_reg The architectural register to remap.
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* @return A RenameInfo pair indicating both the new and previous
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* physical registers.
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*/
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RenameInfo rename(RegIndex arch_reg);
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/**
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* Look up the physical register mapped to an architectural register.
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* @param arch_reg The architectural register to look up.
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* @return The physical register it is currently mapped to.
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*/
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PhysRegIndex lookup(RegIndex arch_reg) const
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{
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assert(arch_reg < map.size());
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return map[arch_reg];
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}
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/**
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* Update rename map with a specific mapping. Generally used to
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* roll back to old mappings on a squash.
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* @param arch_reg The architectural register to remap.
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* @param phys_reg The physical register to remap it to.
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*/
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void setEntry(RegIndex arch_reg, PhysRegIndex phys_reg)
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{
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map[arch_reg] = phys_reg;
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}
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/** Return the number of free entries on the associated free list. */
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unsigned numFreeEntries() const { return freeList->numFreeRegs(); }
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};
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/**
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* Unified register rename map for all classes of registers. Wraps a
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* set of class-specific rename maps. Methods that do not specify a
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* register class (e.g., rename()) take unified register indices,
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* while methods that do specify a register class (e.g., renameInt())
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* take relative register indices. See http://gem5.org/Register_Indexing.
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*/
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class UnifiedRenameMap
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{
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private:
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/** The integer register rename map */
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SimpleRenameMap intMap;
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/** The floating-point register rename map */
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SimpleRenameMap floatMap;
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/**
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* The register file object is used only to distinguish integer
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* from floating-point physical register indices, which in turn is
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* used only for assert statements that make sure the physical
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* register indices that get passed in and handed out are of the
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* proper class.
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*/
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PhysRegFile *regFile;
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/** The condition-code register rename map */
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SimpleRenameMap ccMap;
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public:
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typedef TheISA::RegIndex RegIndex;
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typedef SimpleRenameMap::RenameInfo RenameInfo;
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/** Default constructor. init() must be called prior to use. */
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UnifiedRenameMap() : regFile(nullptr) {};
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/** Destructor. */
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~UnifiedRenameMap() {};
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/** Initializes rename map with given parameters. */
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void init(PhysRegFile *_regFile,
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RegIndex _intZeroReg,
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RegIndex _floatZeroReg,
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UnifiedFreeList *freeList);
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/**
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* Tell rename map to get a new free physical register to remap
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* the specified architectural register. This version takes a
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* unified flattened architectural register index and calls the
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* appropriate class-specific rename table.
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* @param arch_reg The unified architectural register index to remap.
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* @return A RenameInfo pair indicating both the new and previous
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* physical registers.
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*/
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RenameInfo rename(RegIndex arch_reg);
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/**
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* Perform rename() on an integer register, given a relative
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* integer register index.
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*/
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RenameInfo renameInt(RegIndex rel_arch_reg)
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{
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RenameInfo info = intMap.rename(rel_arch_reg);
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assert(regFile->isIntPhysReg(info.first));
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return info;
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}
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/**
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* Perform rename() on a floating-point register, given a relative
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* floating-point register index.
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*/
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RenameInfo renameFloat(RegIndex rel_arch_reg)
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{
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RenameInfo info = floatMap.rename(rel_arch_reg);
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assert(regFile->isFloatPhysReg(info.first));
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return info;
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}
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/**
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* Perform rename() on a condition-code register, given a relative
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* condition-code register index.
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*/
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RenameInfo renameCC(RegIndex rel_arch_reg)
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{
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RenameInfo info = ccMap.rename(rel_arch_reg);
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assert(regFile->isCCPhysReg(info.first));
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return info;
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}
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/**
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* Perform rename() on a misc register, given a relative
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* misc register index.
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*/
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RenameInfo renameMisc(RegIndex rel_arch_reg)
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{
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// misc regs aren't really renamed, just remapped
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PhysRegIndex phys_reg = lookupMisc(rel_arch_reg);
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// Set the previous register to the same register; mainly it must be
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// known that the prev reg was outside the range of normal registers
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// so the free list can avoid adding it.
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return RenameInfo(phys_reg, phys_reg);
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}
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/**
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* Look up the physical register mapped to an architectural register.
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* This version takes a unified flattened architectural register index
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* and calls the appropriate class-specific rename table.
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* @param arch_reg The unified architectural register to look up.
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* @return The physical register it is currently mapped to.
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*/
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PhysRegIndex lookup(RegIndex arch_reg) const;
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/**
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* Perform lookup() on an integer register, given a relative
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* integer register index.
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*/
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PhysRegIndex lookupInt(RegIndex rel_arch_reg) const
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{
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PhysRegIndex phys_reg = intMap.lookup(rel_arch_reg);
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assert(regFile->isIntPhysReg(phys_reg));
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return phys_reg;
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}
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/**
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* Perform lookup() on a floating-point register, given a relative
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* floating-point register index.
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*/
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PhysRegIndex lookupFloat(RegIndex rel_arch_reg) const
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{
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PhysRegIndex phys_reg = floatMap.lookup(rel_arch_reg);
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assert(regFile->isFloatPhysReg(phys_reg));
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return phys_reg;
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}
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/**
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* Perform lookup() on a condition-code register, given a relative
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* condition-code register index.
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*/
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PhysRegIndex lookupCC(RegIndex rel_arch_reg) const
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{
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PhysRegIndex phys_reg = ccMap.lookup(rel_arch_reg);
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assert(regFile->isCCPhysReg(phys_reg));
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return phys_reg;
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}
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/**
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* Perform lookup() on a misc register, given a relative
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* misc register index.
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*/
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PhysRegIndex lookupMisc(RegIndex rel_arch_reg) const
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{
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// misc regs aren't really renamed, just given an index
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// beyond the range of actual physical registers
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PhysRegIndex phys_reg = rel_arch_reg + regFile->totalNumPhysRegs();
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return phys_reg;
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}
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/**
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* Update rename map with a specific mapping. Generally used to
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* roll back to old mappings on a squash. This version takes a
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* unified flattened architectural register index and calls the
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* appropriate class-specific rename table.
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* @param arch_reg The unified architectural register to remap.
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* @param phys_reg The physical register to remap it to.
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*/
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void setEntry(RegIndex arch_reg, PhysRegIndex phys_reg);
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/**
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* Perform setEntry() on an integer register, given a relative
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* integer register index.
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*/
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void setIntEntry(RegIndex arch_reg, PhysRegIndex phys_reg)
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{
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assert(regFile->isIntPhysReg(phys_reg));
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intMap.setEntry(arch_reg, phys_reg);
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}
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/**
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* Perform setEntry() on a floating-point register, given a relative
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* floating-point register index.
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*/
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void setFloatEntry(RegIndex arch_reg, PhysRegIndex phys_reg)
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{
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assert(regFile->isFloatPhysReg(phys_reg));
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floatMap.setEntry(arch_reg, phys_reg);
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}
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/**
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* Perform setEntry() on a condition-code register, given a relative
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* condition-code register index.
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*/
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void setCCEntry(RegIndex arch_reg, PhysRegIndex phys_reg)
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{
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assert(regFile->isCCPhysReg(phys_reg));
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ccMap.setEntry(arch_reg, phys_reg);
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}
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/**
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* Return the minimum number of free entries across all of the
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* register classes. The minimum is used so we guarantee that
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* this number of entries is available regardless of which class
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* of registers is requested.
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*/
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unsigned numFreeEntries() const
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{
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return std::min(intMap.numFreeEntries(), floatMap.numFreeEntries());
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}
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/**
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* Return whether there are enough registers to serve the request.
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*/
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bool canRename(uint32_t intRegs, uint32_t floatRegs, uint32_t ccRegs) const
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{
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return intRegs <= intMap.numFreeEntries() &&
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floatRegs <= floatMap.numFreeEntries() &&
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ccRegs <= ccMap.numFreeEntries();
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}
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};
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#endif //__CPU_O3_RENAME_MAP_HH__
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