c26911013c
This patch adds support for specifying multi-channel memory configurations on the command line, e.g. 'se/fs.py --mem-type=ddr3_1600_x64 --mem-channels=4'. To enable this, it enhances the functionality of MemConfig and moves the existing makeMultiChannel class method from SimpleDRAM to the support scripts. The se/fs.py example scripts are updated to make use of the new feature.
193 lines
7.5 KiB
Python
193 lines
7.5 KiB
Python
# Copyright (c) 2013 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Andreas Sandberg
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# Andreas Hansson
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import m5.objects
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import inspect
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import sys
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from textwrap import TextWrapper
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# Dictionary of mapping names of real memory controller models to
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# classes.
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_mem_classes = {}
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# Memory aliases. We make sure they exist before we add them to the
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# fina; list. A target may be specified as a tuple, in which case the
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# first available memory controller model in the tuple will be used.
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_mem_aliases_all = [
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("simple_mem", "SimpleMemory"),
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("ddr3_1600_x64", "DDR3_1600_x64"),
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("lpddr2_s4_1066_x32", "LPDDR2_S4_1066_x32"),
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("lpddr3_1600_x32", "LPDDR3_1600_x32"),
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("wio_200_x128", "WideIO_200_x128"),
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]
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# Filtered list of aliases. Only aliases for existing memory
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# controllers exist in this list.
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_mem_aliases = {}
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def is_mem_class(cls):
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"""Determine if a class is a memory controller that can be instantiated"""
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# We can't use the normal inspect.isclass because the ParamFactory
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# and ProxyFactory classes have a tendency to confuse it.
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try:
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return issubclass(cls, m5.objects.AbstractMemory) and \
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not cls.abstract
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except TypeError:
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return False
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def get(name):
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"""Get a memory class from a user provided class name or alias."""
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real_name = _mem_aliases.get(name, name)
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try:
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mem_class = _mem_classes[real_name]
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return mem_class
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except KeyError:
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print "%s is not a valid memory controller." % (name,)
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sys.exit(1)
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def print_mem_list():
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"""Print a list of available memory classes including their aliases."""
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print "Available memory classes:"
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doc_wrapper = TextWrapper(initial_indent="\t\t", subsequent_indent="\t\t")
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for name, cls in _mem_classes.items():
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print "\t%s" % name
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# Try to extract the class documentation from the class help
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# string.
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doc = inspect.getdoc(cls)
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if doc:
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for line in doc_wrapper.wrap(doc):
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print line
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if _mem_aliases:
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print "\nMemory aliases:"
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for alias, target in _mem_aliases.items():
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print "\t%s => %s" % (alias, target)
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def mem_names():
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"""Return a list of valid memory names."""
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return _mem_classes.keys() + _mem_aliases.keys()
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# Add all memory controllers in the object hierarchy.
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for name, cls in inspect.getmembers(m5.objects, is_mem_class):
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_mem_classes[name] = cls
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for alias, target in _mem_aliases_all:
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if isinstance(target, tuple):
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# Some aliases contain a list of memory controller models
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# sorted in priority order. Use the first target that's
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# available.
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for t in target:
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if t in _mem_classes:
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_mem_aliases[alias] = t
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break
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elif target in _mem_classes:
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# Normal alias
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_mem_aliases[alias] = target
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def config_mem(options, system):
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"""
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Create the memory controllers based on the options and attach them.
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If requested, we make a multi-channel configuration of the
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selected memory controller class by creating multiple instances of
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the specific class. The individual controllers have their
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parameters set such that the address range is interleaved between
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them.
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"""
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nbr_mem_ctrls = options.mem_channels
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import math
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from m5.util import fatal
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intlv_bits = int(math.log(nbr_mem_ctrls, 2))
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if 2 ** intlv_bits != nbr_mem_ctrls:
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fatal("Number of memory channels must be a power of 2")
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cls = get(options.mem_type)
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mem_ctrls = []
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# The default behaviour is to interleave on cache line granularity
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cache_line_bit = int(math.log(system.cache_line_size.value, 2)) - 1
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intlv_low_bit = cache_line_bit
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# For every range (most systems will only have one), create an
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# array of controllers and set their parameters to match their
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# address mapping in the case of a DRAM
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for r in system.mem_ranges:
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for i in xrange(nbr_mem_ctrls):
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# Create an instance so we can figure out the address
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# mapping and row-buffer size
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ctrl = cls()
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# Only do this for DRAMs
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if issubclass(cls, m5.objects.SimpleDRAM):
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# Inform each controller how many channels to account
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# for
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ctrl.channels = nbr_mem_ctrls
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# If the channel bits are appearing after the column
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# bits, we need to add the appropriate number of bits
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# for the row buffer size
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if ctrl.addr_mapping.value == 'RaBaChCo':
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# This computation only really needs to happen
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# once, but as we rely on having an instance we
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# end up having to repeat it for each and every
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# one
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rowbuffer_size = ctrl.device_rowbuffer_size.value * \
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ctrl.devices_per_rank.value
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intlv_low_bit = int(math.log(rowbuffer_size, 2)) - 1
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# We got all we need to configure the appropriate address
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# range
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ctrl.range = m5.objects.AddrRange(r.start, size = r.size(),
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intlvHighBit = \
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intlv_low_bit + intlv_bits,
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intlvBits = intlv_bits,
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intlvMatch = i)
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mem_ctrls.append(ctrl)
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system.mem_ctrls = mem_ctrls
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# Connect the controllers to the membus
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for i in xrange(nbr_mem_ctrls):
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system.mem_ctrls[i].port = system.membus.master
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