239a89e713
src/arch/alpha/faults.hh:
Only use pagetable.hh in FS
src/arch/alpha/pagetable.hh:
pagetable.hh should only be included in FS, so protecting it internally should be unnecessary.
src/cpu/exetrace.cc:
Only use tlb.hh in FS
--HG--
extra : convert_revision : 91ea61f2e7970e7146b6d407ee250fcb20cd4d48
425 lines
15 KiB
C++
425 lines
15 KiB
C++
/*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Lisa Hsu
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* Nathan Binkert
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* Steve Raasch
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*/
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#include <fstream>
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#include <iomanip>
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#include <sys/ipc.h>
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#include <sys/shm.h>
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#include "arch/regfile.hh"
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#include "arch/utility.hh"
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#include "base/loader/symtab.hh"
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#include "config/full_system.hh"
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#include "cpu/base.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/static_inst.hh"
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#include "sim/param.hh"
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#include "sim/system.hh"
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#if FULL_SYSTEM
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#include "arch/tlb.hh"
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#endif
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//XXX This is temporary
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#include "arch/isa_specific.hh"
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#include "cpu/m5legion_interface.h"
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using namespace std;
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using namespace TheISA;
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namespace Trace {
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SharedData *shared_data = NULL;
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}
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////////////////////////////////////////////////////////////////////////
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//
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// Methods for the InstRecord object
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//
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void
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Trace::InstRecord::dump(ostream &outs)
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{
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if (flags[PRINT_REG_DELTA])
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{
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#if THE_ISA == SPARC_ISA
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//Don't print what happens for each micro-op, just print out
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//once at the last op, and for regular instructions.
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if(!staticInst->isMicroOp() || staticInst->isLastMicroOp())
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{
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static uint64_t regs[32] = {
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0};
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static uint64_t ccr = 0;
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static uint64_t y = 0;
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static uint64_t floats[32];
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uint64_t newVal;
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static const char * prefixes[4] = {"G", "O", "L", "I"};
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outs << hex;
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outs << "PC = " << thread->readNextPC();
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outs << " NPC = " << thread->readNextNPC();
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newVal = thread->readMiscReg(SparcISA::MISCREG_CCR);
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if(newVal != ccr)
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{
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outs << " CCR = " << newVal;
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ccr = newVal;
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}
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newVal = thread->readMiscReg(SparcISA::MISCREG_Y);
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if(newVal != y)
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{
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outs << " Y = " << newVal;
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y = newVal;
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}
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for(int y = 0; y < 4; y++)
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{
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for(int x = 0; x < 8; x++)
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{
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int index = x + 8 * y;
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newVal = thread->readIntReg(index);
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if(regs[index] != newVal)
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{
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outs << " " << prefixes[y] << dec << x << " = " << hex << newVal;
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regs[index] = newVal;
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}
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}
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}
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for(int y = 0; y < 32; y++)
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{
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newVal = thread->readFloatRegBits(2 * y, 64);
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if(floats[y] != newVal)
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{
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outs << " F" << dec << (2 * y) << " = " << hex << newVal;
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floats[y] = newVal;
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}
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}
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outs << dec << endl;
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}
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#endif
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}
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else if (flags[INTEL_FORMAT]) {
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#if FULL_SYSTEM
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bool is_trace_system = (thread->getCpuPtr()->system->name() == trace_system);
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#else
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bool is_trace_system = true;
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#endif
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if (is_trace_system) {
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ccprintf(outs, "%7d ) ", cycle);
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outs << "0x" << hex << PC << ":\t";
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if (staticInst->isLoad()) {
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outs << "<RD 0x" << hex << addr;
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outs << ">";
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} else if (staticInst->isStore()) {
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outs << "<WR 0x" << hex << addr;
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outs << ">";
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}
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outs << endl;
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}
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} else {
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if (flags[PRINT_CYCLE])
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ccprintf(outs, "%7d: ", cycle);
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outs << thread->getCpuPtr()->name() << " ";
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if (flags[TRACE_MISSPEC])
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outs << (misspeculating ? "-" : "+") << " ";
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if (flags[PRINT_THREAD_NUM])
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outs << "T" << thread->getThreadNum() << " : ";
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std::string sym_str;
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Addr sym_addr;
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if (debugSymbolTable
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&& debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr)
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&& flags[PC_SYMBOL]) {
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if (PC != sym_addr)
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sym_str += csprintf("+%d", PC - sym_addr);
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outs << "@" << sym_str << " : ";
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}
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else {
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outs << "0x" << hex << PC << " : ";
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}
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//
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// Print decoded instruction
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//
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#if defined(__GNUC__) && (__GNUC__ < 3)
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// There's a bug in gcc 2.x library that prevents setw()
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// from working properly on strings
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string mc(staticInst->disassemble(PC, debugSymbolTable));
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while (mc.length() < 26)
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mc += " ";
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outs << mc;
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#else
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outs << setw(26) << left << staticInst->disassemble(PC, debugSymbolTable);
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#endif
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outs << " : ";
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if (flags[PRINT_OP_CLASS]) {
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outs << opClassStrings[staticInst->opClass()] << " : ";
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}
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if (flags[PRINT_RESULT_DATA] && data_status != DataInvalid) {
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outs << " D=";
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#if 0
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if (data_status == DataDouble)
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ccprintf(outs, "%f", data.as_double);
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else
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ccprintf(outs, "%#018x", data.as_int);
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#else
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ccprintf(outs, "%#018x", data.as_int);
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#endif
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}
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if (flags[PRINT_EFF_ADDR] && addr_valid)
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outs << " A=0x" << hex << addr;
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if (flags[PRINT_INT_REGS] && regs_valid) {
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for (int i = 0; i < TheISA::NumIntRegs;)
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for (int j = i + 1; i <= j; i++)
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ccprintf(outs, "r%02d = %#018x%s", i,
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iregs->regs.readReg(i),
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((i == j) ? "\n" : " "));
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outs << "\n";
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}
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if (flags[PRINT_FETCH_SEQ] && fetch_seq_valid)
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outs << " FetchSeq=" << dec << fetch_seq;
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if (flags[PRINT_CP_SEQ] && cp_seq_valid)
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outs << " CPSeq=" << dec << cp_seq;
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//
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// End of line...
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//
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outs << endl;
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}
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#if THE_ISA == SPARC_ISA
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// Compare
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if (flags[LEGION_LOCKSTEP])
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{
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bool compared = false;
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bool diffPC = false;
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bool diffInst = false;
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bool diffRegs = false;
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Addr m5Pc, lgnPc;
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if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) {
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while (!compared) {
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m5Pc = PC & TheISA::PAddrImplMask;
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lgnPc = shared_data->pc & TheISA::PAddrImplMask;
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if (shared_data->flags == OWN_M5) {
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if (lgnPc != m5Pc)
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diffPC = true;
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if (shared_data->instruction != staticInst->machInst)
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diffInst = true;
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for (int i = 0; i < TheISA::NumRegularIntRegs; i++) {
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if (thread->readIntReg(i) != shared_data->intregs[i]) {
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diffRegs = true;
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}
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}
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if (diffPC || diffInst || diffRegs ) {
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outs << "Differences found between M5 and Legion:";
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if (diffPC)
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outs << " [PC]";
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if (diffInst)
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outs << " [Instruction]";
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if (diffRegs)
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outs << " [IntRegs]";
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outs << endl << endl;
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outs << right << setfill(' ') << setw(15)
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<< "M5 PC: " << "0x"<< setw(16) << setfill('0')
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<< hex << m5Pc << endl;
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outs << setfill(' ') << setw(15)
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<< "Legion PC: " << "0x"<< setw(16) << setfill('0') << hex
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<< lgnPc << endl << endl;
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outs << setfill(' ') << setw(15)
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<< "M5 Inst: " << "0x"<< setw(8)
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<< setfill('0') << hex << staticInst->machInst
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<< staticInst->disassemble(m5Pc, debugSymbolTable)
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<< endl;
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StaticInstPtr legionInst = StaticInst::decode(makeExtMI(shared_data->instruction, thread));
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outs << setfill(' ') << setw(15)
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<< " Legion Inst: "
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<< "0x" << setw(8) << setfill('0') << hex
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<< shared_data->instruction
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<< legionInst->disassemble(lgnPc, debugSymbolTable)
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<< endl;
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outs << endl;
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static const char * regtypes[4] = {"%g", "%o", "%l", "%i"};
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for(int y = 0; y < 4; y++)
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{
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for(int x = 0; x < 8; x++)
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{
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outs << regtypes[y] << x << " " ;
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outs << "0x" << hex << setw(16) << thread->readIntReg(y*8+x);
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if (thread->readIntReg(y*8 + x) != shared_data->intregs[y*8+x])
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outs << " X ";
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else
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outs << " | ";
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outs << "0x" << setw(16) << hex << shared_data->intregs[y*8+x]
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<< endl;
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}
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}
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fatal("Differences found between Legion and M5\n");
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}
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compared = true;
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shared_data->flags = OWN_LEGION;
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}
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} // while
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} // if not microop
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}
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#endif
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}
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vector<bool> Trace::InstRecord::flags(NUM_BITS);
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string Trace::InstRecord::trace_system;
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////////////////////////////////////////////////////////////////////////
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//
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// Parameter space for per-cycle execution address tracing options.
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// Derive from ParamContext so we can override checkParams() function.
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//
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class ExecutionTraceParamContext : public ParamContext
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{
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public:
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ExecutionTraceParamContext(const string &_iniSection)
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: ParamContext(_iniSection)
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{
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}
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void checkParams(); // defined at bottom of file
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};
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ExecutionTraceParamContext exeTraceParams("exetrace");
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Param<bool> exe_trace_spec(&exeTraceParams, "speculative",
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"capture speculative instructions", true);
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Param<bool> exe_trace_print_cycle(&exeTraceParams, "print_cycle",
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"print cycle number", true);
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Param<bool> exe_trace_print_opclass(&exeTraceParams, "print_opclass",
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"print op class", true);
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Param<bool> exe_trace_print_thread(&exeTraceParams, "print_thread",
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"print thread number", true);
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Param<bool> exe_trace_print_effaddr(&exeTraceParams, "print_effaddr",
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"print effective address", true);
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Param<bool> exe_trace_print_data(&exeTraceParams, "print_data",
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"print result data", true);
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Param<bool> exe_trace_print_iregs(&exeTraceParams, "print_iregs",
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"print all integer regs", false);
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Param<bool> exe_trace_print_fetchseq(&exeTraceParams, "print_fetchseq",
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"print fetch sequence number", false);
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Param<bool> exe_trace_print_cp_seq(&exeTraceParams, "print_cpseq",
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"print correct-path sequence number", false);
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Param<bool> exe_trace_print_reg_delta(&exeTraceParams, "print_reg_delta",
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"print which registers changed to what", false);
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Param<bool> exe_trace_pc_symbol(&exeTraceParams, "pc_symbol",
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"Use symbols for the PC if available", true);
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Param<bool> exe_trace_intel_format(&exeTraceParams, "intel_format",
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"print trace in intel compatible format", false);
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Param<bool> exe_trace_legion_lockstep(&exeTraceParams, "legion_lockstep",
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"Compare sim state to legion state every cycle",
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false);
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Param<string> exe_trace_system(&exeTraceParams, "trace_system",
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"print trace of which system (client or server)",
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"client");
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//
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// Helper function for ExecutionTraceParamContext::checkParams() just
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// to get us into the InstRecord namespace
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//
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void
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Trace::InstRecord::setParams()
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{
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flags[TRACE_MISSPEC] = exe_trace_spec;
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flags[PRINT_CYCLE] = exe_trace_print_cycle;
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flags[PRINT_OP_CLASS] = exe_trace_print_opclass;
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flags[PRINT_THREAD_NUM] = exe_trace_print_thread;
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flags[PRINT_RESULT_DATA] = exe_trace_print_effaddr;
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flags[PRINT_EFF_ADDR] = exe_trace_print_data;
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flags[PRINT_INT_REGS] = exe_trace_print_iregs;
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flags[PRINT_FETCH_SEQ] = exe_trace_print_fetchseq;
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flags[PRINT_CP_SEQ] = exe_trace_print_cp_seq;
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flags[PRINT_REG_DELTA] = exe_trace_print_reg_delta;
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flags[PC_SYMBOL] = exe_trace_pc_symbol;
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flags[INTEL_FORMAT] = exe_trace_intel_format;
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flags[LEGION_LOCKSTEP] = exe_trace_legion_lockstep;
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trace_system = exe_trace_system;
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// If were going to be in lockstep with Legion
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// Setup shared memory, and get otherwise ready
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if (flags[LEGION_LOCKSTEP]) {
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int shmfd = shmget('M' << 24 | getuid(), sizeof(SharedData), 0777);
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if (shmfd < 0)
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fatal("Couldn't get shared memory fd. Is Legion running?");
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shared_data = (SharedData*)shmat(shmfd, NULL, SHM_RND);
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if (shared_data == (SharedData*)-1)
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fatal("Couldn't allocate shared memory");
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if (shared_data->flags != OWN_M5)
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fatal("Shared memory has invalid owner");
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if (shared_data->version != VERSION)
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fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION,
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shared_data->version);
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// step legion forward one cycle so we can get register values
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shared_data->flags = OWN_LEGION;
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}
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}
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void
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ExecutionTraceParamContext::checkParams()
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{
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Trace::InstRecord::setParams();
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}
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