1086 lines
124 KiB
Plaintext
1086 lines
124 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.022820 # Number of seconds simulated
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sim_ticks 22819771500 # Number of ticks simulated
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final_tick 22819771500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 186519 # Simulator instruction rate (inst/s)
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host_op_rate 186519 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 53476835 # Simulator tick rate (ticks/s)
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host_mem_usage 263708 # Number of bytes of host memory used
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host_seconds 426.72 # Real time elapsed on the host
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sim_insts 79591756 # Number of instructions simulated
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sim_ops 79591756 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states
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system.physmem.bytes_read::cpu.inst 414016 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 10170944 # Number of bytes read from this memory
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system.physmem.bytes_read::total 10584960 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 414016 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 414016 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 7372608 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7372608 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 6469 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 158921 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 165390 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 115197 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 115197 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 18142864 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 445707530 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 463850394 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 18142864 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 18142864 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 323079835 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 323079835 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 323079835 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 18142864 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 445707530 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 786930228 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 165390 # Number of read requests accepted
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system.physmem.writeReqs 115197 # Number of write requests accepted
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system.physmem.readBursts 165390 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 115197 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 10584512 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue
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system.physmem.bytesWritten 7370752 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 10584960 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 7372608 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 10310 # Per bank write bursts
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system.physmem.perBankRdBursts::1 10353 # Per bank write bursts
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system.physmem.perBankRdBursts::2 10221 # Per bank write bursts
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system.physmem.perBankRdBursts::3 10036 # Per bank write bursts
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system.physmem.perBankRdBursts::4 10349 # Per bank write bursts
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system.physmem.perBankRdBursts::5 10326 # Per bank write bursts
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system.physmem.perBankRdBursts::6 9802 # Per bank write bursts
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system.physmem.perBankRdBursts::7 10209 # Per bank write bursts
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system.physmem.perBankRdBursts::8 10557 # Per bank write bursts
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system.physmem.perBankRdBursts::9 10617 # Per bank write bursts
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system.physmem.perBankRdBursts::10 10516 # Per bank write bursts
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system.physmem.perBankRdBursts::11 10223 # Per bank write bursts
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system.physmem.perBankRdBursts::12 10279 # Per bank write bursts
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system.physmem.perBankRdBursts::13 10557 # Per bank write bursts
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system.physmem.perBankRdBursts::14 10475 # Per bank write bursts
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system.physmem.perBankRdBursts::15 10553 # Per bank write bursts
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system.physmem.perBankWrBursts::0 7167 # Per bank write bursts
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system.physmem.perBankWrBursts::1 7277 # Per bank write bursts
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system.physmem.perBankWrBursts::2 7300 # Per bank write bursts
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system.physmem.perBankWrBursts::3 7008 # Per bank write bursts
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system.physmem.perBankWrBursts::4 7142 # Per bank write bursts
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system.physmem.perBankWrBursts::5 7300 # Per bank write bursts
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system.physmem.perBankWrBursts::6 6892 # Per bank write bursts
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system.physmem.perBankWrBursts::7 7158 # Per bank write bursts
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system.physmem.perBankWrBursts::8 7240 # Per bank write bursts
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system.physmem.perBankWrBursts::9 7069 # Per bank write bursts
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system.physmem.perBankWrBursts::10 7202 # Per bank write bursts
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system.physmem.perBankWrBursts::11 7121 # Per bank write bursts
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system.physmem.perBankWrBursts::12 7069 # Per bank write bursts
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system.physmem.perBankWrBursts::13 7390 # Per bank write bursts
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system.physmem.perBankWrBursts::14 7350 # Per bank write bursts
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system.physmem.perBankWrBursts::15 7483 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 22819740500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 165390 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 115197 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 51469 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 42313 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 37455 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 34126 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 585 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 604 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 2061 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 4086 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 5723 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 7152 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 7161 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 7166 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 7176 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 7208 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 7248 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 7623 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 7486 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 7552 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 9529 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 9432 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 7837 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 8541 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 945 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 29 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 44648 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 402.130084 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 240.586732 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 367.720381 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 13091 29.32% 29.32% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 8315 18.62% 47.94% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 5360 12.01% 59.95% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 2692 6.03% 65.98% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 2549 5.71% 71.69% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 1575 3.53% 75.22% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 1705 3.82% 79.03% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 1125 2.52% 81.55% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 8236 18.45% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 44648 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 7096 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 23.304961 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::gmean 17.955367 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 317.126574 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-1023 7095 99.99% 99.99% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 7096 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 7096 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 16.229989 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 16.211978 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 0.816035 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16 6480 91.32% 91.32% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::17 18 0.25% 91.57% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::18 334 4.71% 96.28% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::19 161 2.27% 98.55% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::20 74 1.04% 99.59% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::21 24 0.34% 99.93% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::22 2 0.03% 99.96% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::23 1 0.01% 99.97% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::30 2 0.03% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::total 7096 # Writes before turning the bus around for reads
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system.physmem.totQLat 7131716500 # Total ticks spent queuing
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system.physmem.totMemAccLat 10232647750 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 826915000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 43122.43 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 61872.43 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 463.83 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 323.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 463.85 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 323.08 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 6.15 # Data bus utilization in percentage
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system.physmem.busUtilRead 3.62 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 2.52 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.98 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing
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system.physmem.readRowHits 145971 # Number of row buffer hits during reads
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system.physmem.writeRowHits 89923 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 88.26 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 78.06 # Row buffer hit rate for writes
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system.physmem.avgGap 81328.57 # Average gap between requests
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system.physmem.pageHitRate 84.07 # Row buffer hit rate, read and write combined
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system.physmem_0.actEnergy 153103020 # Energy for activate commands per rank (pJ)
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system.physmem_0.preEnergy 81361005 # Energy for precharge commands per rank (pJ)
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system.physmem_0.readEnergy 582666840 # Energy for read commands per rank (pJ)
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system.physmem_0.writeEnergy 298813680 # Energy for write commands per rank (pJ)
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system.physmem_0.refreshEnergy 1398920640.000000 # Energy for refresh commands per rank (pJ)
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system.physmem_0.actBackEnergy 1820142240 # Energy for active background per rank (pJ)
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system.physmem_0.preBackEnergy 87895200 # Energy for precharge background per rank (pJ)
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system.physmem_0.actPowerDownEnergy 2523555300 # Energy for active power-down per rank (pJ)
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system.physmem_0.prePowerDownEnergy 1884269760 # Energy for precharge power-down per rank (pJ)
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system.physmem_0.selfRefreshEnergy 2191410645 # Energy for self refresh per rank (pJ)
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system.physmem_0.totalEnergy 11023267740 # Total energy per rank (pJ)
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system.physmem_0.averagePower 483.057740 # Core power per rank (mW)
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system.physmem_0.totalIdleTime 18596850000 # Total Idle time Per DRAM Rank
|
|
system.physmem_0.memoryStateTime::IDLE 135529000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 594334000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::SREF 8155766000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 4906976500 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 3493009750 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 5534156250 # Time in different power states
|
|
system.physmem_1.actEnergy 165747960 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 88078155 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 598167780 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 302363280 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 1429652640.000000 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 1911531480 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 82258560 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.actPowerDownEnergy 2724848520 # Energy for active power-down per rank (pJ)
|
|
system.physmem_1.prePowerDownEnergy 1880202720 # Energy for precharge power-down per rank (pJ)
|
|
system.physmem_1.selfRefreshEnergy 2026371015 # Energy for self refresh per rank (pJ)
|
|
system.physmem_1.totalEnergy 11210189940 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 491.248979 # Core power per rank (mW)
|
|
system.physmem_1.totalIdleTime 18411251500 # Total Idle time Per DRAM Rank
|
|
system.physmem_1.memoryStateTime::IDLE 119903000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 607208000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::SREF 7539541250 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 4896374750 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 3681289750 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 5975454750 # Time in different power states
|
|
system.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.branchPred.lookups 16458678 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 10655092 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 320474 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 8794743 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 7227596 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 82.180866 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 1974394 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 3324 # Number of incorrect RAS predictions.
|
|
system.cpu.branchPred.indirectLookups 39317 # Number of indirect predictor lookups.
|
|
system.cpu.branchPred.indirectHits 31522 # Number of indirect target hits.
|
|
system.cpu.branchPred.indirectMisses 7795 # Number of indirect misses.
|
|
system.cpu.branchPredindirectMispredicted 2656 # Number of mispredicted indirect branches.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 22495361 # DTB read hits
|
|
system.cpu.dtb.read_misses 227004 # DTB read misses
|
|
system.cpu.dtb.read_acv 16 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 22722365 # DTB read accesses
|
|
system.cpu.dtb.write_hits 15803250 # DTB write hits
|
|
system.cpu.dtb.write_misses 44602 # DTB write misses
|
|
system.cpu.dtb.write_acv 6 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 15847852 # DTB write accesses
|
|
system.cpu.dtb.data_hits 38298611 # DTB hits
|
|
system.cpu.dtb.data_misses 271606 # DTB misses
|
|
system.cpu.dtb.data_acv 22 # DTB access violations
|
|
system.cpu.dtb.data_accesses 38570217 # DTB accesses
|
|
system.cpu.itb.fetch_hits 13713928 # ITB hits
|
|
system.cpu.itb.fetch_misses 29641 # ITB misses
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
system.cpu.itb.fetch_accesses 13743569 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 4583 # Number of system calls
|
|
system.cpu.pwrStateResidencyTicks::ON 22819771500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.numCycles 45639548 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 15527632 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 104958165 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 16458678 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 9233512 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 28526394 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 879432 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.TlbCycles 1335 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu.fetch.MiscStallCycles 4713 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 342280 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 91 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 13713928 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 186437 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 44842161 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 2.340613 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 3.113400 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 25352844 56.54% 56.54% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 1513864 3.38% 59.91% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 1375551 3.07% 62.98% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 1499198 3.34% 66.32% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 4186922 9.34% 75.66% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 1824752 4.07% 79.73% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 669001 1.49% 81.22% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 1050081 2.34% 83.56% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 7369948 16.44% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 44842161 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.360623 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 2.299720 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 14899514 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 10738608 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 18272960 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 588305 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 342774 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 3699945 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 98528 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 102994976 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 312859 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 342774 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 15240271 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 5029380 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 97820 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 18506228 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 5625688 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 102003977 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 6871 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 88609 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 422499 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 5043111 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 61324692 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 123005722 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 122686459 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 319262 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 8777811 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 5683 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 5735 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 2339310 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 23131891 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 16353716 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 1249387 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 502474 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 90699211 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 5558 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 88573949 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 67838 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 11113012 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 4439512 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 975 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 44842161 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.975238 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 2.240795 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 18402096 41.04% 41.04% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 5711089 12.74% 53.77% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 5105714 11.39% 65.16% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 4382501 9.77% 74.93% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 4313150 9.62% 84.55% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 2637224 5.88% 90.43% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 1940283 4.33% 94.76% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 1377321 3.07% 97.83% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 972783 2.17% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 44842161 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 241463 9.57% 9.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 9.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 9.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 9.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 9.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 9.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 1168337 46.29% 55.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 1114013 44.14% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 49366935 55.74% 55.74% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 43991 0.05% 55.78% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.78% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 121159 0.14% 55.92% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 93 0.00% 55.92% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 120693 0.14% 56.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 63 0.00% 56.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 39087 0.04% 56.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 22887844 25.84% 81.94% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 15994084 18.06% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 88573949 # Type of FU issued
|
|
system.cpu.iq.rate 1.940728 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 2523813 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.028494 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 223970382 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 101417859 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 86818116 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 611328 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 420538 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 299902 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 90791946 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 305816 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 1674439 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 2855253 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 5856 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 20836 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 1740339 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 3017 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 190756 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 342774 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 1435868 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 3107979 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 100192818 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 116708 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 23131891 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 16353716 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 5558 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 3773 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 3106841 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 20836 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 111267 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 152585 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 263852 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 87883972 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 22722991 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 689977 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 9488049 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 38571182 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 15118040 # Number of branches executed
|
|
system.cpu.iew.exec_stores 15848191 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.925610 # Inst execution rate
|
|
system.cpu.iew.wb_sent 87519959 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 87118018 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 33843453 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 44250497 # num instructions consuming a value
|
|
system.cpu.iew.wb_rate 1.908827 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.764815 # average fanout of values written-back
|
|
system.cpu.commit.commitSquashedInsts 8632074 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 223532 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 43575084 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 2.027321 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.870724 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 22117259 50.76% 50.76% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 6277727 14.41% 65.16% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 2900957 6.66% 71.82% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 1737731 3.99% 75.81% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 1677521 3.85% 79.66% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 1124025 2.58% 82.24% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 1202727 2.76% 85.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 795829 1.83% 86.82% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 5741308 13.18% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 43575084 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 88340672 # Number of instructions committed
|
|
system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 34890015 # Number of memory references committed
|
|
system.cpu.commit.loads 20276638 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 13754477 # Number of branches committed
|
|
system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 77942044 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 1661057 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 8748916 9.90% 9.90% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 44394798 50.25% 60.16% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 41101 0.05% 60.20% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 60.20% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 114304 0.13% 60.33% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 84 0.00% 60.33% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 113640 0.13% 60.46% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 50 0.00% 60.46% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 37764 0.04% 60.51% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 60.51% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 60.51% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 60.51% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 60.51% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 60.51% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 60.51% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 60.51% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 60.51% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 60.51% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 60.51% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 60.51% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 60.51% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 60.51% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 60.51% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 60.51% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 60.51% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 60.51% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 60.51% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 60.51% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 60.51% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 60.51% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 20276638 22.95% 83.46% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 5741308 # number cycles where commit BW limit reached
|
|
system.cpu.rob.rob_reads 133489180 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 195215826 # The number of ROB writes
|
|
system.cpu.timesIdled 45373 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 797387 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
|
|
system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 0.573421 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.573421 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.743921 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.743921 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 116327818 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 57658172 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 255578 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 240399 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 38260 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.dcache.tags.replacements 201413 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4069.948439 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 33978122 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 205509 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 165.336418 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 244590500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4069.948439 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.993640 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.993640 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2488 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 1533 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 70808789 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 70808789 # Number of data accesses
|
|
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 20418812 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 20418812 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 13559258 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 13559258 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 52 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 52 # number of LoadLockedReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 33978070 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 33978070 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 33978070 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 33978070 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 269399 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 269399 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1054119 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1054119 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 1323518 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 1323518 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 1323518 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 1323518 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 19371317500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 19371317500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 94432641988 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 94432641988 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 113803959488 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 113803959488 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 113803959488 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 113803959488 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 20688211 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 20688211 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 52 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 52 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 35301588 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 35301588 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 35301588 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 35301588 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.013022 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.013022 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.072134 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.072134 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.037492 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.037492 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.037492 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.037492 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71905.677081 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 71905.677081 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89584.422620 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 89584.422620 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 85985.955225 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 85985.955225 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 85985.955225 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 85985.955225 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 7415690 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 299 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 82797 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 89.564719 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 149.500000 # average number of cycles each access was blocked
|
|
system.cpu.dcache.writebacks::writebacks 168510 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 168510 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 207284 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 207284 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910725 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 910725 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 1118009 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 1118009 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 1118009 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 1118009 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62115 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 62115 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143394 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 143394 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 205509 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 205509 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 205509 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 205509 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3617431500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3617431500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15283982713 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 15283982713 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18901414213 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 18901414213 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18901414213 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 18901414213 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003002 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003002 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005822 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.005822 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005822 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.005822 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58237.647911 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58237.647911 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106587.323828 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106587.323828 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 91973.656691 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 91973.656691 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 91973.656691 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 91973.656691 # average overall mshr miss latency
|
|
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.icache.tags.replacements 90457 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 1914.919853 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 13608920 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 92505 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 147.115507 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 19216549500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1914.919853 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.935019 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.935019 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 1462 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 388 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 27520357 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 27520357 # Number of data accesses
|
|
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 13608920 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 13608920 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 13608920 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 13608920 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 13608920 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 13608920 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 105006 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 105006 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 105006 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 105006 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 105006 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 105006 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 2088801499 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 2088801499 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 2088801499 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 2088801499 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 2088801499 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 2088801499 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 13713926 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 13713926 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 13713926 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 13713926 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 13713926 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 13713926 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007657 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.007657 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.007657 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.007657 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.007657 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.007657 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19892.210912 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 19892.210912 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 19892.210912 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 19892.210912 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 19892.210912 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 19892.210912 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 683 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 42.687500 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.writebacks::writebacks 90457 # number of writebacks
|
|
system.cpu.icache.writebacks::total 90457 # number of writebacks
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12500 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 12500 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 12500 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 12500 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 12500 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 12500 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 92506 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 92506 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 92506 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 92506 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 92506 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 92506 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1693618500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 1693618500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1693618500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 1693618500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1693618500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 1693618500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006745 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006745 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006745 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.006745 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006745 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.006745 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18308.201630 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18308.201630 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18308.201630 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 18308.201630 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18308.201630 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 18308.201630 # average overall mshr miss latency
|
|
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.l2cache.tags.replacements 134872 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 31840.102351 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 422133 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 167640 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 2.518092 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 5003072000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 716.868966 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1773.767441 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 29349.465945 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.021877 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.054131 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.895675 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.971683 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2733 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 28770 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1005 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 4886720 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 4886720 # Number of data accesses
|
|
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.l2cache.WritebackDirty_hits::writebacks 168510 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackDirty_hits::total 168510 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackClean_hits::writebacks 90457 # number of WritebackClean hits
|
|
system.cpu.l2cache.WritebackClean_hits::total 90457 # number of WritebackClean hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 12581 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 12581 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 86036 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 86036 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 34007 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::total 34007 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 86036 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 46588 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 132624 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 86036 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 46588 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 132624 # number of overall hits
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 130815 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 130815 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 6470 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 6470 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 28106 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 28106 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 6470 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 158921 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 165391 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 6470 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 158921 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 165391 # number of overall misses
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14933033000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 14933033000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 647096000 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 647096000 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3162742000 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 3162742000 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 647096000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 18095775000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 18742871000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 647096000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 18095775000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 18742871000 # number of overall miss cycles
|
|
system.cpu.l2cache.WritebackDirty_accesses::writebacks 168510 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackDirty_accesses::total 168510 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::writebacks 90457 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::total 90457 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 143396 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 143396 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 92506 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 92506 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 62113 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 62113 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 92506 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 205509 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 298015 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 92506 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 205509 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 298015 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.912264 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.912264 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.069941 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.069941 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.452498 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.452498 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.069941 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.773304 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.554975 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.069941 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.773304 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.554975 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 114153.827925 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 114153.827925 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 100014.837713 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 100014.837713 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 112529.068526 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 112529.068526 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 100014.837713 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 113866.480830 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 113324.612585 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 100014.837713 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 113866.480830 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 113324.612585 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.writebacks::writebacks 115198 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 115198 # number of writebacks
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 111 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::total 111 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130815 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 130815 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6470 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6470 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 28106 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 28106 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 6470 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 158921 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 165391 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 6470 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 158921 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 165391 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13624883000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13624883000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 582406000 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 582406000 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2881682000 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2881682000 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 582406000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16506565000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 17088971000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 582406000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16506565000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 17088971000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912264 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912264 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.069941 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.069941 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.452498 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.452498 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.069941 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773304 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.554975 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.069941 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773304 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.554975 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 104153.827925 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 104153.827925 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 90016.383308 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 90016.383308 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 102529.068526 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 102529.068526 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 90016.383308 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 103866.480830 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 103324.673048 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 90016.383308 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 103866.480830 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 103324.673048 # average overall mshr miss latency
|
|
system.cpu.toL2Bus.snoop_filter.tot_requests 589885 # Total number of requests made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_requests 291870 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.tot_snoops 4237 # Total number of snoops made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4237 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 154618 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackDirty 283708 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackClean 90457 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::CleanEvict 52577 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 143396 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 143396 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 92506 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 62113 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 275468 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612431 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 887899 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11709568 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23937216 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 35646784 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 134872 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoopTraffic 7372672 # Total snoop traffic (bytes)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 432887 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 0.009788 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.098448 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 428650 99.02% 99.02% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 4237 0.98% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 432887 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 553909500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 138764985 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 308272981 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
|
|
system.membus.snoop_filter.tot_requests 296135 # Total number of requests made to the snoop filter.
|
|
system.membus.snoop_filter.hit_single_requests 130745 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
|
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.membus.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states
|
|
system.membus.trans_dist::ReadResp 34575 # Transaction distribution
|
|
system.membus.trans_dist::WritebackDirty 115197 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 15548 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 130815 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 130815 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 34575 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 461525 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 461525 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17957568 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 17957568 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
|
system.membus.snoop_fanout::samples 165390 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 165390 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 165390 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 779827500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 3.4 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 851966000 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 3.7 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|