81d5ffe7de
some sundry problems with new interface
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/baddev.cc:
dev/baddev.hh:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunami_uart.cc:
dev/tsunami_uart.hh:
Fixed to use new FunctionalMemory interface
--HG--
extra : convert_revision : bee98e6285d92f28fafacf919ab06eaf333a9b56
99 lines
3.2 KiB
C++
99 lines
3.2 KiB
C++
/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* @file
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* PCI configspace devices
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*/
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#ifndef __PCI_DEV_HH__
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#define __PCI_DEV_HH__
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#include "dev/pcireg.h"
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#include "sim/sim_object.hh"
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#include "mem/functional_mem/functional_memory.hh"
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class PCIConfigAll;
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class MemoryController;
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class PciConfigData : public SimObject
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{
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public:
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PciConfigData(const std::string &name)
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: SimObject(name)
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{
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memset(config.data, 0, sizeof(config.data));
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memset(BARAddrs, 0, sizeof(BARAddrs));
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memset(BARSize, 0, sizeof(BARSize));
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}
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PCIConfig config;
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uint32_t BARSize[6];
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Addr BARAddrs[6];
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};
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/**
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* PCI device, base implemnation is only config space.
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* Each device is connected to a PCIConfigSpace device
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* which returns -1 for everything but the pcidevs that
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* register with it. This object registers with the PCIConfig space
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* object.
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*/
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class PciDev : public FunctionalMemory
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{
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protected:
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MemoryController *MMU;
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PCIConfigAll *ConfigSpace;
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PciConfigData *ConfigData;
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uint32_t Bus;
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uint32_t Device;
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uint32_t Function;
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PCIConfig config;
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uint32_t BARSize[6];
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Addr BARAddrs[6];
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public:
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PciDev(const std::string &name, MemoryController *mmu, PCIConfigAll *cf,
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PciConfigData *cd, uint32_t bus, uint32_t dev, uint32_t func);
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virtual Fault read(MemReqPtr &req, uint8_t *data) {
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return No_Fault;
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}
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virtual Fault write(MemReqPtr &req, const uint8_t *data) {
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return No_Fault;
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}
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virtual void WriteConfig(int offset, int size, uint32_t data);
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virtual void ReadConfig(int offset, int size, uint8_t *data);
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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};
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#endif // __PCI_DEV_HH__
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