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gem5/util/cpt_upgraders
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Curtis Dunham 2f14baaabc arm, dev: refactor GIC Pl390 GICD_ITARGETSRn handling 
The aforementioned registers (Interrupt Processor Targets Registers) are
banked per-CPU, but are read-only.  This patch eliminates the per-CPU
storage of these values that are simply computed.

Change-Id: I52cafc2f58e87dd54239a71326c01f4923544689
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2442
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03 16:51:46 +00:00
..
arm-ccregs.py sim: tag-based checkpoint versioning 2015-09-02 15:23:30 -05:00
arm-contextidr-el2.py sim: tag-based checkpoint versioning 2015-09-02 15:23:30 -05:00
arm-gem5-gic-ext.py dev, arm: Add gem5 extensions to support more than 8 cores 2015-09-18 16:49:28 +01:00
arm-gicv2-banked-regs.py arm, dev: refactor GIC Pl390 GICD_ITARGETSRn handling 2017-04-03 16:51:46 +00:00
arm-hdlcd-upgrade.py dev, arm: Rewrite the HDLCD controller 2015-09-11 15:55:46 +01:00
arm-miscreg-teehbr.py sim: tag-based checkpoint versioning 2015-09-02 15:23:30 -05:00
arm-sysreg-mapping-ns.py arm: update AArch{64,32} register mappings 2016-12-19 11:03:27 -06:00
armv8.py sim: tag-based checkpoint versioning 2015-09-02 15:23:30 -05:00
cpu-pid.py sim: tag-based checkpoint versioning 2015-09-02 15:23:30 -05:00
dvfs-perflevel.py sim: tag-based checkpoint versioning 2015-09-02 15:23:30 -05:00
etherswitch.py dist, dev: fix etherswitch upgrade script 2016-12-19 12:12:28 -06:00
ide-dma-abort.py sim: tag-based checkpoint versioning 2015-09-02 15:23:30 -05:00
isa-is-simobject.py sim: tag-based checkpoint versioning 2015-09-02 15:23:30 -05:00
memory-per-range.py sim: tag-based checkpoint versioning 2015-09-02 15:23:30 -05:00
multiple-event-queues.py sim: tag-based checkpoint versioning 2015-09-02 15:23:30 -05:00
process-fdmap-rename.py sim: tag-based checkpoint versioning 2015-09-02 15:23:30 -05:00
remove-arm-cpsr-mode-miscreg.py sim: tag-based checkpoint versioning 2015-09-02 15:23:30 -05:00
ruby-block-size-bytes.py sim: tag-based checkpoint versioning 2015-09-02 15:23:30 -05:00
smt-interrupts.py isa,cpu: Add support for FS SMT Interrupts 2015-09-30 11:14:19 -05:00
x86-add-tlb.py sim: tag-based checkpoint versioning 2015-09-02 15:23:30 -05:00