afbae1ec95
The o3 cpu relies upon instructions that suspend a thread context being flagged as "IsQuiesce". If they are not, unpredictable behavior can occur. This patch fixes that for the x86 ISA.
261 lines
8.7 KiB
Plaintext
261 lines
8.7 KiB
Plaintext
// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
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// Copyright (c) 2011 Mark D. Hill and David A. Wood
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// All rights reserved.
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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//////////////////////////////////////////////////////////////////////////
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//
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// Fault Microop
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//
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//////////////////////////////////////////////////////////////////////////
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output header {{
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class MicroFaultBase : public X86ISA::X86MicroopBase
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{
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protected:
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Fault fault;
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uint8_t cc;
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public:
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MicroFaultBase(ExtMachInst _machInst, const char * instMnem,
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uint64_t setFlags, Fault _fault, uint8_t _cc);
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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};
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class MicroHalt : public X86ISA::X86MicroopBase
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{
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public:
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MicroHalt(ExtMachInst _machInst, const char * instMnem,
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uint64_t setFlags) :
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X86MicroopBase(_machInst, "halt", instMnem,
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setFlags | (ULL(1) << StaticInst::IsNonSpeculative) |
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(ULL(1) << StaticInst::IsQuiesce),
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No_OpClass)
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{
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}
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%(BasicExecDeclare)s
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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};
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}};
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def template MicroFaultDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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%(class_name)s(ExtMachInst _machInst, const char * instMnem,
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uint64_t setFlags, Fault _fault, uint8_t _cc);
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%(BasicExecDeclare)s
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};
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}};
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def template MicroFaultExecute {{
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Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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%(op_decl)s;
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%(op_rd)s;
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if (%(cond_test)s) {
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//Return the fault we were constructed with
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return fault;
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} else {
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return NoFault;
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}
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}
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}};
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output exec {{
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Fault
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MicroHalt::execute(CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord * traceData) const
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{
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xc->tcBase()->suspend();
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return NoFault;
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}
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}};
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output decoder {{
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MicroFaultBase::MicroFaultBase(
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ExtMachInst machInst, const char * instMnem,
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uint64_t setFlags, Fault _fault, uint8_t _cc) :
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X86MicroopBase(machInst, "fault", instMnem, setFlags, No_OpClass),
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fault(_fault), cc(_cc)
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{
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}
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}};
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def template MicroFaultConstructor {{
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%(class_name)s::%(class_name)s(
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ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
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Fault _fault, uint8_t _cc) :
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%(base_class)s(machInst, instMnem, setFlags, _fault, _cc)
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{
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%(constructor)s;
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}
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}};
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output decoder {{
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std::string MicroFaultBase::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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std::stringstream response;
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printMnemonic(response, instMnem, mnemonic);
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if(fault)
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response << fault->name();
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else
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response << "No Fault";
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return response.str();
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}
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std::string MicroHalt::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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std::stringstream response;
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printMnemonic(response, instMnem, mnemonic);
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return response.str();
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}
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}};
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let {{
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class Fault(X86Microop):
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className = "MicroFault"
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def __init__(self, fault, flags=None):
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self.fault = fault
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if flags:
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if not isinstance(flags, (list, tuple)):
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raise Exception, "flags must be a list or tuple of flags"
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self.cond = " | ".join(flags)
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self.className += "Flags"
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else:
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self.cond = "0"
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def getAllocator(self, microFlags):
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allocator = '''new %(class_name)s(machInst, macrocodeBlock,
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%(flags)s, %(fault)s, %(cc)s)''' % {
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"class_name" : self.className,
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"flags" : self.microFlagsText(microFlags),
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"fault" : self.fault,
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"cc" : self.cond}
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return allocator
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iop = InstObjParams("fault", "MicroFaultFlags", "MicroFaultBase",
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{"code": "",
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"cond_test": "checkCondition(ccFlagBits | cfofBits | dfBit | \
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ecfBit | ezfBit, cc)"})
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exec_output = MicroFaultExecute.subst(iop)
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header_output = MicroFaultDeclare.subst(iop)
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decoder_output = MicroFaultConstructor.subst(iop)
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iop = InstObjParams("fault", "MicroFault", "MicroFaultBase",
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{"code": "",
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"cond_test": "true"})
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exec_output += MicroFaultExecute.subst(iop)
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header_output += MicroFaultDeclare.subst(iop)
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decoder_output += MicroFaultConstructor.subst(iop)
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microopClasses["fault"] = Fault
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class Halt(X86Microop):
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className = "MicroHalt"
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def __init__(self):
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pass
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def getAllocator(self, microFlags):
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return "new MicroHalt(machInst, macrocodeBlock, %s)" % \
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self.microFlagsText(microFlags)
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microopClasses["halt"] = Halt
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}};
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def template MicroFenceOpDeclare {{
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class %(class_name)s : public X86ISA::X86MicroopBase
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{
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public:
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%(class_name)s(ExtMachInst _machInst,
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const char * instMnem,
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uint64_t setFlags);
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%(BasicExecDeclare)s
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};
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}};
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def template MicroFenceOpConstructor {{
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%(class_name)s::%(class_name)s(
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ExtMachInst machInst, const char * instMnem, uint64_t setFlags) :
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%(base_class)s(machInst, "%(mnemonic)s", instMnem,
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setFlags, %(op_class)s)
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{
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%(constructor)s;
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}
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}};
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let {{
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class MfenceOp(X86Microop):
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def __init__(self):
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self.className = "Mfence"
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self.mnemonic = "mfence"
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self.instFlags = "| (1ULL << StaticInst::IsMemBarrier)"
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def getAllocator(self, microFlags):
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allocString = '''
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(StaticInstPtr)(new %(class_name)s(machInst,
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macrocodeBlock, %(flags)s))
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'''
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allocator = allocString % {
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"class_name" : self.className,
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"mnemonic" : self.mnemonic,
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"flags" : self.microFlagsText(microFlags) + self.instFlags}
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return allocator
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microopClasses["mfence"] = MfenceOp
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}};
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let {{
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# Build up the all register version of this micro op
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iop = InstObjParams("mfence", "Mfence", 'X86MicroopBase',
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{"code" : ""})
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header_output += MicroFenceOpDeclare.subst(iop)
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decoder_output += MicroFenceOpConstructor.subst(iop)
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exec_output += BasicExecute.subst(iop)
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}};
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