a5802c823f
This changeset adds functionality that allows system calls to retry without affecting thread context state such as the program counter or register values for the associated thread context (when system calls return with a retry fault). This functionality is needed to solve problems with blocking system calls in multi-process or multi-threaded simulations where information is passed between processes/threads. Blocking system calls can cause deadlock because the simulator itself is single threaded. There is only a single thread servicing the event queue which can cause deadlock if the thread hits a blocking system call instruction. To illustrate the problem, consider two processes using the producer/consumer sharing model. The processes can use file descriptors and the read and write calls to pass information to one another. If the consumer calls the blocking read system call before the producer has produced anything, the call will block the event queue (while executing the system call instruction) and deadlock the simulation. The solution implemented in this changeset is to recognize that the system calls will block and then generate a special retry fault. The fault will be sent back up through the function call chain until it is exposed to the cpu model's pipeline where the fault becomes visible. The fault will trigger the cpu model to replay the instruction at a future tick where the call has a chance to succeed without actually going into a blocking state. In subsequent patches, we recognize that a syscall will block by calling a non-blocking poll (from inside the system call implementation) and checking for events. When events show up during the poll, it signifies that the call would not have blocked and the syscall is allowed to proceed (calling an underlying host system call if necessary). If no events are returned from the poll, we generate the fault and try the instruction for the thread context at a distant tick. Note that retrying every tick is not efficient. As an aside, the simulator has some multi-threading support for the event queue, but it is not used by default and needs work. Even if the event queue was completely multi-threaded, meaning that there is a hardware thread on the host servicing a single simulator thread contexts with a 1:1 mapping between them, it's still possible to run into deadlock due to the event queue barriers on quantum boundaries. The solution of replaying at a later tick is the simplest solution and solves the problem generally.
578 lines
20 KiB
Plaintext
578 lines
20 KiB
Plaintext
// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
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// All rights reserved.
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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////////////////////////////////////////////////////////////////////
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//
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// Decode the one byte opcodes
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//
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'X86ISA::OneByteOpcode': decode OPCODE_OP_TOP5 {
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format Inst {
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0x00: decode OPCODE_OP_BOTTOM3 {
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0x6: decode MODE_SUBMODE {
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0x0: UD2();
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default: WarnUnimpl::push_ES();
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}
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0x7: decode MODE_SUBMODE {
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0x0: UD2();
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default: WarnUnimpl::pop_ES();
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}
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default: MultiInst::ADD(OPCODE_OP_BOTTOM3,
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[Eb,Gb], [Ev,Gv],
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[Gb,Eb], [Gv,Ev],
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[rAb,Ib], [rAv,Iz]);
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}
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0x01: decode OPCODE_OP_BOTTOM3 {
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0x6: decode MODE_SUBMODE {
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0x0: UD2();
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default: WarnUnimpl::push_CS();
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}
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//Any time this is seen, it should generate a two byte opcode
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0x7: M5InternalError::error(
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{{"Saw a one byte opcode whose value was 0x0F!"}});
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default: MultiInst::OR(OPCODE_OP_BOTTOM3,
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[Eb,Gb], [Ev,Gv],
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[Gb,Eb], [Gv,Ev],
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[rAb,Ib], [rAv,Iz]);
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}
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0x02: decode OPCODE_OP_BOTTOM3 {
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0x6: decode MODE_SUBMODE {
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0x0: UD2();
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default: WarnUnimpl::push_SS();
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}
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0x7: decode MODE_SUBMODE {
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0x0: UD2();
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default: WarnUnimpl::pop_SS();
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}
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default: MultiInst::ADC(OPCODE_OP_BOTTOM3,
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[Eb,Gb], [Ev,Gv],
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[Gb,Eb], [Gv,Ev],
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[rAb,Ib], [rAv,Iz]);
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}
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0x03: decode OPCODE_OP_BOTTOM3 {
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0x6: decode MODE_SUBMODE {
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0x0: UD2();
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default: WarnUnimpl::push_DS();
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}
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0x7: decode MODE_SUBMODE {
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0x0: UD2();
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default: WarnUnimpl::pop_DS();
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}
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default: MultiInst::SBB(OPCODE_OP_BOTTOM3,
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[Eb,Gb], [Ev,Gv],
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[Gb,Eb], [Gv,Ev],
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[rAb,Ib], [rAv,Iz]);
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}
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0x04: decode OPCODE_OP_BOTTOM3 {
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0x6: M5InternalError::error(
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{{"Tried to execute the ES segment override prefix!"}});
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0x7: decode MODE_SUBMODE {
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0x0: UD2();
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default: WarnUnimpl::daa();
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}
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default: MultiInst::AND(OPCODE_OP_BOTTOM3,
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[Eb,Gb], [Ev,Gv],
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[Gb,Eb], [Gv,Ev],
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[rAb,Ib], [rAv,Iz]);
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}
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0x05: decode OPCODE_OP_BOTTOM3 {
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0x6: M5InternalError::error(
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{{"Tried to execute the CS segment override prefix!"}});
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0x7: decode MODE_SUBMODE {
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0x0: UD2();
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default: WarnUnimpl::das();
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}
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default: MultiInst::SUB(OPCODE_OP_BOTTOM3,
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[Eb,Gb], [Ev,Gv],
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[Gb,Eb], [Gv,Ev],
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[rAb,Ib], [rAv,Iz]);
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}
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0x06: decode OPCODE_OP_BOTTOM3 {
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0x6: M5InternalError::error(
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{{"Tried to execute the SS segment override prefix!"}});
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0x7: decode MODE_SUBMODE {
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0x0: UD2();
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default: WarnUnimpl::aaa();
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}
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default: MultiInst::XOR(OPCODE_OP_BOTTOM3,
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[Eb,Gb], [Ev,Gv],
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[Gb,Eb], [Gv,Ev],
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[rAb,Ib], [rAv,Iz]);
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}
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0x07: decode OPCODE_OP_BOTTOM3 {
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0x6: M5InternalError::error(
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{{"Tried to execute the DS segment override prefix!"}});
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0x7: decode MODE_SUBMODE {
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0x0: UD2();
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default: WarnUnimpl::aas();
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}
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default: MultiInst::CMP(OPCODE_OP_BOTTOM3,
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[Eb,Gb], [Ev,Gv],
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[Gb,Eb], [Gv,Ev],
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[rAb,Ib], [rAv,Iz]);
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}
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0x08: decode MODE_SUBMODE {
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0x0: M5InternalError::error (
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{{"Tried to execute an REX prefix!"}});
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default: INC(Bv);
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}
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0x09: decode MODE_SUBMODE {
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0x0: M5InternalError::error (
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{{"Tried to execute an REX prefix!"}});
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default: DEC(Bv);
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}
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0x0A: PUSH(Bv);
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0x0B: POP(Bv);
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0x0C: decode OPCODE_OP_BOTTOM3 {
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0x0: decode MODE_SUBMODE {
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0x0: UD2();
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default: PUSHA();
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}
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0x1: decode MODE_SUBMODE {
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0x0: UD2();
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default: POPA();
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}
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0x2: decode MODE_SUBMODE {
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0x0: UD2();
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default: BOUND(Gv,Mv);
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}
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0x3: decode MODE_SUBMODE {
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//The second operand should really be of size "d", but it's
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//set to "v" in order to have a consistent register size.
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//This shouldn't affect behavior.
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0x0: MOVSXD(Gv,Ev);
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default: WarnUnimpl::arpl_Ew_Gw();
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}
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0x4: M5InternalError::error(
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{{"Tried to execute the FS segment override prefix!"}});
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0x5: M5InternalError::error(
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{{"Tried to execute the GS segment override prefix!"}});
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0x6: M5InternalError::error(
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{{"Tried to execute the operand size override prefix!"}});
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0x7: M5InternalError::error(
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{{"Tried to execute the DS address size override prefix!"}});
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}
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0x0D: decode OPCODE_OP_BOTTOM3 {
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0x0: PUSH(Iz);
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0x1: IMUL(Gv,Ev,Iz);
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0x2: PUSH(Ib);
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0x3: IMUL(Gv,Ev,Ib);
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0x4: StringInst::INS(Yb,rD);
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0x5: StringInst::INS(Yz,rD);
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0x6: StringInst::OUTS(rD,Xb);
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0x7: StringInst::OUTS(rD,Xz);
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}
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0x0E: decode OPCODE_OP_BOTTOM3 {
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0x0: JO(Jb);
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0x1: JNO(Jb);
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0x2: JB(Jb);
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0x3: JNB(Jb);
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0x4: JZ(Jb);
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0x5: JNZ(Jb);
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0x6: JBE(Jb);
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0x7: JNBE(Jb);
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}
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0x0F: decode OPCODE_OP_BOTTOM3 {
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0x0: JS(Jb);
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0x1: JNS(Jb);
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0x2: JP(Jb);
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0x3: JNP(Jb);
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0x4: JL(Jb);
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0x5: JNL(Jb);
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0x6: JLE(Jb);
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0x7: JNLE(Jb);
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}
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0x10: decode OPCODE_OP_BOTTOM3 {
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//0x0: group1_Eb_Ib();
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0x0: decode MODRM_REG {
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0x0: ADD(Eb,Ib);
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0x1: OR(Eb,Ib);
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0x2: ADC(Eb,Ib);
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0x3: SBB(Eb,Ib);
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0x4: AND(Eb,Ib);
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0x5: SUB(Eb,Ib);
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0x6: XOR(Eb,Ib);
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0x7: CMP(Eb,Ib);
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}
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//0x1: group1_Ev_Iz();
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0x1: decode MODRM_REG {
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0x0: ADD(Ev,Iz);
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0x1: OR(Ev,Iz);
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0x2: ADC(Ev,Iz);
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0x3: SBB(Ev,Iz);
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0x4: AND(Ev,Iz);
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0x5: SUB(Ev,Iz);
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0x6: XOR(Ev,Iz);
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0x7: CMP(Ev,Iz);
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}
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0x2: decode MODE_SUBMODE {
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0x0: UD2();
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//default: group1_Eb_Ib();
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default: decode MODRM_REG {
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0x0: ADD(Eb,Ib);
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0x1: OR(Eb,Ib);
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0x2: ADC(Eb,Ib);
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0x3: SBB(Eb,Ib);
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0x4: AND(Eb,Ib);
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0x5: SUB(Eb,Ib);
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0x6: XOR(Eb,Ib);
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0x7: CMP(Eb,Ib);
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}
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}
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//0x3: group1_Ev_Ib();
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0x3: decode MODRM_REG {
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0x0: ADD(Ev,Ib);
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0x1: OR(Ev,Ib);
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0x2: ADC(Ev,Ib);
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0x3: SBB(Ev,Ib);
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0x4: AND(Ev,Ib);
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0x5: SUB(Ev,Ib);
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0x6: XOR(Ev,Ib);
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0x7: CMP(Ev,Ib);
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}
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0x4: TEST(Eb,Gb);
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0x5: TEST(Ev,Gv);
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0x6: XCHG(Eb,Gb);
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0x7: XCHG(Ev,Gv);
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}
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0x11: decode OPCODE_OP_BOTTOM3 {
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0x0: MOV(Eb,Gb);
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0x1: MOV(Ev,Gv);
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0x2: MOV(Gb,Eb);
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0x3: MOV(Gv,Ev);
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0x4: decode MODRM_REG {
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0x0, 0x1, 0x2,
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0x3, 0x4, 0x5: MOV(Ev,Sv);
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}
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0x5: LEA(Gv,M);
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0x6: decode MODE_SUBMODE {
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0x3, 0x4: MOV_REAL(Sv,Ev);
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default: decode MODRM_REG {
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0x1: UD2(); // Moving to the CS selector is illegal.
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0x2: MOVSS(Sv,Ev);
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0x0, 0x3,
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0x4, 0x5: MOV(Sv,Ev);
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default: UD2();
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}
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}
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//0x7: group10_Ev();
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0x7: decode MODRM_REG {
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0x0: POP(Ev);
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default: UD2();
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}
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}
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0x12: decode OPCODE_OP_BOTTOM3 {
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0x0: NopInst::NOP(); //XXX repe makes this a "pause"
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default: XCHG(Bv,rAv);
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}
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0x13: decode OPCODE_OP_BOTTOM3 {
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0x0: CDQE(rAv);
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0x1: CQO(rAv,rDv);
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0x2: decode MODE_SUBMODE {
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0x0: UD2();
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default: WarnUnimpl::call_far_Ap();
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}
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0x3: WarnUnimpl::fwait(); //aka wait
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0x4: PUSHF();
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0x5: POPF();
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//The 64 bit versions of both of these should be illegal only
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//if CPUID says it isn't supported. For now, we'll just assume
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//that it's supported.
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0x6: SAHF();
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0x7: LAHF();
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}
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0x14: decode OPCODE_OP_BOTTOM3 {
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0x0: MOV(rAb, Ob);
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0x1: MOV(rAv, Ov);
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0x2: MOV(Ob, rAb);
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0x3: MOV(Ov, rAv);
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0x4: StringInst::MOVS(Yb,Xb);
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0x5: StringInst::MOVS(Yv,Xv);
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0x6: StringTestInst::CMPS(Yb,Xb);
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0x7: StringTestInst::CMPS(Yv,Xv);
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}
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0x15: decode OPCODE_OP_BOTTOM3 {
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0x0: TEST(rAb,Ib);
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0x1: TEST(rAv,Iz);
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0x2: StringInst::STOS(Yb);
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0x3: StringInst::STOS(Yv);
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0x4: StringInst::LODS(Xb);
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0x5: StringInst::LODS(Xv);
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0x6: StringTestInst::SCAS(Yb);
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0x7: StringTestInst::SCAS(Yv);
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}
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0x16: MOV(Bb,Ib);
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0x17: MOV(Bv,Iv);
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0x18: decode OPCODE_OP_BOTTOM3 {
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//0x0: group2_Eb_Ib();
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0x0: decode MODRM_REG {
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0x0: ROL(Eb,Ib);
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0x1: ROR(Eb,Ib);
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0x2: RCL(Eb,Ib);
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0x3: RCR(Eb,Ib);
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0x4: SAL(Eb,Ib);
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0x5: SHR(Eb,Ib);
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0x6: SAL(Eb,Ib);
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0x7: SAR(Eb,Ib);
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}
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//0x1: group2_Ev_Ib();
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0x1: decode MODRM_REG {
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0x0: ROL(Ev,Ib);
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0x1: ROR(Ev,Ib);
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0x2: RCL(Ev,Ib);
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0x3: RCR(Ev,Ib);
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0x4: SAL(Ev,Ib);
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0x5: SHR(Ev,Ib);
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0x6: SAL(Ev,Ib);
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0x7: SAR(Ev,Ib);
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}
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0x2: RET_NEAR(Iw);
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0x3: RET_NEAR();
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0x4: decode MODE_SUBMODE {
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0x0: UD2();
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default: WarnUnimpl::les_Gz_Mp();
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}
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0x5: decode MODE_SUBMODE {
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0x0: UD2();
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default: WarnUnimpl::lds_Gz_Mp();
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}
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//0x6: group12_Eb_Ib();
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0x6: decode MODRM_REG {
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0x0: MOV(Eb,Ib);
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default: UD2();
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}
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//0x7: group12_Ev_Iz();
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0x7: decode MODRM_REG {
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0x0: MOV(Ev,Iz);
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default: UD2();
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}
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}
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format WarnUnimpl {
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0x19: decode OPCODE_OP_BOTTOM3 {
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// The second parameter here should be of size b, but
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// immediate sizes are determined elsewhere and this would
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// confuse the instruction type specialization code.
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0x0: Inst::ENTER(Iw,Iw);
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0x1: Inst::LEAVE();
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0x2: ret_far_Iw();
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0x3: decode MODE_SUBMODE {
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0x3, 0x4: ret_far_real();
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default: Inst::RET_FAR();
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}
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0x4: Inst::INT3();
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0x5: decode FullSystemInt default inst_ib() {
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0: decode IMMEDIATE {
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// Really only the LSB matters, but the decoder
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// will sign extend it, and there's no easy way to
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// specify only checking the first byte.
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0xffffffffffffff80:
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SyscallInst::int80('xc->syscall(Rax, &fault)',
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IsSyscall, IsNonSpeculative,
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IsSerializeAfter);
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}
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default: Inst::INT(Ib);
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}
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0x6: decode MODE_SUBMODE {
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0x0: Inst::UD2();
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default: into();
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}
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0x7: decode MODE_SUBMODE {
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0x4: Inst::IRET_REAL();
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0x3: Inst::IRET_VIRT();
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default: Inst::IRET_PROT();
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}
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}
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}
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0x1A: decode OPCODE_OP_BOTTOM3 {
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|
//0x0: group2_Eb_1();
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|
0x0: decode MODRM_REG {
|
|
0x0: ROL_1(Eb);
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|
0x1: ROR_1(Eb);
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|
0x2: RCL_1(Eb);
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|
0x3: RCR_1(Eb);
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|
0x4: SAL_1(Eb);
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|
0x5: SHR_1(Eb);
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|
0x6: SAL_1(Eb);
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|
0x7: SAR_1(Eb);
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|
}
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|
//0x1: group2_Ev_1();
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|
0x1: decode MODRM_REG {
|
|
0x0: ROL_1(Ev);
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|
0x1: ROR_1(Ev);
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|
0x2: RCL_1(Ev);
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|
0x3: RCR_1(Ev);
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|
0x4: SAL_1(Ev);
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|
0x5: SHR_1(Ev);
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|
0x6: SAL_1(Ev);
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|
0x7: SAR_1(Ev);
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|
}
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|
//0x2: group2_Eb_Cl();
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|
0x2: decode MODRM_REG {
|
|
0x0: ROL(Eb,rCb);
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|
0x1: ROR(Eb,rCb);
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|
0x2: RCL(Eb,rCb);
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|
0x3: RCR(Eb,rCb);
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|
0x4: SAL(Eb,rCb);
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|
0x5: SHR(Eb,rCb);
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|
0x6: SAL(Eb,rCb);
|
|
0x7: SAR(Eb,rCb);
|
|
}
|
|
//The second operand should have size "b", but to have
|
|
//consistent register sizes it's "v". This shouldn't have
|
|
//any affect on functionality.
|
|
//0x3: group2_Ev_Cl();
|
|
0x3: decode MODRM_REG {
|
|
0x0: ROL(Ev,rCv);
|
|
0x1: ROR(Ev,rCv);
|
|
0x2: RCL(Ev,rCv);
|
|
0x3: RCR(Ev,rCv);
|
|
0x4: SAL(Ev,rCv);
|
|
0x5: SHR(Ev,rCv);
|
|
0x6: SAL(Ev,rCv);
|
|
0x7: SAR(Ev,rCv);
|
|
}
|
|
0x4: decode MODE_SUBMODE {
|
|
0x0: UD2();
|
|
default: WarnUnimpl::aam_Ib();
|
|
}
|
|
0x5: decode MODE_SUBMODE {
|
|
0x0: UD2();
|
|
default: WarnUnimpl::aad_Ib();
|
|
}
|
|
0x6: decode MODE_SUBMODE {
|
|
0x0: UD2();
|
|
default: SALC(rAb);
|
|
}
|
|
0x7: XLAT();
|
|
}
|
|
##include "x87.isa"
|
|
0x1C: decode OPCODE_OP_BOTTOM3 {
|
|
0x0: LOOPNE(Jb);
|
|
0x1: LOOPE(Jb);
|
|
0x2: LOOP(Jb);
|
|
0x3: JRCX(Jb);
|
|
0x4: IN(rAb,Ib);
|
|
0x5: IN(rAv,Iv);
|
|
0x6: OUT(Ib,rAb);
|
|
0x7: OUT(Iv,rAv);
|
|
}
|
|
0x1D: decode OPCODE_OP_BOTTOM3 {
|
|
0x0: CALL_NEAR(Jz);
|
|
0x1: JMP(Jz);
|
|
0x2: decode MODE_SUBMODE {
|
|
0x0: UD2();
|
|
0x1: JMP_FAR(Iz);
|
|
0x2: JMP_FAR(Iz);
|
|
0x3: JMP_FAR_REAL(Iz);
|
|
0x4: JMP_FAR_REAL(Iz);
|
|
}
|
|
0x3: JMP(Jb);
|
|
0x4: IN(rAb,rD);
|
|
0x5: IN(rAv,rD);
|
|
0x6: OUT(rD,rAb);
|
|
0x7: OUT(rD,rAv);
|
|
}
|
|
0x1E: decode OPCODE_OP_BOTTOM3 {
|
|
0x0: M5InternalError::error(
|
|
{{"Tried to execute the lock prefix!"}});
|
|
0x1: WarnUnimpl::int1();
|
|
0x2: M5InternalError::error(
|
|
{{"Tried to execute the repne prefix!"}});
|
|
0x3: M5InternalError::error(
|
|
{{"Tried to execute the rep/repe prefix!"}});
|
|
0x4: HLT();
|
|
0x5: CMC();
|
|
//0x6: group3_Eb();
|
|
0x6: decode MODRM_REG {
|
|
0x0: TEST(Eb,Iz);
|
|
0x1: TEST(Eb,Iz);
|
|
0x2: NOT(Eb);
|
|
0x3: NEG(Eb);
|
|
0x4: MUL_B(Eb);
|
|
0x5: IMUL_B(Eb);
|
|
//This should be Eb, but it access the entire word value ax.
|
|
0x6: DIV_B(Ew);
|
|
0x7: IDIV_B(Eb);
|
|
}
|
|
//0x7: group3_Ev();
|
|
0x7: decode MODRM_REG {
|
|
0x0: TEST(Ev,Iz);
|
|
0x1: TEST(Ev,Iz);
|
|
0x2: NOT(Ev);
|
|
0x3: NEG(Ev);
|
|
0x4: MUL(Ev);
|
|
0x5: IMUL(Ev);
|
|
0x6: DIV(Ev);
|
|
0x7: IDIV(Ev);
|
|
}
|
|
}
|
|
0x1F: decode OPCODE_OP_BOTTOM3 {
|
|
0x0: CLC();
|
|
0x1: STC();
|
|
0x2: CLI();
|
|
0x3: STI();
|
|
0x4: CLD();
|
|
0x5: STD();
|
|
//0x6: group4();
|
|
0x6: decode MODRM_REG {
|
|
0x0: INC(Eb);
|
|
0x1: DEC(Eb);
|
|
default: UD2();
|
|
}
|
|
//0x7: group5();
|
|
0x7: decode MODRM_REG {
|
|
0x0: INC(Ev);
|
|
0x1: DEC(Ev);
|
|
0x2: CALL_NEAR(Ev);
|
|
0x3: WarnUnimpl::call_far_Mp();
|
|
0x4: JMP(Ev);
|
|
0x5: decode MODE_SUBMODE {
|
|
0x0: JMP_FAR(Mz);
|
|
0x1: JMP_FAR(Mz);
|
|
0x2: JMP_FAR(Mz);
|
|
0x3: JMP_FAR_REAL(Mz);
|
|
0x4: JMP_FAR_REAL(Mz);
|
|
}
|
|
0x6: PUSH(Ev);
|
|
0x7: UD2();
|
|
}
|
|
}
|
|
}
|
|
default: FailUnimpl::oneByteOps();
|
|
}
|