2c1286865f
The changeset does a major refactor on the exit, exit_group, and futex system calls regarding exit functionality. A FutexMap class and related structures are added into a new file. This increases code clarity by encapsulating the futex operations and the futex state into an object. Several exit conditions were added to allow the simulator to end processes under certain conditions. Also, the simulation only exits now when all processes have finished executing. Change-Id: I1ee244caa9b5586fe7375e5b9b50fd3959b9655e Reviewed-on: https://gem5-review.googlesource.com/2269 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
183 lines
6 KiB
C++
183 lines
6 KiB
C++
/*
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* Copyright (c) 2013 ARM Limited
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* Copyright (c) 2014-2015 Sven Karlsson
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2016 RISC-V Foundation
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* Copyright (c) 2016 The University of Virginia
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andreas Hansson
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* Sven Karlsson
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* Alec Roelke
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*/
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#ifndef __ARCH_RISCV_REGISTERS_HH__
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#define __ARCH_RISCV_REGISTERS_HH__
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#include <map>
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#include <string>
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#include "arch/isa_traits.hh"
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#include "arch/riscv/generated/max_inst_regs.hh"
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#include "base/types.hh"
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namespace RiscvISA {
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using RiscvISAInst::MaxInstSrcRegs;
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using RiscvISAInst::MaxInstDestRegs;
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const int MaxMiscDestRegs = 1;
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typedef uint_fast16_t RegIndex;
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typedef uint64_t IntReg;
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typedef uint64_t FloatRegBits;
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typedef double FloatReg;
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typedef uint8_t CCReg; // Not applicable to Riscv
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typedef uint64_t MiscReg;
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const int NumIntArchRegs = 32;
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const int NumMicroIntRegs = 1;
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const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs;
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const int NumFloatRegs = 32;
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const int NumCCRegs = 0;
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const int NumMiscRegs = 4096;
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// These help enumerate all the registers for dependence tracking.
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const int FP_Reg_Base = NumIntRegs;
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const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs;
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const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs;
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const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
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// Semantically meaningful register indices
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const int ZeroReg = 0;
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const int ReturnAddrReg = 1;
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const int StackPointerReg = 2;
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const int GlobalPointerReg = 3;
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const int ThreadPointerReg = 4;
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const int FramePointerReg = 8;
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const int ReturnValueRegs[] = {10, 11};
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const int ReturnValueReg = ReturnValueRegs[0];
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const int ArgumentRegs[] = {10, 11, 12, 13, 14, 15, 16, 17};
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const int AMOTempReg = 32;
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const char* const RegisterNames[] = {"zero", "ra", "sp", "gp",
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"tp", "t0", "t1", "t2",
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"s0", "s1", "a0", "a1",
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"a2", "a3", "a4", "a5",
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"a6", "a7", "s2", "s3",
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"s4", "s5", "s6", "s7",
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"s8", "s9", "s10", "s11",
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"t3", "t4", "t5", "t6"};
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const int SyscallNumReg = ArgumentRegs[7];
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const int SyscallArgumentRegs[] = {ArgumentRegs[0], ArgumentRegs[1],
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ArgumentRegs[2], ArgumentRegs[3]};
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const int SyscallPseudoReturnReg = ReturnValueRegs[0];
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enum MiscRegIndex {
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MISCREG_FFLAGS = 0x001,
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MISCREG_FRM = 0x002,
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MISCREG_FCSR = 0x003,
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MISCREG_CYCLE = 0xC00,
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MISCREG_TIME = 0xC01,
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MISCREG_INSTRET = 0xC02,
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MISCREG_CYCLEH = 0xC80,
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MISCREG_TIMEH = 0xC81,
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MISCREG_INSTRETH = 0xC82,
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MISCREG_SSTATUS = 0x100,
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MISCREG_STVEC = 0x101,
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MISCREG_SIE = 0x104,
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MISCREG_STIMECMP = 0x121,
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MISCREG_STIME = 0xD01,
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MISCREG_STIMEH = 0xD81,
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MISCREG_SSCRATCH = 0x140,
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MISCREG_SEPC = 0x141,
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MISCREG_SCAUSE = 0xD42,
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MISCREG_SBADADDR = 0xD43,
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MISCREG_SIP = 0x144,
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MISCREG_SPTBR = 0x180,
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MISCREG_SASID = 0x181,
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MISCREG_CYCLEW = 0x900,
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MISCREG_TIMEW = 0x901,
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MISCREG_INSTRETW = 0x902,
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MISCREG_CYCLEHW = 0x980,
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MISCREG_TIMEHW = 0x981,
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MISCREG_INSTRETHW = 0x982,
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MISCREG_HSTATUS = 0x200,
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MISCREG_HTVEC = 0x201,
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MISCREG_HTDELEG = 0x202,
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MISCREG_HTIMECMP = 0x221,
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MISCREG_HTIME = 0xE01,
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MISCREG_HTIMEH = 0xE81,
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MISCREG_HSCRATCH = 0x240,
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MISCREG_HEPC = 0x241,
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MISCREG_HCAUSE = 0x242,
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MISCREG_HBADADDR = 0x243,
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MISCREG_STIMEW = 0xA01,
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MISCREG_STIMEHW = 0xA81,
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MISCREG_MCPUID = 0xF00,
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MISCREG_MIMPID = 0xF01,
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MISCREG_MHARTID = 0xF10,
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MISCREG_MSTATUS = 0x300,
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MISCREG_MTVEC = 0x301,
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MISCREG_MTDELEG = 0x302,
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MISCREG_MIE = 0x304,
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MISCREG_MTIMECMP = 0x321,
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MISCREG_MTIME = 0x701,
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MISCREG_MTIMEH = 0x741,
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MISCREG_MSCRATCH = 0x340,
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MISCREG_MEPC = 0x341,
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MISCREG_MCAUSE = 0x342,
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MISCREG_MBADADDR = 0x343,
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MISCREG_MIP = 0x344,
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MISCREG_MBASE = 0x380,
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MISCREG_MBOUND = 0x381,
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MISCREG_MIBASE = 0x382,
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MISCREG_MIBOUND = 0x383,
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MISCREG_MDBASE = 0x384,
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MISCREG_MDBOUND = 0x385,
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MISCREG_HTIMEW = 0xB01,
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MISCREG_HTIMEHW = 0xB81,
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MISCREG_MTOHOST = 0x780,
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MISCREG_MFROMHOST = 0x781
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};
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}
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#endif // __ARCH_RISCV_REGISTERS_HH__
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