66a1016a35
The kernel and gem5 derive MPIDR values from CPU IDs in slightly different ways. This means that guests running in a multi-CPU setup sometimes fail to bring up secondary CPUs. Fix this by overriding the MPIDR value in virtual CPUs just after they have been instantiated. Change-Id: I916d44978a9c855ab89c80a083af45b0cea6edac Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2461 Reviewed-by: Weiping Liao <weipingliao@google.com>
145 lines
5.5 KiB
C++
145 lines
5.5 KiB
C++
/*
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* Copyright (c) 2015, 2017 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andreas Sandberg
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*/
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#ifndef __ARCH_ARM_KVM_ARMV8_CPU_HH__
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#define __ARCH_ARM_KVM_ARMV8_CPU_HH__
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#include <vector>
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#include "arch/arm/intregs.hh"
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#include "arch/arm/kvm/base_cpu.hh"
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#include "arch/arm/miscregs.hh"
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struct ArmV8KvmCPUParams;
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/**
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* This is an implementation of a KVM-based ARMv8-compatible CPU.
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*
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* Known limitations:
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* <ul>
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*
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* <li>The system-register-based generic timer can only be simulated
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* by the host kernel. Workaround: Use a memory mapped timer
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* instead to simulate the timer in gem5.
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*
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* <li>Simulating devices (e.g., the generic timer) in the host
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* kernel requires that the host kernel also simulates the
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* GIC.
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*
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* <li>ID registers in the host and in gem5 must match for switching
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* between simulated CPUs and KVM. This is particularly
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* important for ID registers describing memory system
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* capabilities (e.g., ASID size, physical address size).
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*
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* <li>Switching between a virtualized CPU and a simulated CPU is
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* currently not supported if in-kernel device emulation is
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* used. This could be worked around by adding support for
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* switching to the gem5 (e.g., the KvmGic) side of the device
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* models. A simpler workaround is to avoid in-kernel device
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* models altogether.
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*
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* </ul>
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*
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*/
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class ArmV8KvmCPU : public BaseArmKvmCPU
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{
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public:
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ArmV8KvmCPU(ArmV8KvmCPUParams *params);
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virtual ~ArmV8KvmCPU();
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void startup() override;
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void dump() const override;
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protected:
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void updateKvmState() override;
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void updateThreadContext() override;
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protected:
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/** Mapping between integer registers in gem5 and KVM */
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struct IntRegInfo {
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IntRegInfo(uint64_t _kvm, IntRegIndex _idx, const char *_name)
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: kvm(_kvm), idx(_idx), name(_name) {}
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/** Register index in KVM */
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uint64_t kvm;
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/** Register index in gem5 */
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IntRegIndex idx;
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/** Name to use in debug dumps */
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const char *name;
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};
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/** Mapping between misc registers in gem5 and registers in KVM */
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struct MiscRegInfo {
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MiscRegInfo(uint64_t _kvm, MiscRegIndex _idx, const char *_name)
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: kvm(_kvm), idx(_idx), name(_name) {}
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/** Register index in KVM */
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uint64_t kvm;
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/** Register index in gem5 */
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MiscRegIndex idx;
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/** Name to use in debug dumps */
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const char *name;
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};
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/**
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* Get a map between system registers in kvm and gem5 registers
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*
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* This method returns a mapping between system registers in kvm
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* and misc regs in gem5. The actual mapping is only created the
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* first time the method is called and stored in a cache
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* (ArmV8KvmCPU::sysRegMap).
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*
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* @return Vector of kvm<->misc reg mappings.
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*/
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const std::vector<ArmV8KvmCPU::MiscRegInfo> &getSysRegMap() const;
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/** Mapping between gem5 integer registers and integer registers in kvm */
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static const std::vector<ArmV8KvmCPU::IntRegInfo> intRegMap;
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/** Mapping between gem5 misc registers registers and registers in kvm */
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static const std::vector<ArmV8KvmCPU::MiscRegInfo> miscRegMap;
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/** Mapping between gem5 ID misc registers registers and registers in kvm */
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static const std::vector<ArmV8KvmCPU::MiscRegInfo> miscRegIdMap;
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/** Cached mapping between system registers in kvm and misc regs in gem5 */
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mutable std::vector<ArmV8KvmCPU::MiscRegInfo> sysRegMap;
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};
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#endif // __ARCH_ARM_KVM_ARMV8_CPU_HH__
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