1b6355c895
For historical reasons, the ExecContext interface had a single function, readMem(), that did two different things depending on whether the ExecContext supported atomic memory mode (i.e., AtomicSimpleCPU) or timing memory mode (all the other models). In the former case, it actually performed a memory read; in the latter case, it merely initiated a read access, and the read completion did not happen until later when a response packet arrived from the memory system. This led to some confusing things, including timing accesses being required to provide a pointer for the return data even though that pointer was only used in atomic mode. This patch splits this interface, adding a new initiateMemRead() function to the ExecContext interface to replace the timing-mode use of readMem(). For consistency and clarity, the readMemTiming() helper function in the ISA definitions is renamed to initiateMemRead() as well. For x86, where the access size is passed in explicitly, we can also get rid of the data parameter at this level. For other ISAs, where the access size is determined from the type of the data parameter, we have to keep the parameter for that purpose.
561 lines
15 KiB
C++
561 lines
15 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2003-2005 The Regents of The University of Michigan
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Steve Reinhardt
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// Kevin Lim
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////////////////////////////////////////////////////////////////////
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//
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// Memory-format instructions: LoadAddress, Load, Store
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//
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output header {{
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/**
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* Base class for general Alpha memory-format instructions.
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*/
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class Memory : public AlphaStaticInst
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{
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protected:
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/// Memory request flags. See mem_req_base.hh.
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Request::Flags memAccessFlags;
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/// Constructor
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Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
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: AlphaStaticInst(mnem, _machInst, __opClass)
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{
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}
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Base class for memory-format instructions using a 32-bit
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* displacement (i.e. most of them).
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*/
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class MemoryDisp32 : public Memory
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{
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protected:
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/// Displacement for EA calculation (signed).
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int32_t disp;
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/// Constructor.
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MemoryDisp32(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
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: Memory(mnem, _machInst, __opClass),
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disp(MEMDISP)
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{
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}
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};
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/**
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* Base class for a few miscellaneous memory-format insts
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* that don't interpret the disp field: wh64, fetch, fetch_m, ecb.
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* None of these instructions has a destination register either.
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*/
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class MemoryNoDisp : public Memory
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{
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protected:
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/// Constructor
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MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
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: Memory(mnem, _machInst, __opClass)
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{
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}
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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output decoder {{
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std::string
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Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
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flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB);
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}
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std::string
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MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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return csprintf("%-10s (r%d)", mnemonic, RB);
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}
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}};
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def format LoadAddress(code) {{
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iop = InstObjParams(name, Name, 'MemoryDisp32', code)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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def template LoadStoreDeclare {{
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/**
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* Static instruction class for "%(mnemonic)s".
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*/
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class %(class_name)s : public %(base_class)s
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{
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public:
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/// Constructor.
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%(class_name)s(ExtMachInst machInst);
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%(BasicExecDeclare)s
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%(EACompDeclare)s
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%(InitiateAccDeclare)s
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%(CompleteAccDeclare)s
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};
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}};
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def template EACompDeclare {{
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Fault eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const;
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}};
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def template InitiateAccDeclare {{
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Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
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}};
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def template CompleteAccDeclare {{
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Fault completeAcc(PacketPtr, %(CPU_exec_context)s *,
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Trace::InstRecord *) const;
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}};
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def template LoadStoreConstructor {{
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%(class_name)s::%(class_name)s(ExtMachInst machInst)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
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{
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%(constructor)s;
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}
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}};
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def template EACompExecute {{
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Fault %(class_name)s::eaComp(CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (fault == NoFault) {
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%(op_wb)s;
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xc->setEA(EA);
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}
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return fault;
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}
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}};
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def template LoadExecute {{
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Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (fault == NoFault) {
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fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template LoadInitiateAcc {{
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Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(fp_enable_check)s;
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%(op_src_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (fault == NoFault) {
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fault = initiateMemRead(xc, traceData, EA, Mem, memAccessFlags);
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}
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return fault;
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}
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}};
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def template LoadCompleteAcc {{
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Fault %(class_name)s::completeAcc(PacketPtr pkt,
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CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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%(fp_enable_check)s;
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%(op_decl)s;
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getMem(pkt, Mem, traceData);
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template StoreExecute {{
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Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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fault = writeMemAtomic(xc, traceData, Mem, EA,
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memAccessFlags, NULL);
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}
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if (fault == NoFault) {
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%(postacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template StoreCondExecute {{
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Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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uint64_t write_result = 0;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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fault = writeMemAtomic(xc, traceData, Mem, EA,
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memAccessFlags, &write_result);
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}
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if (fault == NoFault) {
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%(postacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template StoreInitiateAcc {{
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Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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fault = writeMemTiming(xc, traceData, Mem, EA,
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memAccessFlags, NULL);
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}
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return fault;
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}
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}};
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def template StoreCompleteAcc {{
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Fault %(class_name)s::completeAcc(PacketPtr pkt,
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CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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return NoFault;
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}
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}};
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def template StoreCondCompleteAcc {{
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Fault %(class_name)s::completeAcc(PacketPtr pkt,
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CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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%(fp_enable_check)s;
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%(op_dest_decl)s;
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uint64_t write_result = pkt->req->getExtraData();
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if (fault == NoFault) {
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%(postacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template MiscExecute {{
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Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA M5_VAR_USED;
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Fault fault = NoFault;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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warn_once("Prefetch instructions in Alpha do not do anything\n");
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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return NoFault;
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}
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}};
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// Prefetches in Alpha don't actually do anything
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// They just build an effective address and complete
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def template MiscInitiateAcc {{
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Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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warn("initiateAcc undefined: Misc instruction does not support split "
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"access method!");
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return NoFault;
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}
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}};
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def template MiscCompleteAcc {{
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Fault %(class_name)s::completeAcc(PacketPtr pkt,
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CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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warn("completeAcc undefined: Misc instruction does not support split "
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"access method!");
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return NoFault;
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}
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}};
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// load instructions use Ra as dest, so check for
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// Ra == 31 to detect nops
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def template LoadNopCheckDecode {{
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{
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AlphaStaticInst *i = new %(class_name)s(machInst);
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if (RA == 31) {
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i = makeNop(i);
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}
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return i;
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}
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}};
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// for some load instructions, Ra == 31 indicates a prefetch (not a nop)
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def template LoadPrefetchCheckDecode {{
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{
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if (RA != 31) {
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return new %(class_name)s(machInst);
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}
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else {
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return new %(class_name)sPrefetch(machInst);
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}
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}
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}};
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let {{
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def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
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postacc_code = '', base_class = 'MemoryDisp32',
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decode_template = BasicDecode, exec_template_base = ''):
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# Make sure flags are in lists (convert to lists if not).
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mem_flags = makeList(mem_flags)
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inst_flags = makeList(inst_flags)
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iop = InstObjParams(name, Name, base_class,
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{ 'ea_code':ea_code, 'memacc_code':memacc_code, 'postacc_code':postacc_code },
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inst_flags)
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if mem_flags:
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mem_flags = [ 'Request::%s' % flag for flag in mem_flags ]
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s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
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iop.constructor += s
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# select templates
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# The InitiateAcc template is the same for StoreCond templates as the
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# corresponding Store template..
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StoreCondInitiateAcc = StoreInitiateAcc
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fullExecTemplate = eval(exec_template_base + 'Execute')
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initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
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completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
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# (header_output, decoder_output, decode_block, exec_output)
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return (LoadStoreDeclare.subst(iop),
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LoadStoreConstructor.subst(iop),
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decode_template.subst(iop),
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fullExecTemplate.subst(iop)
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+ EACompExecute.subst(iop)
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+ initiateAccTemplate.subst(iop)
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+ completeAccTemplate.subst(iop))
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}};
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def format LoadOrNop(memacc_code, ea_code = {{ EA = Rb + disp; }},
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mem_flags = [], inst_flags = []) {{
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(header_output, decoder_output, decode_block, exec_output) = \
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LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
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decode_template = LoadNopCheckDecode,
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exec_template_base = 'Load')
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}};
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// Note that the flags passed in apply only to the prefetch version
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def format LoadOrPrefetch(memacc_code, ea_code = {{ EA = Rb + disp; }},
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mem_flags = [], pf_flags = [], inst_flags = []) {{
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# declare the load instruction object and generate the decode block
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(header_output, decoder_output, decode_block, exec_output) = \
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LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
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decode_template = LoadPrefetchCheckDecode,
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exec_template_base = 'Load')
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# Declare the prefetch instruction object.
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# Make sure flag args are lists so we can mess with them.
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mem_flags = makeList(mem_flags)
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pf_flags = makeList(pf_flags)
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inst_flags = makeList(inst_flags)
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pf_mem_flags = mem_flags + pf_flags + ['PREFETCH']
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pf_inst_flags = inst_flags
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(pf_header_output, pf_decoder_output, _, pf_exec_output) = \
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LoadStoreBase(name, Name + 'Prefetch', ea_code, ';',
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pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc')
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header_output += pf_header_output
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decoder_output += pf_decoder_output
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exec_output += pf_exec_output
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}};
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def format Store(memacc_code, ea_code = {{ EA = Rb + disp; }},
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mem_flags = [], inst_flags = []) {{
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(header_output, decoder_output, decode_block, exec_output) = \
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LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
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exec_template_base = 'Store')
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}};
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def format StoreCond(memacc_code, postacc_code,
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ea_code = {{ EA = Rb + disp; }},
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mem_flags = [], inst_flags = []) {{
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(header_output, decoder_output, decode_block, exec_output) = \
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LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
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postacc_code, exec_template_base = 'StoreCond')
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}};
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// Use 'MemoryNoDisp' as base: for wh64, fetch, ecb
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def format MiscPrefetch(ea_code, memacc_code,
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mem_flags = [], inst_flags = []) {{
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(header_output, decoder_output, decode_block, exec_output) = \
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LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
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base_class = 'MemoryNoDisp', exec_template_base = 'Misc')
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}};
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