ce2722cdd9
If the cache access mode is parallel, i.e. "sequential_access" parameter is set to "False", tags and data are accessed in parallel. Therefore, the hit_latency is the maximum latency between tag_latency and data_latency. On the other hand, if the cache access mode is sequential, i.e. "sequential_access" parameter is set to "True", tags and data are accessed sequentially. Therefore, the hit_latency is the sum of tag_latency plus data_latency. Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
130 lines
4.2 KiB
Python
130 lines
4.2 KiB
Python
# -*- coding: utf-8 -*-
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# Copyright (c) 2015 Jason Power
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Jason Power
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""" Caches with options for a simple gem5 configuration script
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This file contains L1 I/D and L2 caches to be used in the simple
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gem5 configuration script. It uses the SimpleOpts wrapper to set up command
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line options from each individual class.
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"""
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from m5.objects import Cache
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from common import SimpleOpts
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# Some specific options for caches
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# For all options see src/mem/cache/BaseCache.py
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class L1Cache(Cache):
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"""Simple L1 Cache with default values"""
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assoc = 2
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tag_latency = 2
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data_latency = 2
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response_latency = 2
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mshrs = 4
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tgts_per_mshr = 20
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def __init__(self, options=None):
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super(L1Cache, self).__init__()
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pass
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def connectBus(self, bus):
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"""Connect this cache to a memory-side bus"""
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self.mem_side = bus.slave
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def connectCPU(self, cpu):
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"""Connect this cache's port to a CPU-side port
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This must be defined in a subclass"""
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raise NotImplementedError
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class L1ICache(L1Cache):
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"""Simple L1 instruction cache with default values"""
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# Set the default size
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size = '16kB'
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SimpleOpts.add_option('--l1i_size',
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help="L1 instruction cache size. Default: %s" % size)
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def __init__(self, opts=None):
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super(L1ICache, self).__init__(opts)
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if not opts or not opts.l1i_size:
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return
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self.size = opts.l1i_size
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def connectCPU(self, cpu):
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"""Connect this cache's port to a CPU icache port"""
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self.cpu_side = cpu.icache_port
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class L1DCache(L1Cache):
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"""Simple L1 data cache with default values"""
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# Set the default size
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size = '64kB'
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SimpleOpts.add_option('--l1d_size',
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help="L1 data cache size. Default: %s" % size)
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def __init__(self, opts=None):
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super(L1DCache, self).__init__(opts)
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if not opts or not opts.l1d_size:
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return
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self.size = opts.l1d_size
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def connectCPU(self, cpu):
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"""Connect this cache's port to a CPU dcache port"""
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self.cpu_side = cpu.dcache_port
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class L2Cache(Cache):
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"""Simple L2 Cache with default values"""
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# Default parameters
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size = '256kB'
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assoc = 8
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tag_latency = 20
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data_latency = 20
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response_latency = 20
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mshrs = 20
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tgts_per_mshr = 12
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SimpleOpts.add_option('--l2_size', help="L2 cache size. Default: %s" % size)
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def __init__(self, opts=None):
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super(L2Cache, self).__init__()
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if not opts or not opts.l2_size:
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return
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self.size = opts.l2_size
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def connectCPUSideBus(self, bus):
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self.cpu_side = bus.master
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def connectMemSideBus(self, bus):
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self.mem_side = bus.slave
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