ef6e2eb3c4
cpu/o3/alpha_cpu.hh:
Update for sampler to work properly. Also code cleanup.
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_dyn_inst.hh:
Updates to support the checker.
cpu/o3/alpha_cpu_impl.hh:
Updates to support the checker. Also general code cleanup.
cpu/o3/alpha_dyn_inst_impl.hh:
Code cleanup.
cpu/o3/alpha_params.hh:
Updates to support the checker. Also supports trap latencies set through the parameters.
cpu/o3/commit.hh:
Supports sampler, checker. Code cleanup.
cpu/o3/commit_impl.hh:
Updates to support the sampler and checker, as well as general code cleanup.
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
Support sampler and checker.
cpu/o3/decode_impl.hh:
Supports sampler.
cpu/o3/fetch.hh:
Supports sampler. Also update to hold the youngest valid SN fetch has seen to ensure that the entire pipeline has been drained.
cpu/o3/fetch_impl.hh:
Sampler updates. Also be sure to not fetches to uncached space (bad path).
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
Sampler updates.
cpu/o3/lsq_unit_impl.hh:
Supports checker.
cpu/o3/regfile.hh:
No need for accessing xcProxies directly.
cpu/o3/rename.hh:
cpu/o3/rename_impl.hh:
Sampler support.
--HG--
extra : convert_revision : 03881885dd50ebbca13ef31f31492fd4ef59121c
430 lines
13 KiB
C++
430 lines
13 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_O3_ALPHA_FULL_CPU_HH__
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#define __CPU_O3_ALPHA_FULL_CPU_HH__
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#include "arch/isa_traits.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/o3/cpu.hh"
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#include "sim/byteswap.hh"
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class EndQuiesceEvent;
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template <class Impl>
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class AlphaFullCPU : public FullO3CPU<Impl>
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{
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protected:
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typedef TheISA::IntReg IntReg;
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typedef TheISA::MiscReg MiscReg;
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typedef TheISA::RegFile RegFile;
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typedef TheISA::MiscRegFile MiscRegFile;
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public:
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typedef O3ThreadState<Impl> ImplState;
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typedef O3ThreadState<Impl> Thread;
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typedef typename Impl::Params Params;
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/** Constructs an AlphaFullCPU with the given parameters. */
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AlphaFullCPU(Params *params);
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class AlphaXC : public ExecContext
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{
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public:
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AlphaFullCPU<Impl> *cpu;
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O3ThreadState<Impl> *thread;
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Tick lastActivate;
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Tick lastSuspend;
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EndQuiesceEvent *quiesceEvent;
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virtual BaseCPU *getCpuPtr() { return cpu; }
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virtual void setCpuId(int id) { cpu->cpu_id = id; }
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virtual int readCpuId() { return cpu->cpu_id; }
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virtual FunctionalMemory *getMemPtr() { return thread->mem; }
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#if FULL_SYSTEM
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virtual System *getSystemPtr() { return cpu->system; }
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virtual PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
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virtual AlphaITB *getITBPtr() { return cpu->itb; }
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virtual AlphaDTB * getDTBPtr() { return cpu->dtb; }
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#else
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virtual Process *getProcessPtr() { return thread->process; }
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#endif
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virtual Status status() const { return thread->status(); }
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virtual void setStatus(Status new_status) { thread->setStatus(new_status); }
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/// Set the status to Active. Optional delay indicates number of
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/// cycles to wait before beginning execution.
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virtual void activate(int delay = 1);
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/// Set the status to Suspended.
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virtual void suspend();
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/// Set the status to Unallocated.
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virtual void deallocate();
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/// Set the status to Halted.
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virtual void halt();
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#if FULL_SYSTEM
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virtual void dumpFuncProfile();
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#endif
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virtual void takeOverFrom(ExecContext *old_context);
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virtual void regStats(const std::string &name);
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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#if FULL_SYSTEM
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virtual EndQuiesceEvent *getQuiesceEvent();
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virtual Tick readLastActivate();
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virtual Tick readLastSuspend();
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virtual void profileClear();
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virtual void profileSample();
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#endif
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virtual int getThreadNum() { return thread->tid; }
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virtual TheISA::MachInst getInst();
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virtual void copyArchRegs(ExecContext *xc);
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virtual void clearArchRegs();
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virtual uint64_t readIntReg(int reg_idx);
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virtual float readFloatRegSingle(int reg_idx);
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virtual double readFloatRegDouble(int reg_idx);
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virtual uint64_t readFloatRegInt(int reg_idx);
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virtual void setIntReg(int reg_idx, uint64_t val);
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virtual void setFloatRegSingle(int reg_idx, float val);
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virtual void setFloatRegDouble(int reg_idx, double val);
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virtual void setFloatRegInt(int reg_idx, uint64_t val);
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virtual uint64_t readPC()
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{ return cpu->readPC(thread->tid); }
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virtual void setPC(uint64_t val);
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virtual uint64_t readNextPC()
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{ return cpu->readNextPC(thread->tid); }
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virtual void setNextPC(uint64_t val);
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virtual MiscReg readMiscReg(int misc_reg)
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{ return cpu->readMiscReg(misc_reg, thread->tid); }
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virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
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{ return cpu->readMiscRegWithEffect(misc_reg, fault, thread->tid); }
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virtual Fault setMiscReg(int misc_reg, const MiscReg &val);
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virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
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// @todo: Figure out where these store cond failures should go.
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virtual unsigned readStCondFailures() { return thread->storeCondFailures; }
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virtual void setStCondFailures(unsigned sc_failures) { thread->storeCondFailures = sc_failures; }
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#if FULL_SYSTEM
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virtual bool inPalMode() { return TheISA::PcPAL(cpu->readPC(thread->tid)); }
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#endif
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// Only really makes sense for old CPU model. Lots of code
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// outside the CPU still checks this function, so it will
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// always return false to keep everything working.
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virtual bool misspeculating() { return false; }
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#if !FULL_SYSTEM
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virtual IntReg getSyscallArg(int i);
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virtual void setSyscallArg(int i, IntReg val);
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virtual void setSyscallReturn(SyscallReturn return_value);
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virtual void syscall() { return cpu->syscall(thread->tid); }
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virtual Counter readFuncExeInst() { return thread->funcExeInst; }
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#endif
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};
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// friend class AlphaXC;
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// std::vector<ExecContext *> xcProxies;
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#if FULL_SYSTEM
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/** ITB pointer. */
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AlphaITB *itb;
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/** DTB pointer. */
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AlphaDTB *dtb;
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#endif
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/** Registers statistics. */
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void regStats();
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#if FULL_SYSTEM
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/** Translates instruction requestion. */
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Fault translateInstReq(MemReqPtr &req)
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{
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return itb->translate(req);
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}
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/** Translates data read request. */
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Fault translateDataReadReq(MemReqPtr &req)
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{
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return dtb->translate(req, false);
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}
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/** Translates data write request. */
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Fault translateDataWriteReq(MemReqPtr &req)
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{
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return dtb->translate(req, true);
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}
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#else
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Fault dummyTranslation(MemReqPtr &req)
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{
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#if 0
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assert((req->vaddr >> 48 & 0xffff) == 0);
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#endif
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// put the asid in the upper 16 bits of the paddr
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req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
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req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
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return NoFault;
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}
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/** Translates instruction requestion in syscall emulation mode. */
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Fault translateInstReq(MemReqPtr &req)
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{
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return dummyTranslation(req);
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}
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/** Translates data read request in syscall emulation mode. */
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Fault translateDataReadReq(MemReqPtr &req)
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{
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return dummyTranslation(req);
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}
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/** Translates data write request in syscall emulation mode. */
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Fault translateDataWriteReq(MemReqPtr &req)
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{
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return dummyTranslation(req);
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}
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#endif
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MiscReg readMiscReg(int misc_reg, unsigned tid);
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MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault, unsigned tid);
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Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned tid);
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Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid);
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void squashFromXC(unsigned tid);
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#if FULL_SYSTEM
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void post_interrupt(int int_num, int index);
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int readIntrFlag();
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/** Sets the interrupt flags. */
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void setIntrFlag(int val);
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/** HW return from error interrupt. */
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Fault hwrei(unsigned tid);
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/** Returns if a specific PC is a PAL mode PC. */
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bool inPalMode(uint64_t PC)
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{ return AlphaISA::PcPAL(PC); }
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/** Traps to handle given fault. */
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void trap(Fault fault, unsigned tid);
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bool simPalCheck(int palFunc, unsigned tid);
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/** Processes any interrupts. */
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void processInterrupts();
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/** Halts the CPU. */
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void halt() { panic("Halt not implemented!\n"); }
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#endif
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#if !FULL_SYSTEM
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/** Executes a syscall.
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* @todo: Determine if this needs to be virtual.
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*/
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void syscall(int thread_num);
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/** Gets a syscall argument. */
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IntReg getSyscallArg(int i, int tid);
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/** Used to shift args for indirect syscall. */
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void setSyscallArg(int i, IntReg val, int tid);
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/** Sets the return value of a syscall. */
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void setSyscallReturn(SyscallReturn return_value, int tid);
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#endif
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/** Read from memory function. */
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template <class T>
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Fault read(MemReqPtr &req, T &data)
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{
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#if 0
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#if FULL_SYSTEM && defined(TARGET_ALPHA)
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if (req->flags & LOCKED) {
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req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
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req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
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}
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#endif
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#endif
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Fault error;
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#if FULL_SYSTEM
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// @todo: Fix this LL/SC hack.
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if (req->flags & LOCKED) {
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lockAddr = req->paddr;
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lockFlag = true;
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}
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#endif
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error = this->mem->read(req, data);
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data = gtoh(data);
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return error;
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}
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/** CPU read function, forwards read to LSQ. */
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template <class T>
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Fault read(MemReqPtr &req, T &data, int load_idx)
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{
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return this->iew.ldstQueue.read(req, data, load_idx);
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}
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/** Write to memory function. */
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template <class T>
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Fault write(MemReqPtr &req, T &data)
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{
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#if 0
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#if FULL_SYSTEM && defined(TARGET_ALPHA)
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ExecContext *xc;
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// If this is a store conditional, act appropriately
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if (req->flags & LOCKED) {
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xc = req->xc;
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if (req->flags & UNCACHEABLE) {
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// Don't update result register (see stq_c in isa_desc)
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req->result = 2;
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xc->setStCondFailures(0);//Needed? [RGD]
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} else {
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bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
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Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
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req->result = lock_flag;
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if (!lock_flag ||
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((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
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xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
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xc->setStCondFailures(xc->readStCondFailures() + 1);
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if (((xc->readStCondFailures()) % 100000) == 0) {
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std::cerr << "Warning: "
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<< xc->readStCondFailures()
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<< " consecutive store conditional failures "
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<< "on cpu " << req->xc->readCpuId()
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<< std::endl;
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}
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return NoFault;
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}
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else xc->setStCondFailures(0);
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}
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}
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// Need to clear any locked flags on other proccessors for
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// this address. Only do this for succsful Store Conditionals
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// and all other stores (WH64?). Unsuccessful Store
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// Conditionals would have returned above, and wouldn't fall
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// through.
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for (int i = 0; i < this->system->execContexts.size(); i++){
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xc = this->system->execContexts[i];
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if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
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(req->paddr & ~0xf)) {
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xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
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}
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}
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#endif
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#endif
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#if FULL_SYSTEM
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// @todo: Fix this LL/SC hack.
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if (req->flags & LOCKED) {
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if (req->flags & UNCACHEABLE) {
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req->result = 2;
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} else {
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if (this->lockFlag) {
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req->result = 1;
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} else {
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req->result = 0;
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return NoFault;
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}
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}
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}
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#endif
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return this->mem->write(req, (T)htog(data));
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}
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/** CPU write function, forwards write to LSQ. */
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template <class T>
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Fault write(MemReqPtr &req, T &data, int store_idx)
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{
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return this->iew.ldstQueue.write(req, data, store_idx);
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}
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Addr lockAddr;
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bool lockFlag;
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};
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#endif // __CPU_O3_ALPHA_FULL_CPU_HH__
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