10c79efe55
SConscript:
The new faults.cc file in sim allocates the system wide faults. When these faults are generated through a function interface in the ISA, this file may go away.
arch/alpha/alpha_memory.cc:
Changed Fault to Fault * and took the underscores out of fault names.
arch/alpha/alpha_memory.hh:
Changed Fault to Fault *. Also, added an include for the alpha faults.
arch/alpha/ev5.cc:
Changed the fault_addr array into a fault_addr function. Once all of the faults can be expected to have the same type, fault_addr can go away completely and the info it provided will come from the fault itself. Also, Fault was changed to Fault *, and underscores were taken out of fault names.
arch/alpha/isa/decoder.isa:
Changed Fault to Fault * and took the underscores out fault names.
arch/alpha/isa/fp.isa:
Changed Fault to Fault *, and took the underscores out of fault names.
arch/alpha/isa/main.isa:
Changed Fault to Fault *, removed underscores from fault names, and made an include of the alpha faults show up in all the generated files.
arch/alpha/isa/mem.isa:
Changed Fault to Fault * and removed underscores from fault names.
arch/alpha/isa/unimp.isa:
arch/alpha/isa/unknown.isa:
cpu/exec_context.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
Changed Fault to Fault *, and removed underscores from fault names.
arch/alpha/isa_traits.hh:
Changed the include of arch/alpha/faults.hh to sim/faults.hh, since the alpha faults weren't needed.
cpu/base_dyn_inst.cc:
Changed Fault to Fault *, and removed underscores from fault names. This file probably shouldn't use the Unimplemented Opcode fault.
cpu/base_dyn_inst.hh:
Changed Fault to Fault * and took the underscores out of the fault names.
cpu/exec_context.cc:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/fetch.hh:
dev/alpha_console.hh:
dev/baddev.hh:
dev/ide_ctrl.hh:
dev/isa_fake.hh:
dev/ns_gige.hh:
dev/pciconfigall.hh:
dev/sinic.hh:
dev/tsunami_cchip.hh:
dev/tsunami_io.hh:
dev/tsunami_pchip.hh:
dev/uart.hh:
dev/uart8250.hh:
Changed Fault to Fault *.
cpu/o3/alpha_cpu.hh:
Changed Fault to Fault *, removed underscores from fault names.
cpu/o3/alpha_cpu_impl.hh:
Changed Fault to Fault *, removed underscores from fault names, and changed the fault_addr array to the fault_addr function. Once all faults are from the ISA, this function will probably go away.
cpu/o3/commit_impl.hh:
cpu/o3/fetch_impl.hh:
dev/baddev.cc:
Changed Fault to Fault *, and removed underscores from the fault names.
cpu/o3/regfile.hh:
Added an include for the alpha specific faults which will hopefully go away once the ipr stuff is moved, changed Fault to Fault *, and removed the underscores from fault names.
cpu/simple/cpu.hh:
Changed Fault to Fault *
dev/ns_gige.cc:
Changed Fault to Fault *, and removdd underscores from fault names.
dev/sinic.cc:
Changed Fault to Fault *, and removed the underscores from fault names.
dev/uart8250.cc:
Chanted Fault to Fault *, and removed underscores from fault names.
kern/kernel_stats.cc:
Removed underscores from fault names, and from NumFaults.
kern/kernel_stats.hh:
Changed the predeclaration of Fault from an enum to a class, and changd the "fault" function to work with the classes instead of the enum. Once there are no system wide faults anymore, this code will simplify back to something like it was originally.
sim/faults.cc:
This allocates the system wide faults.
sim/faults.hh:
This declares the system wide faults.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
Removed the underscores from fault names.
--HG--
rename : arch/alpha/faults.cc => sim/faults.cc
rename : arch/alpha/faults.hh => sim/faults.hh
extra : convert_revision : 253d39258237333ae8ec4d8047367cb3ea68569d
682 lines
18 KiB
C++
682 lines
18 KiB
C++
/*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sstream>
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#include <string>
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#include <vector>
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#include "arch/alpha/alpha_memory.hh"
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#include "base/inifile.hh"
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#include "base/str.hh"
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#include "base/trace.hh"
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#include "config/alpha_tlaser.hh"
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#include "cpu/exec_context.hh"
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#include "sim/builder.hh"
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using namespace std;
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using namespace EV5;
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///////////////////////////////////////////////////////////////////////
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//
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// Alpha TLB
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//
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#ifdef DEBUG
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bool uncacheBit39 = false;
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bool uncacheBit40 = false;
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#endif
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#define MODE2MASK(X) (1 << (X))
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AlphaTLB::AlphaTLB(const string &name, int s)
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: SimObject(name), size(s), nlu(0)
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{
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table = new AlphaISA::PTE[size];
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memset(table, 0, sizeof(AlphaISA::PTE[size]));
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}
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AlphaTLB::~AlphaTLB()
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{
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if (table)
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delete [] table;
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}
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// look up an entry in the TLB
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AlphaISA::PTE *
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AlphaTLB::lookup(Addr vpn, uint8_t asn) const
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{
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// assume not found...
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AlphaISA::PTE *retval = NULL;
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PageTable::const_iterator i = lookupTable.find(vpn);
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if (i != lookupTable.end()) {
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while (i->first == vpn) {
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int index = i->second;
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AlphaISA::PTE *pte = &table[index];
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assert(pte->valid);
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if (vpn == pte->tag && (pte->asma || pte->asn == asn)) {
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retval = pte;
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break;
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}
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++i;
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}
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}
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DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
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retval ? "hit" : "miss", retval ? retval->ppn : 0);
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return retval;
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}
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void
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AlphaTLB::checkCacheability(MemReqPtr &req)
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{
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// in Alpha, cacheability is controlled by upper-level bits of the
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// physical address
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/*
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* We support having the uncacheable bit in either bit 39 or bit 40.
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* The Turbolaser platform (and EV5) support having the bit in 39, but
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* Tsunami (which Linux assumes uses an EV6) generates accesses with
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* the bit in 40. So we must check for both, but we have debug flags
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* to catch a weird case where both are used, which shouldn't happen.
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*/
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#if ALPHA_TLASER
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if (req->paddr & PAddrUncachedBit39) {
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#else
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if (req->paddr & PAddrUncachedBit43) {
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#endif
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// IPR memory space not implemented
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if (PAddrIprSpace(req->paddr)) {
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if (!req->xc->misspeculating()) {
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switch (req->paddr) {
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case ULL(0xFFFFF00188):
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req->data = 0;
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break;
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default:
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panic("IPR memory space not implemented! PA=%x\n",
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req->paddr);
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}
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}
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} else {
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// mark request as uncacheable
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req->flags |= UNCACHEABLE;
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#if !ALPHA_TLASER
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// Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
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req->paddr &= PAddrUncachedMask;
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#endif
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}
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}
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}
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// insert a new TLB entry
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void
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AlphaTLB::insert(Addr addr, AlphaISA::PTE &pte)
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{
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AlphaISA::VAddr vaddr = addr;
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if (table[nlu].valid) {
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Addr oldvpn = table[nlu].tag;
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PageTable::iterator i = lookupTable.find(oldvpn);
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if (i == lookupTable.end())
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panic("TLB entry not found in lookupTable");
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int index;
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while ((index = i->second) != nlu) {
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if (table[index].tag != oldvpn)
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panic("TLB entry not found in lookupTable");
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++i;
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}
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DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn);
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lookupTable.erase(i);
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}
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DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), pte.ppn);
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table[nlu] = pte;
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table[nlu].tag = vaddr.vpn();
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table[nlu].valid = true;
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lookupTable.insert(make_pair(vaddr.vpn(), nlu));
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nextnlu();
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}
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void
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AlphaTLB::flushAll()
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{
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DPRINTF(TLB, "flushAll\n");
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memset(table, 0, sizeof(AlphaISA::PTE[size]));
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lookupTable.clear();
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nlu = 0;
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}
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void
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AlphaTLB::flushProcesses()
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{
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PageTable::iterator i = lookupTable.begin();
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PageTable::iterator end = lookupTable.end();
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while (i != end) {
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int index = i->second;
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AlphaISA::PTE *pte = &table[index];
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assert(pte->valid);
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// we can't increment i after we erase it, so save a copy and
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// increment it to get the next entry now
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PageTable::iterator cur = i;
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++i;
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if (!pte->asma) {
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DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, pte->tag, pte->ppn);
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pte->valid = false;
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lookupTable.erase(cur);
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}
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}
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}
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void
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AlphaTLB::flushAddr(Addr addr, uint8_t asn)
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{
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AlphaISA::VAddr vaddr = addr;
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PageTable::iterator i = lookupTable.find(vaddr.vpn());
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if (i == lookupTable.end())
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return;
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while (i->first == vaddr.vpn()) {
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int index = i->second;
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AlphaISA::PTE *pte = &table[index];
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assert(pte->valid);
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if (vaddr.vpn() == pte->tag && (pte->asma || pte->asn == asn)) {
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DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(),
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pte->ppn);
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// invalidate this entry
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pte->valid = false;
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lookupTable.erase(i);
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}
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++i;
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}
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}
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void
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AlphaTLB::serialize(ostream &os)
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{
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SERIALIZE_SCALAR(size);
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SERIALIZE_SCALAR(nlu);
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for (int i = 0; i < size; i++) {
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nameOut(os, csprintf("%s.PTE%d", name(), i));
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table[i].serialize(os);
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}
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}
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void
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AlphaTLB::unserialize(Checkpoint *cp, const string §ion)
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{
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UNSERIALIZE_SCALAR(size);
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UNSERIALIZE_SCALAR(nlu);
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for (int i = 0; i < size; i++) {
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table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
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if (table[i].valid) {
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lookupTable.insert(make_pair(table[i].tag, i));
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}
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}
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}
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///////////////////////////////////////////////////////////////////////
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//
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// Alpha ITB
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//
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AlphaITB::AlphaITB(const std::string &name, int size)
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: AlphaTLB(name, size)
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{}
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void
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AlphaITB::regStats()
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{
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hits
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.name(name() + ".hits")
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.desc("ITB hits");
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misses
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.name(name() + ".misses")
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.desc("ITB misses");
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acv
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.name(name() + ".acv")
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.desc("ITB acv");
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accesses
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.name(name() + ".accesses")
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.desc("ITB accesses");
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accesses = hits + misses;
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}
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void
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AlphaITB::fault(Addr pc, ExecContext *xc) const
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{
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uint64_t *ipr = xc->regs.ipr;
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if (!xc->misspeculating()) {
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ipr[AlphaISA::IPR_ITB_TAG] = pc;
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ipr[AlphaISA::IPR_IFAULT_VA_FORM] =
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ipr[AlphaISA::IPR_IVPTBR] | (AlphaISA::VAddr(pc).vpn() << 3);
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}
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}
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Fault *
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AlphaITB::translate(MemReqPtr &req) const
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{
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InternalProcReg *ipr = req->xc->regs.ipr;
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if (AlphaISA::PcPAL(req->vaddr)) {
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// strip off PAL PC marker (lsb is 1)
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req->paddr = (req->vaddr & ~3) & PAddrImplMask;
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hits++;
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return NoFault;
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}
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if (req->flags & PHYSICAL) {
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req->paddr = req->vaddr;
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} else {
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// verify that this is a good virtual address
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if (!validVirtualAddress(req->vaddr)) {
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fault(req->vaddr, req->xc);
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acv++;
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return ItbAcvFault;
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}
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// VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
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// VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
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#if ALPHA_TLASER
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if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
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VAddrSpaceEV5(req->vaddr) == 2) {
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#else
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if (VAddrSpaceEV6(req->vaddr) == 0x7e) {
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#endif
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// only valid in kernel mode
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if (ICM_CM(ipr[AlphaISA::IPR_ICM]) !=
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AlphaISA::mode_kernel) {
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fault(req->vaddr, req->xc);
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acv++;
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return ItbAcvFault;
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}
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req->paddr = req->vaddr & PAddrImplMask;
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#if !ALPHA_TLASER
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// sign extend the physical address properly
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if (req->paddr & PAddrUncachedBit40)
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req->paddr |= ULL(0xf0000000000);
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else
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req->paddr &= ULL(0xffffffffff);
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#endif
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} else {
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// not a physical address: need to look up pte
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AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(),
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DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
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if (!pte) {
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fault(req->vaddr, req->xc);
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misses++;
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return ItbPageFault;
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}
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req->paddr = (pte->ppn << AlphaISA::PageShift) +
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(AlphaISA::VAddr(req->vaddr).offset() & ~3);
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// check permissions for this access
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if (!(pte->xre & (1 << ICM_CM(ipr[AlphaISA::IPR_ICM])))) {
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// instruction access fault
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fault(req->vaddr, req->xc);
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acv++;
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return ItbAcvFault;
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}
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hits++;
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}
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}
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// check that the physical address is ok (catch bad physical addresses)
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if (req->paddr & ~PAddrImplMask)
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return MachineCheckFault;
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checkCacheability(req);
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return NoFault;
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}
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///////////////////////////////////////////////////////////////////////
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//
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// Alpha DTB
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//
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AlphaDTB::AlphaDTB(const std::string &name, int size)
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: AlphaTLB(name, size)
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{}
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void
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AlphaDTB::regStats()
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{
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read_hits
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.name(name() + ".read_hits")
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.desc("DTB read hits")
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;
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read_misses
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.name(name() + ".read_misses")
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.desc("DTB read misses")
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;
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read_acv
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.name(name() + ".read_acv")
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.desc("DTB read access violations")
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;
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read_accesses
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.name(name() + ".read_accesses")
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.desc("DTB read accesses")
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;
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write_hits
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.name(name() + ".write_hits")
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.desc("DTB write hits")
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;
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write_misses
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.name(name() + ".write_misses")
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.desc("DTB write misses")
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;
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write_acv
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.name(name() + ".write_acv")
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.desc("DTB write access violations")
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;
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write_accesses
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.name(name() + ".write_accesses")
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.desc("DTB write accesses")
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;
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hits
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.name(name() + ".hits")
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.desc("DTB hits")
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;
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misses
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.name(name() + ".misses")
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.desc("DTB misses")
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;
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acv
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.name(name() + ".acv")
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.desc("DTB access violations")
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;
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accesses
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.name(name() + ".accesses")
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.desc("DTB accesses")
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;
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hits = read_hits + write_hits;
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misses = read_misses + write_misses;
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acv = read_acv + write_acv;
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accesses = read_accesses + write_accesses;
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}
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void
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AlphaDTB::fault(MemReqPtr &req, uint64_t flags) const
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{
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ExecContext *xc = req->xc;
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AlphaISA::VAddr vaddr = req->vaddr;
|
|
uint64_t *ipr = xc->regs.ipr;
|
|
|
|
// Set fault address and flags. Even though we're modeling an
|
|
// EV5, we use the EV6 technique of not latching fault registers
|
|
// on VPTE loads (instead of locking the registers until IPR_VA is
|
|
// read, like the EV5). The EV6 approach is cleaner and seems to
|
|
// work with EV5 PAL code, but not the other way around.
|
|
if (!xc->misspeculating()
|
|
&& !(req->flags & VPTE) && !(req->flags & NO_FAULT)) {
|
|
// set VA register with faulting address
|
|
ipr[AlphaISA::IPR_VA] = req->vaddr;
|
|
|
|
// set MM_STAT register flags
|
|
ipr[AlphaISA::IPR_MM_STAT] =
|
|
(((Opcode(xc->getInst()) & 0x3f) << 11)
|
|
| ((Ra(xc->getInst()) & 0x1f) << 6)
|
|
| (flags & 0x3f));
|
|
|
|
// set VA_FORM register with faulting formatted address
|
|
ipr[AlphaISA::IPR_VA_FORM] =
|
|
ipr[AlphaISA::IPR_MVPTBR] | (vaddr.vpn() << 3);
|
|
}
|
|
}
|
|
|
|
Fault *
|
|
AlphaDTB::translate(MemReqPtr &req, bool write) const
|
|
{
|
|
RegFile *regs = &req->xc->regs;
|
|
Addr pc = regs->pc;
|
|
InternalProcReg *ipr = regs->ipr;
|
|
|
|
AlphaISA::mode_type mode =
|
|
(AlphaISA::mode_type)DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]);
|
|
|
|
|
|
/**
|
|
* Check for alignment faults
|
|
*/
|
|
if (req->vaddr & (req->size - 1)) {
|
|
fault(req, write ? MM_STAT_WR_MASK : 0);
|
|
DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->vaddr,
|
|
req->size);
|
|
return AlignmentFault;
|
|
}
|
|
|
|
if (pc & 0x1) {
|
|
mode = (req->flags & ALTMODE) ?
|
|
(AlphaISA::mode_type)ALT_MODE_AM(ipr[AlphaISA::IPR_ALT_MODE])
|
|
: AlphaISA::mode_kernel;
|
|
}
|
|
|
|
if (req->flags & PHYSICAL) {
|
|
req->paddr = req->vaddr;
|
|
} else {
|
|
// verify that this is a good virtual address
|
|
if (!validVirtualAddress(req->vaddr)) {
|
|
fault(req, (write ? MM_STAT_WR_MASK : 0) |
|
|
MM_STAT_BAD_VA_MASK |
|
|
MM_STAT_ACV_MASK);
|
|
|
|
if (write) { write_acv++; } else { read_acv++; }
|
|
return DtbPageFault;
|
|
}
|
|
|
|
// Check for "superpage" mapping
|
|
#if ALPHA_TLASER
|
|
if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
|
|
VAddrSpaceEV5(req->vaddr) == 2) {
|
|
#else
|
|
if (VAddrSpaceEV6(req->vaddr) == 0x7e) {
|
|
#endif
|
|
|
|
// only valid in kernel mode
|
|
if (DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]) !=
|
|
AlphaISA::mode_kernel) {
|
|
fault(req, ((write ? MM_STAT_WR_MASK : 0) |
|
|
MM_STAT_ACV_MASK));
|
|
if (write) { write_acv++; } else { read_acv++; }
|
|
return DtbAcvFault;
|
|
}
|
|
|
|
req->paddr = req->vaddr & PAddrImplMask;
|
|
|
|
#if !ALPHA_TLASER
|
|
// sign extend the physical address properly
|
|
if (req->paddr & PAddrUncachedBit40)
|
|
req->paddr |= ULL(0xf0000000000);
|
|
else
|
|
req->paddr &= ULL(0xffffffffff);
|
|
#endif
|
|
|
|
} else {
|
|
if (write)
|
|
write_accesses++;
|
|
else
|
|
read_accesses++;
|
|
|
|
// not a physical address: need to look up pte
|
|
AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(),
|
|
DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
|
|
|
|
if (!pte) {
|
|
// page fault
|
|
fault(req, (write ? MM_STAT_WR_MASK : 0) |
|
|
MM_STAT_DTB_MISS_MASK);
|
|
if (write) { write_misses++; } else { read_misses++; }
|
|
return (req->flags & VPTE) ? (Fault *)PDtbMissFault : (Fault *)NDtbMissFault;
|
|
}
|
|
|
|
req->paddr = (pte->ppn << AlphaISA::PageShift) +
|
|
AlphaISA::VAddr(req->vaddr).offset();
|
|
|
|
if (write) {
|
|
if (!(pte->xwe & MODE2MASK(mode))) {
|
|
// declare the instruction access fault
|
|
fault(req, MM_STAT_WR_MASK |
|
|
MM_STAT_ACV_MASK |
|
|
(pte->fonw ? MM_STAT_FONW_MASK : 0));
|
|
write_acv++;
|
|
return DtbPageFault;
|
|
}
|
|
if (pte->fonw) {
|
|
fault(req, MM_STAT_WR_MASK |
|
|
MM_STAT_FONW_MASK);
|
|
write_acv++;
|
|
return DtbPageFault;
|
|
}
|
|
} else {
|
|
if (!(pte->xre & MODE2MASK(mode))) {
|
|
fault(req, MM_STAT_ACV_MASK |
|
|
(pte->fonr ? MM_STAT_FONR_MASK : 0));
|
|
read_acv++;
|
|
return DtbAcvFault;
|
|
}
|
|
if (pte->fonr) {
|
|
fault(req, MM_STAT_FONR_MASK);
|
|
read_acv++;
|
|
return DtbPageFault;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (write)
|
|
write_hits++;
|
|
else
|
|
read_hits++;
|
|
}
|
|
|
|
// check that the physical address is ok (catch bad physical addresses)
|
|
if (req->paddr & ~PAddrImplMask)
|
|
return MachineCheckFault;
|
|
|
|
checkCacheability(req);
|
|
|
|
return NoFault;
|
|
}
|
|
|
|
AlphaISA::PTE &
|
|
AlphaTLB::index(bool advance)
|
|
{
|
|
AlphaISA::PTE *pte = &table[nlu];
|
|
|
|
if (advance)
|
|
nextnlu();
|
|
|
|
return *pte;
|
|
}
|
|
|
|
DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", AlphaTLB)
|
|
|
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaITB)
|
|
|
|
Param<int> size;
|
|
|
|
END_DECLARE_SIM_OBJECT_PARAMS(AlphaITB)
|
|
|
|
BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaITB)
|
|
|
|
INIT_PARAM_DFLT(size, "TLB size", 48)
|
|
|
|
END_INIT_SIM_OBJECT_PARAMS(AlphaITB)
|
|
|
|
|
|
CREATE_SIM_OBJECT(AlphaITB)
|
|
{
|
|
return new AlphaITB(getInstanceName(), size);
|
|
}
|
|
|
|
REGISTER_SIM_OBJECT("AlphaITB", AlphaITB)
|
|
|
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB)
|
|
|
|
Param<int> size;
|
|
|
|
END_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB)
|
|
|
|
BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDTB)
|
|
|
|
INIT_PARAM_DFLT(size, "TLB size", 64)
|
|
|
|
END_INIT_SIM_OBJECT_PARAMS(AlphaDTB)
|
|
|
|
|
|
CREATE_SIM_OBJECT(AlphaDTB)
|
|
{
|
|
return new AlphaDTB(getInstanceName(), size);
|
|
}
|
|
|
|
REGISTER_SIM_OBJECT("AlphaDTB", AlphaDTB)
|
|
|