c761aaae65
objects. The improper serialization of arrays was particularly
bad.
dev/alpha_console.cc:
dev/isa_fake.cc:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
the pio interface is a different simobject and should have a
different name.
dev/ethertap.cc:
fix serialization.
dev/ide_ctrl.cc:
- the pio interface is a different simobject and should have a
different name.
- properly initialize variables
- When serializing an array, the size is the number of elements,
not the number of bytes!
dev/pcidev.cc:
When serializing an array, the size is the number of elements,
not the number of bytes!
dev/tsunami_io.hh:
Don't make objects SimObjects if they're not exposed to python.
Don't add serialization functions to events, it's generally not
what you want.
allow the real time clock and interval timer to serialize themselves,
must pass a base name since it is not a SimObject and the values will
be going into the section of the parent.
--HG--
extra : convert_revision : 3fc5de9b858ed770c8f385cf38b53242cf859c33
369 lines
11 KiB
C++
369 lines
11 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/** @file
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* Tsunami I/O Space mapping including RTC/timer interrupts
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*/
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#ifndef __DEV_TSUNAMI_IO_HH__
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#define __DEV_TSUNAMI_IO_HH__
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#include "dev/io_device.hh"
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#include "base/range.hh"
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#include "dev/tsunami.hh"
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#include "sim/eventq.hh"
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/**
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* Tsunami I/O device is a catch all for all the south bridge stuff we care
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* to implement.
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*/
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class TsunamiIO : public PioDevice
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{
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private:
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/** The base address of this device */
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Addr addr;
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/** The size of mappad from the above address */
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static const Addr size = 0xff;
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struct tm tm;
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protected:
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/** Real-Time Clock (MC146818) */
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class RTC
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{
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private:
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/** Event for RTC periodic interrupt */
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struct RTCEvent : public Event
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{
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/** A pointer back to tsunami to create interrupt the processor. */
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Tsunami* tsunami;
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Tick interval;
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RTCEvent(Tsunami* t, Tick i);
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/** Schedule the RTC periodic interrupt */
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void scheduleIntr();
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/** Event process to occur at interrupt*/
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virtual void process();
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/** Event description */
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virtual const char *description();
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};
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private:
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std::string _name;
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const std::string &name() const { return _name; }
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/** RTC periodic interrupt event */
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RTCEvent event;
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/** Current RTC register address/index */
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int addr;
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/** Data for real-time clock function */
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union {
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uint8_t clock_data[10];
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struct {
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uint8_t sec;
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uint8_t sec_alrm;
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uint8_t min;
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uint8_t min_alrm;
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uint8_t hour;
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uint8_t hour_alrm;
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uint8_t wday;
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uint8_t mday;
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uint8_t mon;
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uint8_t year;
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};
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};
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/** RTC status register A */
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uint8_t stat_regA;
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/** RTC status register B */
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uint8_t stat_regB;
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public:
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RTC(const std::string &name, Tsunami* t, Tick i);
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/** Set the initial RTC time/date */
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void set_time(time_t t);
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/** RTC address port: write address of RTC RAM data to access */
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void writeAddr(const uint8_t *data);
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/** RTC write data */
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void writeData(const uint8_t *data);
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/** RTC read data */
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void readData(uint8_t *data);
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/**
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* Serialize this object to the given output stream.
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* @param os The stream to serialize to.
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*/
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void serialize(const std::string &base, std::ostream &os);
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/**
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* Reconstruct the state of this object from a checkpoint.
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* @param cp The checkpoint use.
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* @param section The section name of this object
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*/
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void unserialize(const std::string &base, Checkpoint *cp,
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const std::string §ion);
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};
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/** Programmable Interval Timer (Intel 8254) */
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class PITimer
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{
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/** Counter element for PIT */
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class Counter
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{
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/** Event for counter interrupt */
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class CounterEvent : public Event
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{
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private:
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/** Pointer back to Counter */
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Counter* counter;
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Tick interval;
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public:
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CounterEvent(Counter*);
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/** Event process */
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virtual void process();
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/** Event description */
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virtual const char *description();
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friend class Counter;
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};
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private:
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std::string _name;
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const std::string &name() const { return _name; }
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CounterEvent event;
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/** Current count value */
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uint16_t count;
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/** Latched count */
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uint16_t latched_count;
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/** Interrupt period */
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uint16_t period;
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/** Current mode of operation */
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uint8_t mode;
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/** Output goes high when the counter reaches zero */
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bool output_high;
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/** State of the count latch */
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bool latch_on;
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/** Set of values for read_byte and write_byte */
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enum {LSB, MSB};
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/** Determine which byte of a 16-bit count value to read/write */
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uint8_t read_byte, write_byte;
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public:
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Counter(const std::string &name);
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/** Latch the current count (if one is not already latched) */
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void latchCount();
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/** Set the read/write mode */
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void setRW(int rw_val);
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/** Set operational mode */
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void setMode(int mode_val);
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/** Set count encoding */
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void setBCD(int bcd_val);
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/** Read a count byte */
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void read(uint8_t *data);
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/** Write a count byte */
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void write(const uint8_t *data);
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/** Is the output high? */
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bool outputHigh();
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/**
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* Serialize this object to the given output stream.
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* @param os The stream to serialize to.
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*/
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void serialize(const std::string &base, std::ostream &os);
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/**
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* Reconstruct the state of this object from a checkpoint.
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* @param cp The checkpoint use.
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* @param section The section name of this object
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*/
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void unserialize(const std::string &base, Checkpoint *cp,
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const std::string §ion);
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};
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private:
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std::string _name;
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const std::string &name() const { return _name; }
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/** PIT has three seperate counters */
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Counter *counter[3];
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public:
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/** Public way to access individual counters (avoid array accesses) */
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Counter counter0;
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Counter counter1;
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Counter counter2;
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PITimer(const std::string &name);
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/** Write control word */
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void writeControl(const uint8_t* data);
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/**
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* Serialize this object to the given output stream.
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* @param os The stream to serialize to.
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*/
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void serialize(const std::string &base, std::ostream &os);
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/**
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* Reconstruct the state of this object from a checkpoint.
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* @param cp The checkpoint use.
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* @param section The section name of this object
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*/
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void unserialize(const std::string &base, Checkpoint *cp,
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const std::string §ion);
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};
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/** Mask of the PIC1 */
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uint8_t mask1;
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/** Mask of the PIC2 */
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uint8_t mask2;
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/** Mode of PIC1. Not used for anything */
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uint8_t mode1;
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/** Mode of PIC2. Not used for anything */
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uint8_t mode2;
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/** Raw PIC interrupt register before masking */
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uint8_t picr; //Raw PIC interrput register
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/** Is the pic interrupting right now or not. */
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bool picInterrupting;
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Tick clockInterval;
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/** A pointer to the Tsunami device which be belong to */
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Tsunami *tsunami;
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/** Intel 8253 Periodic Interval Timer */
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PITimer pitimer;
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RTC rtc;
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/** The interval is set via two writes to the PIT.
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* This variable contains a flag as to how many writes have happened, and
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* the time so far.
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*/
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uint16_t timerData;
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public:
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/**
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* Return the freqency of the RTC
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* @return interrupt rate of the RTC
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*/
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Tick frequency() const;
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/**
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* Initialize all the data for devices supported by Tsunami I/O.
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* @param name name of this device.
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* @param t pointer back to the Tsunami object that we belong to.
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* @param init_time Time (as in seconds since 1970) to set RTC to.
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* @param a address we are mapped at.
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* @param mmu pointer to the memory controller that sends us events.
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*/
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TsunamiIO(const std::string &name, Tsunami *t, time_t init_time,
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Addr a, MemoryController *mmu, HierParams *hier, Bus *bus,
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Tick pio_latency, Tick ci);
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/**
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* Process a read to one of the devices we are emulating.
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* @param req Contains the address to read from.
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* @param data A pointer to write the read data to.
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* @return The fault condition of the access.
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*/
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virtual Fault read(MemReqPtr &req, uint8_t *data);
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/**
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* Process a write to one of the devices we emulate.
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* @param req Contains the address to write to.
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* @param data The data to write.
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* @return The fault condition of the access.
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*/
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virtual Fault write(MemReqPtr &req, const uint8_t *data);
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/**
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* Post an PIC interrupt to the CPU via the CChip
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* @param bitvector interrupt to post.
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*/
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void postPIC(uint8_t bitvector);
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/**
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* Clear a posted interrupt
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* @param bitvector interrupt to clear
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*/
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void clearPIC(uint8_t bitvector);
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/**
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* Serialize this object to the given output stream.
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* @param os The stream to serialize to.
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*/
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virtual void serialize(std::ostream &os);
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/**
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* Reconstruct the state of this object from a checkpoint.
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* @param cp The checkpoint use.
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* @param section The section name of this object
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*/
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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Tick cacheAccess(MemReqPtr &req);
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};
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#endif // __DEV_TSUNAMI_IO_HH__
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