c75ff71139
In general, the ThreadID parameter is unnecessary in the memory system as the ContextID is what is used for the purposes of locks/wakeups. Since we allocate sequential ContextIDs for each thread on MT-enabled CPUs, ThreadID is unnecessary as the CPUs can identify the requesting thread through sideband info (SenderState / LSQ entries) or ContextID offset from the base ContextID for a cpu. This is a re-spin of 20264eb after the revert (bd1c6789) and includes some fixes of that commit.
702 lines
20 KiB
C++
702 lines
20 KiB
C++
/*
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* Copyright 2014 Google, Inc.
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* Copyright (c) 2012-2013,2015 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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*/
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#include "arch/locked_mem.hh"
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#include "arch/mmapped_ipr.hh"
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#include "arch/utility.hh"
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#include "base/bigint.hh"
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#include "base/output.hh"
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#include "config/the_isa.hh"
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#include "cpu/simple/atomic.hh"
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#include "cpu/exetrace.hh"
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#include "debug/Drain.hh"
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#include "debug/ExecFaulting.hh"
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#include "debug/SimpleCPU.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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#include "mem/physical.hh"
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#include "params/AtomicSimpleCPU.hh"
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#include "sim/faults.hh"
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#include "sim/system.hh"
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#include "sim/full_system.hh"
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using namespace std;
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using namespace TheISA;
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AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
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: Event(CPU_Tick_Pri), cpu(c)
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{
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}
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void
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AtomicSimpleCPU::TickEvent::process()
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{
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cpu->tick();
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}
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const char *
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AtomicSimpleCPU::TickEvent::description() const
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{
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return "AtomicSimpleCPU tick";
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}
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void
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AtomicSimpleCPU::init()
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{
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BaseSimpleCPU::init();
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int cid = threadContexts[0]->contextId();
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ifetch_req.setContext(cid);
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data_read_req.setContext(cid);
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data_write_req.setContext(cid);
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}
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AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
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: BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false),
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simulate_data_stalls(p->simulate_data_stalls),
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simulate_inst_stalls(p->simulate_inst_stalls),
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icachePort(name() + ".icache_port", this),
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dcachePort(name() + ".dcache_port", this),
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fastmem(p->fastmem), dcache_access(false), dcache_latency(0),
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ppCommit(nullptr)
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{
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_status = Idle;
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}
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AtomicSimpleCPU::~AtomicSimpleCPU()
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{
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if (tickEvent.scheduled()) {
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deschedule(tickEvent);
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}
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}
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DrainState
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AtomicSimpleCPU::drain()
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{
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if (switchedOut())
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return DrainState::Drained;
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if (!isDrained()) {
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DPRINTF(Drain, "Requesting drain.\n");
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return DrainState::Draining;
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} else {
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if (tickEvent.scheduled())
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deschedule(tickEvent);
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activeThreads.clear();
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DPRINTF(Drain, "Not executing microcode, no need to drain.\n");
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return DrainState::Drained;
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}
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}
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void
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AtomicSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender)
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{
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DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(),
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pkt->cmdString());
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for (ThreadID tid = 0; tid < numThreads; tid++) {
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if (tid != sender) {
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if (getCpuAddrMonitor(tid)->doMonitor(pkt)) {
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wakeup(tid);
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}
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TheISA::handleLockedSnoop(threadInfo[tid]->thread,
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pkt, dcachePort.cacheBlockMask);
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}
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}
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}
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void
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AtomicSimpleCPU::drainResume()
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{
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assert(!tickEvent.scheduled());
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if (switchedOut())
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return;
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DPRINTF(SimpleCPU, "Resume\n");
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verifyMemoryMode();
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assert(!threadContexts.empty());
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_status = BaseSimpleCPU::Idle;
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for (ThreadID tid = 0; tid < numThreads; tid++) {
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if (threadInfo[tid]->thread->status() == ThreadContext::Active) {
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threadInfo[tid]->notIdleFraction = 1;
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activeThreads.push_back(tid);
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_status = BaseSimpleCPU::Running;
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// Tick if any threads active
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if (!tickEvent.scheduled()) {
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schedule(tickEvent, nextCycle());
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}
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} else {
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threadInfo[tid]->notIdleFraction = 0;
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}
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}
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}
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bool
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AtomicSimpleCPU::tryCompleteDrain()
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{
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if (drainState() != DrainState::Draining)
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return false;
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DPRINTF(Drain, "tryCompleteDrain.\n");
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if (!isDrained())
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return false;
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DPRINTF(Drain, "CPU done draining, processing drain event\n");
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signalDrainDone();
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return true;
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}
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void
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AtomicSimpleCPU::switchOut()
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{
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BaseSimpleCPU::switchOut();
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assert(!tickEvent.scheduled());
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assert(_status == BaseSimpleCPU::Running || _status == Idle);
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assert(isDrained());
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}
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void
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AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
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{
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BaseSimpleCPU::takeOverFrom(oldCPU);
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// The tick event should have been descheduled by drain()
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assert(!tickEvent.scheduled());
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}
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void
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AtomicSimpleCPU::verifyMemoryMode() const
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{
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if (!system->isAtomicMode()) {
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fatal("The atomic CPU requires the memory system to be in "
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"'atomic' mode.\n");
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}
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}
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void
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AtomicSimpleCPU::activateContext(ThreadID thread_num)
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{
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DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num);
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assert(thread_num < numThreads);
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threadInfo[thread_num]->notIdleFraction = 1;
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Cycles delta = ticksToCycles(threadInfo[thread_num]->thread->lastActivate -
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threadInfo[thread_num]->thread->lastSuspend);
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numCycles += delta;
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ppCycles->notify(delta);
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if (!tickEvent.scheduled()) {
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//Make sure ticks are still on multiples of cycles
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schedule(tickEvent, clockEdge(Cycles(0)));
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}
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_status = BaseSimpleCPU::Running;
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if (std::find(activeThreads.begin(), activeThreads.end(), thread_num)
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== activeThreads.end()) {
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activeThreads.push_back(thread_num);
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}
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}
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void
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AtomicSimpleCPU::suspendContext(ThreadID thread_num)
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{
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DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
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assert(thread_num < numThreads);
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activeThreads.remove(thread_num);
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if (_status == Idle)
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return;
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assert(_status == BaseSimpleCPU::Running);
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threadInfo[thread_num]->notIdleFraction = 0;
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if (activeThreads.empty()) {
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_status = Idle;
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if (tickEvent.scheduled()) {
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deschedule(tickEvent);
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}
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}
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}
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Tick
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AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt)
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{
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DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(),
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pkt->cmdString());
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// X86 ISA: Snooping an invalidation for monitor/mwait
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AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner);
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for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
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if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
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cpu->wakeup(tid);
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}
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}
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// if snoop invalidates, release any associated locks
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// When run without caches, Invalidation packets will not be received
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// hence we must check if the incoming packets are writes and wakeup
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// the processor accordingly
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if (pkt->isInvalidate() || pkt->isWrite()) {
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DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n",
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pkt->getAddr());
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for (auto &t_info : cpu->threadInfo) {
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TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask);
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}
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}
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return 0;
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}
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void
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AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt)
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{
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DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(),
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pkt->cmdString());
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// X86 ISA: Snooping an invalidation for monitor/mwait
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AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner);
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for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
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if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
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cpu->wakeup(tid);
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}
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}
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// if snoop invalidates, release any associated locks
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if (pkt->isInvalidate()) {
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DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n",
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pkt->getAddr());
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for (auto &t_info : cpu->threadInfo) {
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TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask);
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}
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}
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}
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Fault
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AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
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unsigned size, unsigned flags)
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{
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SimpleExecContext& t_info = *threadInfo[curThread];
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SimpleThread* thread = t_info.thread;
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// use the CPU's statically allocated read request and packet objects
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Request *req = &data_read_req;
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if (traceData)
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traceData->setMem(addr, size, flags);
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//The size of the data we're trying to read.
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int fullSize = size;
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//The address of the second part of this access if it needs to be split
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//across a cache line boundary.
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Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
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if (secondAddr > addr)
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size = secondAddr - addr;
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dcache_latency = 0;
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req->taskId(taskId());
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while (1) {
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req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr());
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// translate to physical address
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Fault fault = thread->dtb->translateAtomic(req, thread->getTC(),
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BaseTLB::Read);
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// Now do the access.
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if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
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Packet pkt(req, Packet::makeReadCmd(req));
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pkt.dataStatic(data);
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if (req->isMmappedIpr())
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dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
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else {
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if (fastmem && system->isMemAddr(pkt.getAddr()))
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system->getPhysMem().access(&pkt);
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else
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dcache_latency += dcachePort.sendAtomic(&pkt);
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}
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dcache_access = true;
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assert(!pkt.isError());
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if (req->isLLSC()) {
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TheISA::handleLockedRead(thread, req);
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}
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}
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//If there's a fault, return it
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if (fault != NoFault) {
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if (req->isPrefetch()) {
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return NoFault;
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} else {
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return fault;
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}
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}
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//If we don't need to access a second cache line, stop now.
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if (secondAddr <= addr)
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{
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if (req->isLockedRMW() && fault == NoFault) {
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assert(!locked);
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locked = true;
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}
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return fault;
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}
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/*
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* Set up for accessing the second cache line.
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*/
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//Move the pointer we're reading into to the correct location.
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data += size;
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//Adjust the size to get the remaining bytes.
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size = addr + fullSize - secondAddr;
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//And access the right address.
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addr = secondAddr;
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}
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}
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Fault
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AtomicSimpleCPU::initiateMemRead(Addr addr, unsigned size, unsigned flags)
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{
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panic("initiateMemRead() is for timing accesses, and should "
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"never be called on AtomicSimpleCPU.\n");
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}
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Fault
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AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size,
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Addr addr, unsigned flags, uint64_t *res)
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{
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SimpleExecContext& t_info = *threadInfo[curThread];
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SimpleThread* thread = t_info.thread;
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static uint8_t zero_array[64] = {};
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if (data == NULL) {
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assert(size <= 64);
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assert(flags & Request::CACHE_BLOCK_ZERO);
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// This must be a cache block cleaning request
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data = zero_array;
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}
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// use the CPU's statically allocated write request and packet objects
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Request *req = &data_write_req;
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if (traceData)
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traceData->setMem(addr, size, flags);
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//The size of the data we're trying to read.
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int fullSize = size;
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//The address of the second part of this access if it needs to be split
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//across a cache line boundary.
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Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
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if (secondAddr > addr)
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size = secondAddr - addr;
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dcache_latency = 0;
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req->taskId(taskId());
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while (1) {
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req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr());
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// translate to physical address
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Fault fault = thread->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write);
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// Now do the access.
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if (fault == NoFault) {
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MemCmd cmd = MemCmd::WriteReq; // default
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bool do_access = true; // flag to suppress cache access
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if (req->isLLSC()) {
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cmd = MemCmd::StoreCondReq;
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do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask);
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} else if (req->isSwap()) {
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cmd = MemCmd::SwapReq;
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if (req->isCondSwap()) {
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assert(res);
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req->setExtraData(*res);
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}
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}
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if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) {
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Packet pkt = Packet(req, cmd);
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pkt.dataStatic(data);
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if (req->isMmappedIpr()) {
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dcache_latency +=
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TheISA::handleIprWrite(thread->getTC(), &pkt);
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} else {
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if (fastmem && system->isMemAddr(pkt.getAddr()))
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system->getPhysMem().access(&pkt);
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else
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dcache_latency += dcachePort.sendAtomic(&pkt);
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// Notify other threads on this CPU of write
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threadSnoop(&pkt, curThread);
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}
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dcache_access = true;
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assert(!pkt.isError());
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if (req->isSwap()) {
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assert(res);
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memcpy(res, pkt.getConstPtr<uint8_t>(), fullSize);
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}
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}
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if (res && !req->isSwap()) {
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*res = req->getExtraData();
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}
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}
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//If there's a fault or we don't need to access a second cache line,
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//stop now.
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if (fault != NoFault || secondAddr <= addr)
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{
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if (req->isLockedRMW() && fault == NoFault) {
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assert(locked);
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locked = false;
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}
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if (fault != NoFault && req->isPrefetch()) {
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return NoFault;
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} else {
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return fault;
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}
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}
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/*
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* Set up for accessing the second cache line.
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*/
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//Move the pointer we're reading into to the correct location.
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data += size;
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//Adjust the size to get the remaining bytes.
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size = addr + fullSize - secondAddr;
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//And access the right address.
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addr = secondAddr;
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}
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}
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void
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AtomicSimpleCPU::tick()
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{
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DPRINTF(SimpleCPU, "Tick\n");
|
|
|
|
// Change thread if multi-threaded
|
|
swapActiveThread();
|
|
|
|
// Set memroy request ids to current thread
|
|
if (numThreads > 1) {
|
|
ContextID cid = threadContexts[curThread]->contextId();
|
|
|
|
ifetch_req.setContext(cid);
|
|
data_read_req.setContext(cid);
|
|
data_write_req.setContext(cid);
|
|
}
|
|
|
|
SimpleExecContext& t_info = *threadInfo[curThread];
|
|
SimpleThread* thread = t_info.thread;
|
|
|
|
Tick latency = 0;
|
|
|
|
for (int i = 0; i < width || locked; ++i) {
|
|
numCycles++;
|
|
ppCycles->notify(1);
|
|
|
|
if (!curStaticInst || !curStaticInst->isDelayedCommit()) {
|
|
checkForInterrupts();
|
|
checkPcEventQueue();
|
|
}
|
|
|
|
// We must have just got suspended by a PC event
|
|
if (_status == Idle) {
|
|
tryCompleteDrain();
|
|
return;
|
|
}
|
|
|
|
Fault fault = NoFault;
|
|
|
|
TheISA::PCState pcState = thread->pcState();
|
|
|
|
bool needToFetch = !isRomMicroPC(pcState.microPC()) &&
|
|
!curMacroStaticInst;
|
|
if (needToFetch) {
|
|
ifetch_req.taskId(taskId());
|
|
setupFetchRequest(&ifetch_req);
|
|
fault = thread->itb->translateAtomic(&ifetch_req, thread->getTC(),
|
|
BaseTLB::Execute);
|
|
}
|
|
|
|
if (fault == NoFault) {
|
|
Tick icache_latency = 0;
|
|
bool icache_access = false;
|
|
dcache_access = false; // assume no dcache access
|
|
|
|
if (needToFetch) {
|
|
// This is commented out because the decoder would act like
|
|
// a tiny cache otherwise. It wouldn't be flushed when needed
|
|
// like the I cache. It should be flushed, and when that works
|
|
// this code should be uncommented.
|
|
//Fetch more instruction memory if necessary
|
|
//if (decoder.needMoreBytes())
|
|
//{
|
|
icache_access = true;
|
|
Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq);
|
|
ifetch_pkt.dataStatic(&inst);
|
|
|
|
if (fastmem && system->isMemAddr(ifetch_pkt.getAddr()))
|
|
system->getPhysMem().access(&ifetch_pkt);
|
|
else
|
|
icache_latency = icachePort.sendAtomic(&ifetch_pkt);
|
|
|
|
assert(!ifetch_pkt.isError());
|
|
|
|
// ifetch_req is initialized to read the instruction directly
|
|
// into the CPU object's inst field.
|
|
//}
|
|
}
|
|
|
|
preExecute();
|
|
|
|
if (curStaticInst) {
|
|
fault = curStaticInst->execute(&t_info, traceData);
|
|
|
|
// keep an instruction count
|
|
if (fault == NoFault) {
|
|
countInst();
|
|
ppCommit->notify(std::make_pair(thread, curStaticInst));
|
|
}
|
|
else if (traceData && !DTRACE(ExecFaulting)) {
|
|
delete traceData;
|
|
traceData = NULL;
|
|
}
|
|
|
|
postExecute();
|
|
}
|
|
|
|
// @todo remove me after debugging with legion done
|
|
if (curStaticInst && (!curStaticInst->isMicroop() ||
|
|
curStaticInst->isFirstMicroop()))
|
|
instCnt++;
|
|
|
|
Tick stall_ticks = 0;
|
|
if (simulate_inst_stalls && icache_access)
|
|
stall_ticks += icache_latency;
|
|
|
|
if (simulate_data_stalls && dcache_access)
|
|
stall_ticks += dcache_latency;
|
|
|
|
if (stall_ticks) {
|
|
// the atomic cpu does its accounting in ticks, so
|
|
// keep counting in ticks but round to the clock
|
|
// period
|
|
latency += divCeil(stall_ticks, clockPeriod()) *
|
|
clockPeriod();
|
|
}
|
|
|
|
}
|
|
if (fault != NoFault || !t_info.stayAtPC)
|
|
advancePC(fault);
|
|
}
|
|
|
|
if (tryCompleteDrain())
|
|
return;
|
|
|
|
// instruction takes at least one cycle
|
|
if (latency < clockPeriod())
|
|
latency = clockPeriod();
|
|
|
|
if (_status != Idle)
|
|
reschedule(tickEvent, curTick() + latency, true);
|
|
}
|
|
|
|
void
|
|
AtomicSimpleCPU::regProbePoints()
|
|
{
|
|
BaseCPU::regProbePoints();
|
|
|
|
ppCommit = new ProbePointArg<pair<SimpleThread*, const StaticInstPtr>>
|
|
(getProbeManager(), "Commit");
|
|
}
|
|
|
|
void
|
|
AtomicSimpleCPU::printAddr(Addr a)
|
|
{
|
|
dcachePort.printAddr(a);
|
|
}
|
|
|
|
////////////////////////////////////////////////////////////////////////
|
|
//
|
|
// AtomicSimpleCPU Simulation Object
|
|
//
|
|
AtomicSimpleCPU *
|
|
AtomicSimpleCPUParams::create()
|
|
{
|
|
return new AtomicSimpleCPU(this);
|
|
}
|