d64b34bef8
This patch changes how the MMU and table walkers are created such that a single port is used to connect the MMU and the TLBs to the memory system. Previously two ports were needed as there are two table walker objects (stage one and stage two), and they both had a port. Now the port itself is moved to the Stage2MMU, and each TableWalker is simply using the port from the parent. By using the same port we also remove the need for having an additional crossbar joining the two ports before the walker cache or the L2. This simplifies the creation of the CPU cache topology in BaseCPU.py considerably. Moreover, for naming and symmetry reasons, the TLB walker port is connected through the stage-one table walker thus making the naming identical to x86. Along the same line, we use the stage-one table walker to generate the master id that is used by all TLB-related requests.
977 lines
29 KiB
C++
977 lines
29 KiB
C++
/*
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* Copyright (c) 2010-2015 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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* Giacomo Gabrielli
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*/
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#ifndef __ARCH_ARM_TABLE_WALKER_HH__
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#define __ARCH_ARM_TABLE_WALKER_HH__
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#include <list>
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#include "arch/arm/miscregs.hh"
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#include "arch/arm/system.hh"
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#include "arch/arm/tlb.hh"
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#include "dev/dma_device.hh"
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#include "mem/request.hh"
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#include "params/ArmTableWalker.hh"
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#include "sim/eventq.hh"
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class ThreadContext;
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namespace ArmISA {
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class Translation;
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class TLB;
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class Stage2MMU;
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class TableWalker : public MemObject
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{
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public:
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class WalkerState;
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class DescriptorBase {
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public:
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/** Current lookup level for this descriptor */
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LookupLevel lookupLevel;
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virtual Addr pfn() const = 0;
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virtual TlbEntry::DomainType domain() const = 0;
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virtual bool xn() const = 0;
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virtual uint8_t ap() const = 0;
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virtual bool global(WalkerState *currState) const = 0;
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virtual uint8_t offsetBits() const = 0;
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virtual bool secure(bool have_security, WalkerState *currState) const = 0;
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virtual std::string dbgHeader() const = 0;
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virtual uint64_t getRawData() const = 0;
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virtual uint8_t texcb() const
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{
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panic("texcb() not implemented for this class\n");
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}
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virtual bool shareable() const
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{
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panic("shareable() not implemented for this class\n");
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}
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};
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class L1Descriptor : public DescriptorBase {
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public:
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/** Type of page table entry ARM DDI 0406B: B3-8*/
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enum EntryType {
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Ignore,
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PageTable,
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Section,
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Reserved
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};
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/** The raw bits of the entry */
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uint32_t data;
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/** This entry has been modified (access flag set) and needs to be
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* written back to memory */
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bool _dirty;
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/** Default ctor */
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L1Descriptor() : data(0), _dirty(false)
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{
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lookupLevel = L1;
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}
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virtual uint64_t getRawData() const
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{
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return (data);
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}
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virtual std::string dbgHeader() const
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{
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return "Inserting Section Descriptor into TLB\n";
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}
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virtual uint8_t offsetBits() const
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{
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return 20;
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}
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EntryType type() const
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{
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return (EntryType)(data & 0x3);
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}
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/** Is the page a Supersection (16MB)?*/
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bool supersection() const
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{
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return bits(data, 18);
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}
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/** Return the physcal address of the entry, bits in position*/
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Addr paddr() const
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{
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if (supersection())
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panic("Super sections not implemented\n");
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return mbits(data, 31, 20);
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}
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/** Return the physcal address of the entry, bits in position*/
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Addr paddr(Addr va) const
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{
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if (supersection())
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panic("Super sections not implemented\n");
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return mbits(data, 31, 20) | mbits(va, 19, 0);
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}
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/** Return the physical frame, bits shifted right */
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Addr pfn() const
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{
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if (supersection())
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panic("Super sections not implemented\n");
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return bits(data, 31, 20);
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}
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/** Is the translation global (no asid used)? */
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bool global(WalkerState *currState) const
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{
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return !bits(data, 17);
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}
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/** Is the translation not allow execution? */
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bool xn() const
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{
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return bits(data, 4);
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}
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/** Three bit access protection flags */
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uint8_t ap() const
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{
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return (bits(data, 15) << 2) | bits(data, 11, 10);
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}
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/** Domain Client/Manager: ARM DDI 0406B: B3-31 */
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TlbEntry::DomainType domain() const
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{
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return static_cast<TlbEntry::DomainType>(bits(data, 8, 5));
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}
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/** Address of L2 descriptor if it exists */
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Addr l2Addr() const
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{
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return mbits(data, 31, 10);
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}
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/** Memory region attributes: ARM DDI 0406B: B3-32.
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* These bits are largly ignored by M5 and only used to
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* provide the illusion that the memory system cares about
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* anything but cachable vs. uncachable.
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*/
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uint8_t texcb() const
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{
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return bits(data, 2) | bits(data, 3) << 1 | bits(data, 14, 12) << 2;
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}
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/** If the section is shareable. See texcb() comment. */
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bool shareable() const
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{
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return bits(data, 16);
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}
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/** Set access flag that this entry has been touched. Mark
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* the entry as requiring a writeback, in the future.
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*/
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void setAp0()
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{
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data |= 1 << 10;
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_dirty = true;
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}
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/** This entry needs to be written back to memory */
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bool dirty() const
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{
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return _dirty;
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}
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/**
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* Returns true if this entry targets the secure physical address
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* map.
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*/
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bool secure(bool have_security, WalkerState *currState) const
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{
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if (have_security) {
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if (type() == PageTable)
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return !bits(data, 3);
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else
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return !bits(data, 19);
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}
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return false;
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}
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};
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/** Level 2 page table descriptor */
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class L2Descriptor : public DescriptorBase {
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public:
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/** The raw bits of the entry. */
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uint32_t data;
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L1Descriptor *l1Parent;
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/** This entry has been modified (access flag set) and needs to be
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* written back to memory */
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bool _dirty;
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/** Default ctor */
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L2Descriptor() : data(0), l1Parent(nullptr), _dirty(false)
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{
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lookupLevel = L2;
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}
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L2Descriptor(L1Descriptor &parent) : data(0), l1Parent(&parent),
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_dirty(false)
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{
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lookupLevel = L2;
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}
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virtual uint64_t getRawData() const
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{
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return (data);
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}
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virtual std::string dbgHeader() const
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{
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return "Inserting L2 Descriptor into TLB\n";
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}
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virtual TlbEntry::DomainType domain() const
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{
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return l1Parent->domain();
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}
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bool secure(bool have_security, WalkerState *currState) const
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{
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return l1Parent->secure(have_security, currState);
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}
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virtual uint8_t offsetBits() const
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{
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return large() ? 16 : 12;
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}
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/** Is the entry invalid */
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bool invalid() const
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{
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return bits(data, 1, 0) == 0;
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}
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/** What is the size of the mapping? */
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bool large() const
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{
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return bits(data, 1) == 0;
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}
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/** Is execution allowed on this mapping? */
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bool xn() const
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{
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return large() ? bits(data, 15) : bits(data, 0);
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}
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/** Is the translation global (no asid used)? */
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bool global(WalkerState *currState) const
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{
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return !bits(data, 11);
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}
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/** Three bit access protection flags */
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uint8_t ap() const
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{
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return bits(data, 5, 4) | (bits(data, 9) << 2);
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}
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/** Memory region attributes: ARM DDI 0406B: B3-32 */
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uint8_t texcb() const
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{
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return large() ?
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(bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 14, 12) << 2)) :
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(bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 8, 6) << 2));
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}
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/** Return the physical frame, bits shifted right */
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Addr pfn() const
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{
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return large() ? bits(data, 31, 16) : bits(data, 31, 12);
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}
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/** Return complete physical address given a VA */
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Addr paddr(Addr va) const
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{
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if (large())
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return mbits(data, 31, 16) | mbits(va, 15, 0);
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else
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return mbits(data, 31, 12) | mbits(va, 11, 0);
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}
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/** If the section is shareable. See texcb() comment. */
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bool shareable() const
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{
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return bits(data, 10);
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}
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/** Set access flag that this entry has been touched. Mark
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* the entry as requiring a writeback, in the future.
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*/
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void setAp0()
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{
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data |= 1 << 4;
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_dirty = true;
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}
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/** This entry needs to be written back to memory */
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bool dirty() const
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{
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return _dirty;
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}
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};
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// Granule sizes for AArch64 long descriptors
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enum GrainSize {
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Grain4KB = 12,
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Grain16KB = 14,
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Grain64KB = 16,
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ReservedGrain = 0
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};
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/** Long-descriptor format (LPAE) */
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class LongDescriptor : public DescriptorBase {
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public:
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/** Descriptor type */
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enum EntryType {
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Invalid,
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Table,
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Block,
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Page
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};
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/** The raw bits of the entry */
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uint64_t data;
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/** This entry has been modified (access flag set) and needs to be
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* written back to memory */
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bool _dirty;
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virtual uint64_t getRawData() const
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{
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return (data);
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}
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virtual std::string dbgHeader() const
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{
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if (type() == LongDescriptor::Page) {
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assert(lookupLevel == L3);
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return "Inserting Page descriptor into TLB\n";
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} else {
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assert(lookupLevel < L3);
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return "Inserting Block descriptor into TLB\n";
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}
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}
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/**
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* Returns true if this entry targets the secure physical address
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* map.
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*/
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bool secure(bool have_security, WalkerState *currState) const
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{
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assert(type() == Block || type() == Page);
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return have_security && (currState->secureLookup && !bits(data, 5));
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}
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/** True if the current lookup is performed in AArch64 state */
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bool aarch64;
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/** Width of the granule size in bits */
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GrainSize grainSize;
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/** Return the descriptor type */
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EntryType type() const
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{
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switch (bits(data, 1, 0)) {
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case 0x1:
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// In AArch64 blocks are not allowed at L0 for the 4 KB granule
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// and at L1 for 16/64 KB granules
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if (grainSize > Grain4KB)
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return lookupLevel == L2 ? Block : Invalid;
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return lookupLevel == L0 || lookupLevel == L3 ? Invalid : Block;
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case 0x3:
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return lookupLevel == L3 ? Page : Table;
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default:
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return Invalid;
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}
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}
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/** Return the bit width of the page/block offset */
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uint8_t offsetBits() const
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{
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if (type() == Block) {
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switch (grainSize) {
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case Grain4KB:
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return lookupLevel == L1 ? 30 /* 1 GB */
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: 21 /* 2 MB */;
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case Grain16KB:
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return 25 /* 32 MB */;
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case Grain64KB:
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return 29 /* 512 MB */;
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default:
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panic("Invalid AArch64 VM granule size\n");
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}
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} else if (type() == Page) {
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switch (grainSize) {
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case Grain4KB:
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case Grain16KB:
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case Grain64KB:
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return grainSize; /* enum -> uint okay */
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default:
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panic("Invalid AArch64 VM granule size\n");
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}
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} else {
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panic("AArch64 page table entry must be block or page\n");
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}
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}
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/** Return the physical frame, bits shifted right */
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Addr pfn() const
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{
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if (aarch64)
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return bits(data, 47, offsetBits());
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return bits(data, 39, offsetBits());
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}
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/** Return the complete physical address given a VA */
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Addr paddr(Addr va) const
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{
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int n = offsetBits();
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if (aarch64)
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return mbits(data, 47, n) | mbits(va, n - 1, 0);
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return mbits(data, 39, n) | mbits(va, n - 1, 0);
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}
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/** Return the physical address of the entry */
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Addr paddr() const
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{
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if (aarch64)
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return mbits(data, 47, offsetBits());
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return mbits(data, 39, offsetBits());
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}
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/** Return the address of the next page table */
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Addr nextTableAddr() const
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{
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assert(type() == Table);
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if (aarch64)
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return mbits(data, 47, grainSize);
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else
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return mbits(data, 39, 12);
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}
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/** Return the address of the next descriptor */
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Addr nextDescAddr(Addr va) const
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{
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assert(type() == Table);
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Addr pa = 0;
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if (aarch64) {
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int stride = grainSize - 3;
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int va_lo = stride * (3 - (lookupLevel + 1)) + grainSize;
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int va_hi = va_lo + stride - 1;
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pa = nextTableAddr() | (bits(va, va_hi, va_lo) << 3);
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} else {
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if (lookupLevel == L1)
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pa = nextTableAddr() | (bits(va, 29, 21) << 3);
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else // lookupLevel == L2
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pa = nextTableAddr() | (bits(va, 20, 12) << 3);
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}
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return pa;
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}
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/** Is execution allowed on this mapping? */
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bool xn() const
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{
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assert(type() == Block || type() == Page);
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return bits(data, 54);
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}
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/** Is privileged execution allowed on this mapping? (LPAE only) */
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bool pxn() const
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{
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assert(type() == Block || type() == Page);
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return bits(data, 53);
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}
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|
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/** Contiguous hint bit. */
|
|
bool contiguousHint() const
|
|
{
|
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assert(type() == Block || type() == Page);
|
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return bits(data, 52);
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}
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/** Is the translation global (no asid used)? */
|
|
bool global(WalkerState *currState) const
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{
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assert(currState && (type() == Block || type() == Page));
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if (!currState->aarch64 && (currState->isSecure &&
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!currState->secureLookup)) {
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return false; // ARM ARM issue C B3.6.3
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} else if (currState->aarch64) {
|
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if (currState->el == EL2 || currState->el == EL3) {
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return true; // By default translations are treated as global
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// in AArch64 EL2 and EL3
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|
} else if (currState->isSecure && !currState->secureLookup) {
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return false;
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}
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}
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return !bits(data, 11);
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}
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|
|
/** Returns true if the access flag (AF) is set. */
|
|
bool af() const
|
|
{
|
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assert(type() == Block || type() == Page);
|
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return bits(data, 10);
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}
|
|
|
|
/** 2-bit shareability field */
|
|
uint8_t sh() const
|
|
{
|
|
assert(type() == Block || type() == Page);
|
|
return bits(data, 9, 8);
|
|
}
|
|
|
|
/** 2-bit access protection flags */
|
|
uint8_t ap() const
|
|
{
|
|
assert(type() == Block || type() == Page);
|
|
// Long descriptors only support the AP[2:1] scheme
|
|
return bits(data, 7, 6);
|
|
}
|
|
|
|
/** Read/write access protection flag */
|
|
bool rw() const
|
|
{
|
|
assert(type() == Block || type() == Page);
|
|
return !bits(data, 7);
|
|
}
|
|
|
|
/** User/privileged level access protection flag */
|
|
bool user() const
|
|
{
|
|
assert(type() == Block || type() == Page);
|
|
return bits(data, 6);
|
|
}
|
|
|
|
/** Return the AP bits as compatible with the AP[2:0] format. Utility
|
|
* function used to simplify the code in the TLB for performing
|
|
* permission checks. */
|
|
static uint8_t ap(bool rw, bool user)
|
|
{
|
|
return ((!rw) << 2) | (user << 1);
|
|
}
|
|
|
|
TlbEntry::DomainType domain() const
|
|
{
|
|
// Long-desc. format only supports Client domain
|
|
assert(type() == Block || type() == Page);
|
|
return TlbEntry::DomainType::Client;
|
|
}
|
|
|
|
/** Attribute index */
|
|
uint8_t attrIndx() const
|
|
{
|
|
assert(type() == Block || type() == Page);
|
|
return bits(data, 4, 2);
|
|
}
|
|
|
|
/** Memory attributes, only used by stage 2 translations */
|
|
uint8_t memAttr() const
|
|
{
|
|
assert(type() == Block || type() == Page);
|
|
return bits(data, 5, 2);
|
|
}
|
|
|
|
/** Set access flag that this entry has been touched. Mark the entry as
|
|
* requiring a writeback, in the future. */
|
|
void setAf()
|
|
{
|
|
data |= 1 << 10;
|
|
_dirty = true;
|
|
}
|
|
|
|
/** This entry needs to be written back to memory */
|
|
bool dirty() const
|
|
{
|
|
return _dirty;
|
|
}
|
|
|
|
/** Whether the subsequent levels of lookup are secure */
|
|
bool secureTable() const
|
|
{
|
|
assert(type() == Table);
|
|
return !bits(data, 63);
|
|
}
|
|
|
|
/** Two bit access protection flags for subsequent levels of lookup */
|
|
uint8_t apTable() const
|
|
{
|
|
assert(type() == Table);
|
|
return bits(data, 62, 61);
|
|
}
|
|
|
|
/** R/W protection flag for subsequent levels of lookup */
|
|
uint8_t rwTable() const
|
|
{
|
|
assert(type() == Table);
|
|
return !bits(data, 62);
|
|
}
|
|
|
|
/** User/privileged mode protection flag for subsequent levels of
|
|
* lookup */
|
|
uint8_t userTable() const
|
|
{
|
|
assert(type() == Table);
|
|
return !bits(data, 61);
|
|
}
|
|
|
|
/** Is execution allowed on subsequent lookup levels? */
|
|
bool xnTable() const
|
|
{
|
|
assert(type() == Table);
|
|
return bits(data, 60);
|
|
}
|
|
|
|
/** Is privileged execution allowed on subsequent lookup levels? */
|
|
bool pxnTable() const
|
|
{
|
|
assert(type() == Table);
|
|
return bits(data, 59);
|
|
}
|
|
};
|
|
|
|
class WalkerState
|
|
{
|
|
public:
|
|
/** Thread context that we're doing the walk for */
|
|
ThreadContext *tc;
|
|
|
|
/** If the access is performed in AArch64 state */
|
|
bool aarch64;
|
|
|
|
/** Current exception level */
|
|
ExceptionLevel el;
|
|
|
|
/** Current physical address range in bits */
|
|
int physAddrRange;
|
|
|
|
/** Request that is currently being serviced */
|
|
RequestPtr req;
|
|
|
|
/** ASID that we're servicing the request under */
|
|
uint16_t asid;
|
|
uint8_t vmid;
|
|
bool isHyp;
|
|
|
|
/** Translation state for delayed requests */
|
|
TLB::Translation *transState;
|
|
|
|
/** The fault that we are going to return */
|
|
Fault fault;
|
|
|
|
/** The virtual address that is being translated with tagging removed.*/
|
|
Addr vaddr;
|
|
|
|
/** The virtual address that is being translated */
|
|
Addr vaddr_tainted;
|
|
|
|
/** Cached copy of the sctlr as it existed when translation began */
|
|
SCTLR sctlr;
|
|
|
|
/** Cached copy of the scr as it existed when translation began */
|
|
SCR scr;
|
|
|
|
/** Cached copy of the cpsr as it existed when translation began */
|
|
CPSR cpsr;
|
|
|
|
/** Cached copy of ttbcr/tcr as it existed when translation began */
|
|
union {
|
|
TTBCR ttbcr; // AArch32 translations
|
|
TCR tcr; // AArch64 translations
|
|
};
|
|
|
|
/** Cached copy of the htcr as it existed when translation began. */
|
|
HTCR htcr;
|
|
|
|
/** Cached copy of the htcr as it existed when translation began. */
|
|
HCR hcr;
|
|
|
|
/** Cached copy of the vtcr as it existed when translation began. */
|
|
VTCR_t vtcr;
|
|
|
|
/** If the access is a write */
|
|
bool isWrite;
|
|
|
|
/** If the access is a fetch (for execution, and no-exec) must be checked?*/
|
|
bool isFetch;
|
|
|
|
/** If the access comes from the secure state. */
|
|
bool isSecure;
|
|
|
|
/** Helper variables used to implement hierarchical access permissions
|
|
* when the long-desc. format is used (LPAE only) */
|
|
bool secureLookup;
|
|
bool rwTable;
|
|
bool userTable;
|
|
bool xnTable;
|
|
bool pxnTable;
|
|
|
|
/** Flag indicating if a second stage of lookup is required */
|
|
bool stage2Req;
|
|
|
|
/** Indicates whether the translation has been passed onto the second
|
|
* stage mmu, and no more work is required from the first stage.
|
|
*/
|
|
bool doingStage2;
|
|
|
|
/** A pointer to the stage 2 translation that's in progress */
|
|
TLB::Translation *stage2Tran;
|
|
|
|
/** If the mode is timing or atomic */
|
|
bool timing;
|
|
|
|
/** If the atomic mode should be functional */
|
|
bool functional;
|
|
|
|
/** Save mode for use in delayed response */
|
|
BaseTLB::Mode mode;
|
|
|
|
/** The translation type that has been requested */
|
|
TLB::ArmTranslationType tranType;
|
|
|
|
/** Short-format descriptors */
|
|
L1Descriptor l1Desc;
|
|
L2Descriptor l2Desc;
|
|
|
|
/** Long-format descriptor (LPAE and AArch64) */
|
|
LongDescriptor longDesc;
|
|
|
|
/** Whether the response is delayed in timing mode due to additional
|
|
* lookups */
|
|
bool delayed;
|
|
|
|
TableWalker *tableWalker;
|
|
|
|
/** Timestamp for calculating elapsed time in service (for stats) */
|
|
Tick startTime;
|
|
|
|
/** Page entries walked during service (for stats) */
|
|
unsigned levels;
|
|
|
|
void doL1Descriptor();
|
|
void doL2Descriptor();
|
|
|
|
void doLongDescriptor();
|
|
|
|
WalkerState();
|
|
|
|
std::string name() const { return tableWalker->name(); }
|
|
};
|
|
|
|
protected:
|
|
|
|
/** Queues of requests for all the different lookup levels */
|
|
std::list<WalkerState *> stateQueues[MAX_LOOKUP_LEVELS];
|
|
|
|
/** Queue of requests that have passed are waiting because the walker is
|
|
* currently busy. */
|
|
std::list<WalkerState *> pendingQueue;
|
|
|
|
/** If we're draining keep the drain event around until we're drained */
|
|
DrainManager *drainManager;
|
|
|
|
/** The MMU to forward second stage look upts to */
|
|
Stage2MMU *stage2Mmu;
|
|
|
|
/** Port shared by the two table walkers. */
|
|
DmaPort* port;
|
|
|
|
/** Master id assigned by the MMU. */
|
|
MasterID masterId;
|
|
|
|
/** Indicates whether this table walker is part of the stage 2 mmu */
|
|
const bool isStage2;
|
|
|
|
/** TLB that is initiating these table walks */
|
|
TLB *tlb;
|
|
|
|
/** Cached copy of the sctlr as it existed when translation began */
|
|
SCTLR sctlr;
|
|
|
|
WalkerState *currState;
|
|
|
|
/** If a timing translation is currently in progress */
|
|
bool pending;
|
|
|
|
/** The number of walks belonging to squashed instructions that can be
|
|
* removed from the pendingQueue per cycle. */
|
|
unsigned numSquashable;
|
|
|
|
/** Cached copies of system-level properties */
|
|
bool haveSecurity;
|
|
bool _haveLPAE;
|
|
bool _haveVirtualization;
|
|
uint8_t physAddrRange;
|
|
bool _haveLargeAsid64;
|
|
|
|
/** Statistics */
|
|
Stats::Scalar statWalks;
|
|
Stats::Scalar statWalksShortDescriptor;
|
|
Stats::Scalar statWalksLongDescriptor;
|
|
Stats::Vector statWalksShortTerminatedAtLevel;
|
|
Stats::Vector statWalksLongTerminatedAtLevel;
|
|
Stats::Scalar statSquashedBefore;
|
|
Stats::Scalar statSquashedAfter;
|
|
Stats::Histogram statWalkWaitTime;
|
|
Stats::Histogram statWalkServiceTime;
|
|
Stats::Histogram statPendingWalks; // essentially "L" of queueing theory
|
|
Stats::Vector statPageSizes;
|
|
Stats::Vector2d statRequestOrigin;
|
|
|
|
mutable unsigned pendingReqs;
|
|
mutable Tick pendingChangeTick;
|
|
|
|
static const unsigned REQUESTED = 0;
|
|
static const unsigned COMPLETED = 1;
|
|
|
|
public:
|
|
typedef ArmTableWalkerParams Params;
|
|
TableWalker(const Params *p);
|
|
virtual ~TableWalker();
|
|
|
|
const Params *
|
|
params() const
|
|
{
|
|
return dynamic_cast<const Params *>(_params);
|
|
}
|
|
|
|
virtual void init();
|
|
|
|
bool haveLPAE() const { return _haveLPAE; }
|
|
bool haveVirtualization() const { return _haveVirtualization; }
|
|
bool haveLargeAsid64() const { return _haveLargeAsid64; }
|
|
/** Checks if all state is cleared and if so, completes drain */
|
|
void completeDrain();
|
|
unsigned int drain(DrainManager *dm);
|
|
virtual void drainResume();
|
|
|
|
virtual BaseMasterPort& getMasterPort(const std::string &if_name,
|
|
PortID idx = InvalidPortID);
|
|
|
|
void regStats();
|
|
|
|
Fault walk(RequestPtr req, ThreadContext *tc, uint16_t asid, uint8_t _vmid,
|
|
bool _isHyp, TLB::Mode mode, TLB::Translation *_trans,
|
|
bool timing, bool functional, bool secure,
|
|
TLB::ArmTranslationType tranType);
|
|
|
|
void setTlb(TLB *_tlb) { tlb = _tlb; }
|
|
TLB* getTlb() { return tlb; }
|
|
void setMMU(Stage2MMU *m, MasterID master_id);
|
|
void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
|
|
uint8_t texcb, bool s);
|
|
void memAttrsLPAE(ThreadContext *tc, TlbEntry &te,
|
|
LongDescriptor &lDescriptor);
|
|
void memAttrsAArch64(ThreadContext *tc, TlbEntry &te, uint8_t attrIndx,
|
|
uint8_t sh);
|
|
|
|
static LookupLevel toLookupLevel(uint8_t lookup_level_as_int);
|
|
|
|
private:
|
|
|
|
void doL1Descriptor();
|
|
void doL1DescriptorWrapper();
|
|
EventWrapper<TableWalker,
|
|
&TableWalker::doL1DescriptorWrapper> doL1DescEvent;
|
|
|
|
void doL2Descriptor();
|
|
void doL2DescriptorWrapper();
|
|
EventWrapper<TableWalker,
|
|
&TableWalker::doL2DescriptorWrapper> doL2DescEvent;
|
|
|
|
void doLongDescriptor();
|
|
|
|
void doL0LongDescriptorWrapper();
|
|
EventWrapper<TableWalker,
|
|
&TableWalker::doL0LongDescriptorWrapper> doL0LongDescEvent;
|
|
void doL1LongDescriptorWrapper();
|
|
EventWrapper<TableWalker,
|
|
&TableWalker::doL1LongDescriptorWrapper> doL1LongDescEvent;
|
|
void doL2LongDescriptorWrapper();
|
|
EventWrapper<TableWalker,
|
|
&TableWalker::doL2LongDescriptorWrapper> doL2LongDescEvent;
|
|
void doL3LongDescriptorWrapper();
|
|
EventWrapper<TableWalker,
|
|
&TableWalker::doL3LongDescriptorWrapper> doL3LongDescEvent;
|
|
|
|
void doLongDescriptorWrapper(LookupLevel curr_lookup_level);
|
|
|
|
bool fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes,
|
|
Request::Flags flags, int queueIndex, Event *event,
|
|
void (TableWalker::*doDescriptor)());
|
|
|
|
void insertTableEntry(DescriptorBase &descriptor, bool longDescriptor);
|
|
|
|
Fault processWalk();
|
|
Fault processWalkLPAE();
|
|
static unsigned adjustTableSizeAArch64(unsigned tsz);
|
|
/// Returns true if the address exceeds the range permitted by the
|
|
/// system-wide setting or by the TCR_ELx IPS/PS setting
|
|
static bool checkAddrSizeFaultAArch64(Addr addr, int currPhysAddrRange);
|
|
Fault processWalkAArch64();
|
|
void processWalkWrapper();
|
|
EventWrapper<TableWalker, &TableWalker::processWalkWrapper> doProcessEvent;
|
|
|
|
void nextWalk(ThreadContext *tc);
|
|
|
|
void pendingChange();
|
|
|
|
static uint8_t pageSizeNtoStatBin(uint8_t N);
|
|
};
|
|
|
|
} // namespace ArmISA
|
|
|
|
#endif //__ARCH_ARM_TABLE_WALKER_HH__
|
|
|