Ali Saidi c5fbbf376a Change everything to use the cached virtPort rather than created their own each time. ... This appears to work, but I don't want to commit it until it gets tested a lot more. I haven't deleted the functionality in this patch that will come later, but one question is how to enforce encourage objects that call getVirtPort() to not cache the virtual port since if the CPU changes out from under them it will be worse than useless. Perhaps a null function like delVirtPort() is still useful in that case.		2008-07-01 10:24:19 -04:00
..
alpha	Change everything to use the cached virtPort rather than created their own each time.	2008-07-01 10:24:19 -04:00
mips	Change everything to use the cached virtPort rather than created their own each time.	2008-07-01 10:24:19 -04:00
sparc	Change everything to use the cached virtPort rather than created their own each time.	2008-07-01 10:24:19 -04:00
x86	Fix various SWIG warnings	2008-06-14 12:57:21 -07:00
isa_parser.py	Get MIPS simple regression working. Take out unecessary functions "setShadowSet", "CacheOp"	2007-11-15 03:10:41 -05:00
isa_specific.hh	Add base ARM code to M5	2008-02-05 23:44:13 -05:00
micro_asm.py	Microassembler: Pass the actual mnemonic used to the macroop add_micro function	2007-08-31 22:26:02 -07:00
micro_asm_test.py	Add a second section to make sure the ROM is extended properly.	2007-05-31 22:21:21 +00:00
SConscript	ISA parser: Make the isa parser generate MaxInstSrcRegs and MaxInstDestRegs.	2007-11-08 18:51:50 -08:00