c5dcd152f2
SConscript:
Changed all of the "targetarch" files to be "arch" files
arch/SConscript:
Added all of the remaining targetarch files to isa_switch_hdrs
--HG--
extra : convert_revision : a37d18349e27cf92dce12814f21944daa7fe9480
393 lines
13 KiB
C++
393 lines
13 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "base/inifile.hh"
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#include "base/loader/symtab.hh"
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#include "base/misc.hh"
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#include "cpu/base.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/o3/alpha_cpu.hh"
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#include "cpu/o3/alpha_impl.hh"
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#include "mem/base_mem.hh"
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#include "mem/cache/base_cache.hh"
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#include "mem/mem_interface.hh"
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#include "sim/builder.hh"
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#include "sim/debug.hh"
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#include "sim/host.hh"
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#include "sim/process.hh"
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#include "sim/sim_events.hh"
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#include "sim/sim_object.hh"
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#include "sim/stats.hh"
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#if FULL_SYSTEM
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#include "base/remote_gdb.hh"
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#include "mem/functional/memory_control.hh"
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#include "mem/functional/physical.hh"
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#include "sim/system.hh"
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#include "arch/alpha_memory.hh"
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#include "arch/vtophys.hh"
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#else // !FULL_SYSTEM
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#include "mem/functional/functional.hh"
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#endif // FULL_SYSTEM
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class DerivAlphaFullCPU : public AlphaFullCPU<AlphaSimpleImpl>
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{
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public:
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DerivAlphaFullCPU(AlphaSimpleParams p)
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: AlphaFullCPU<AlphaSimpleImpl>(p)
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{ }
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};
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
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Param<int> clock;
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Param<int> numThreads;
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#if FULL_SYSTEM
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SimObjectParam<System *> system;
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Param<int> cpu_id;
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SimObjectParam<AlphaITB *> itb;
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SimObjectParam<AlphaDTB *> dtb;
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#else
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SimObjectVectorParam<Process *> workload;
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#endif // FULL_SYSTEM
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SimObjectParam<FunctionalMemory *> mem;
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Param<Counter> max_insts_any_thread;
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Param<Counter> max_insts_all_threads;
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Param<Counter> max_loads_any_thread;
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Param<Counter> max_loads_all_threads;
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SimObjectParam<BaseCache *> icache;
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SimObjectParam<BaseCache *> dcache;
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Param<unsigned> decodeToFetchDelay;
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Param<unsigned> renameToFetchDelay;
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Param<unsigned> iewToFetchDelay;
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Param<unsigned> commitToFetchDelay;
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Param<unsigned> fetchWidth;
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Param<unsigned> renameToDecodeDelay;
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Param<unsigned> iewToDecodeDelay;
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Param<unsigned> commitToDecodeDelay;
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Param<unsigned> fetchToDecodeDelay;
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Param<unsigned> decodeWidth;
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Param<unsigned> iewToRenameDelay;
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Param<unsigned> commitToRenameDelay;
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Param<unsigned> decodeToRenameDelay;
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Param<unsigned> renameWidth;
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Param<unsigned> commitToIEWDelay;
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Param<unsigned> renameToIEWDelay;
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Param<unsigned> issueToExecuteDelay;
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Param<unsigned> issueWidth;
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Param<unsigned> executeWidth;
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Param<unsigned> executeIntWidth;
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Param<unsigned> executeFloatWidth;
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Param<unsigned> executeBranchWidth;
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Param<unsigned> executeMemoryWidth;
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Param<unsigned> iewToCommitDelay;
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Param<unsigned> renameToROBDelay;
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Param<unsigned> commitWidth;
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Param<unsigned> squashWidth;
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#if 0
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Param<unsigned> localPredictorSize;
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Param<unsigned> localPredictorCtrBits;
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#endif
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Param<unsigned> local_predictor_size;
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Param<unsigned> local_ctr_bits;
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Param<unsigned> local_history_table_size;
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Param<unsigned> local_history_bits;
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Param<unsigned> global_predictor_size;
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Param<unsigned> global_ctr_bits;
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Param<unsigned> global_history_bits;
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Param<unsigned> choice_predictor_size;
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Param<unsigned> choice_ctr_bits;
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Param<unsigned> BTBEntries;
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Param<unsigned> BTBTagSize;
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Param<unsigned> RASSize;
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Param<unsigned> LQEntries;
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Param<unsigned> SQEntries;
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Param<unsigned> LFSTSize;
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Param<unsigned> SSITSize;
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Param<unsigned> numPhysIntRegs;
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Param<unsigned> numPhysFloatRegs;
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Param<unsigned> numIQEntries;
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Param<unsigned> numROBEntries;
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Param<unsigned> instShiftAmt;
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Param<bool> defer_registration;
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Param<bool> function_trace;
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Param<Tick> function_trace_start;
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END_DECLARE_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
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BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
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INIT_PARAM(clock, "clock speed"),
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INIT_PARAM(numThreads, "number of HW thread contexts"),
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#if FULL_SYSTEM
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INIT_PARAM(system, "System object"),
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INIT_PARAM(cpu_id, "processor ID"),
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INIT_PARAM(itb, "Instruction translation buffer"),
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INIT_PARAM(dtb, "Data translation buffer"),
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#else
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INIT_PARAM(workload, "Processes to run"),
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#endif // FULL_SYSTEM
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INIT_PARAM_DFLT(mem, "Memory", NULL),
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INIT_PARAM_DFLT(max_insts_any_thread,
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"Terminate when any thread reaches this inst count",
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0),
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INIT_PARAM_DFLT(max_insts_all_threads,
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"Terminate when all threads have reached"
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"this inst count",
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0),
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INIT_PARAM_DFLT(max_loads_any_thread,
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"Terminate when any thread reaches this load count",
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0),
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INIT_PARAM_DFLT(max_loads_all_threads,
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"Terminate when all threads have reached this load"
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"count",
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0),
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INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
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INIT_PARAM_DFLT(dcache, "L1 data cache", NULL),
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INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
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INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
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INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
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"delay"),
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INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
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INIT_PARAM(fetchWidth, "Fetch width"),
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INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
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INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
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"delay"),
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INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
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INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
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INIT_PARAM(decodeWidth, "Decode width"),
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INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
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"delay"),
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INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
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INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
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INIT_PARAM(renameWidth, "Rename width"),
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INIT_PARAM(commitToIEWDelay, "Commit to "
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"Issue/Execute/Writeback delay"),
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INIT_PARAM(renameToIEWDelay, "Rename to "
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"Issue/Execute/Writeback delay"),
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INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
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"to the IEW stage)"),
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INIT_PARAM(issueWidth, "Issue width"),
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INIT_PARAM(executeWidth, "Execute width"),
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INIT_PARAM(executeIntWidth, "Integer execute width"),
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INIT_PARAM(executeFloatWidth, "Floating point execute width"),
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INIT_PARAM(executeBranchWidth, "Branch execute width"),
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INIT_PARAM(executeMemoryWidth, "Memory execute width"),
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INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
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"delay"),
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INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
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INIT_PARAM(commitWidth, "Commit width"),
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INIT_PARAM(squashWidth, "Squash width"),
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#if 0
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INIT_PARAM(localPredictorSize, "Size of the local predictor in entries. "
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"Must be a power of 2."),
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INIT_PARAM(localPredictorCtrBits, "Number of bits per counter for bpred"),
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#endif
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INIT_PARAM(local_predictor_size, "Size of local predictor"),
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INIT_PARAM(local_ctr_bits, "Bits per counter"),
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INIT_PARAM(local_history_table_size, "Size of local history table"),
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INIT_PARAM(local_history_bits, "Bits for the local history"),
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INIT_PARAM(global_predictor_size, "Size of global predictor"),
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INIT_PARAM(global_ctr_bits, "Bits per counter"),
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INIT_PARAM(global_history_bits, "Bits of history"),
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INIT_PARAM(choice_predictor_size, "Size of choice predictor"),
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INIT_PARAM(choice_ctr_bits, "Bits of choice counters"),
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INIT_PARAM(BTBEntries, "Number of BTB entries"),
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INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
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INIT_PARAM(RASSize, "RAS size"),
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INIT_PARAM(LQEntries, "Number of load queue entries"),
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INIT_PARAM(SQEntries, "Number of store queue entries"),
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INIT_PARAM(LFSTSize, "Last fetched store table size"),
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INIT_PARAM(SSITSize, "Store set ID table size"),
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INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
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INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
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"registers"),
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INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
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INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
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INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
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INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
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INIT_PARAM(function_trace, "Enable function trace"),
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INIT_PARAM(function_trace_start, "Cycle to start function trace")
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END_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
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CREATE_SIM_OBJECT(DerivAlphaFullCPU)
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{
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DerivAlphaFullCPU *cpu;
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#if FULL_SYSTEM
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// Full-system only supports a single thread for the moment.
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int actual_num_threads = 1;
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#else
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// In non-full-system mode, we infer the number of threads from
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// the workload if it's not explicitly specified.
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int actual_num_threads =
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numThreads.isValid() ? numThreads : workload.size();
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if (workload.size() == 0) {
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fatal("Must specify at least one workload!");
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}
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#endif
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AlphaSimpleParams params;
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params.clock = clock;
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params.name = getInstanceName();
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params.numberOfThreads = actual_num_threads;
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#if FULL_SYSTEM
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params.system = system;
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params.cpu_id = cpu_id;
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params.itb = itb;
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params.dtb = dtb;
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#else
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params.workload = workload;
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#endif // FULL_SYSTEM
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params.mem = mem;
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params.max_insts_any_thread = max_insts_any_thread;
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params.max_insts_all_threads = max_insts_all_threads;
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params.max_loads_any_thread = max_loads_any_thread;
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params.max_loads_all_threads = max_loads_all_threads;
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//
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// Caches
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//
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params.icacheInterface = icache ? icache->getInterface() : NULL;
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params.dcacheInterface = dcache ? dcache->getInterface() : NULL;
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params.decodeToFetchDelay = decodeToFetchDelay;
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params.renameToFetchDelay = renameToFetchDelay;
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params.iewToFetchDelay = iewToFetchDelay;
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params.commitToFetchDelay = commitToFetchDelay;
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params.fetchWidth = fetchWidth;
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params.renameToDecodeDelay = renameToDecodeDelay;
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params.iewToDecodeDelay = iewToDecodeDelay;
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params.commitToDecodeDelay = commitToDecodeDelay;
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params.fetchToDecodeDelay = fetchToDecodeDelay;
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params.decodeWidth = decodeWidth;
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params.iewToRenameDelay = iewToRenameDelay;
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params.commitToRenameDelay = commitToRenameDelay;
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params.decodeToRenameDelay = decodeToRenameDelay;
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params.renameWidth = renameWidth;
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params.commitToIEWDelay = commitToIEWDelay;
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params.renameToIEWDelay = renameToIEWDelay;
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params.issueToExecuteDelay = issueToExecuteDelay;
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params.issueWidth = issueWidth;
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params.executeWidth = executeWidth;
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params.executeIntWidth = executeIntWidth;
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params.executeFloatWidth = executeFloatWidth;
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params.executeBranchWidth = executeBranchWidth;
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params.executeMemoryWidth = executeMemoryWidth;
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params.iewToCommitDelay = iewToCommitDelay;
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params.renameToROBDelay = renameToROBDelay;
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params.commitWidth = commitWidth;
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params.squashWidth = squashWidth;
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#if 0
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params.localPredictorSize = localPredictorSize;
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params.localPredictorCtrBits = localPredictorCtrBits;
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#endif
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params.local_predictor_size = local_predictor_size;
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params.local_ctr_bits = local_ctr_bits;
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params.local_history_table_size = local_history_table_size;
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params.local_history_bits = local_history_bits;
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params.global_predictor_size = global_predictor_size;
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params.global_ctr_bits = global_ctr_bits;
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params.global_history_bits = global_history_bits;
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params.choice_predictor_size = choice_predictor_size;
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params.choice_ctr_bits = choice_ctr_bits;
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params.BTBEntries = BTBEntries;
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params.BTBTagSize = BTBTagSize;
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params.RASSize = RASSize;
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params.LQEntries = LQEntries;
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params.SQEntries = SQEntries;
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params.SSITSize = SSITSize;
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params.LFSTSize = LFSTSize;
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params.numPhysIntRegs = numPhysIntRegs;
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params.numPhysFloatRegs = numPhysFloatRegs;
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params.numIQEntries = numIQEntries;
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params.numROBEntries = numROBEntries;
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params.instShiftAmt = 2;
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params.defReg = defer_registration;
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params.functionTrace = function_trace;
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params.functionTraceStart = function_trace_start;
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cpu = new DerivAlphaFullCPU(params);
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return cpu;
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}
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REGISTER_SIM_OBJECT("DerivAlphaFullCPU", DerivAlphaFullCPU)
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