c27c122afc
change getPort parameter from char* to string Add an extra phase between construction and init called connect SConscript: Add the bus and connector objects to scons cpu/simple/cpu.cc: cpu/simple/cpu.hh: the connection to memory shouldn't be made until we know the memory object exists (e.g. after construction) dev/io_device.hh: change to const string mem/bus.hh: change getPort parameter from char* to string initialize num_interfaces mem/mem_object.hh: change getPort parameter from char* to string mem/physical.cc: mem/physical.hh: change getPort parameter from char* to string get rid of the bus object I created last time python/m5/objects/PhysicalMemory.py: get rid of the bus object I created last time sim/main.cc: sim/sim_object.cc: sim/sim_object.hh: Add an extra phase between construction and init called connect --HG-- extra : convert_revision : 0e994f93374fa72a06d291655c440ff1b8e155a9
152 lines
5.2 KiB
C++
152 lines
5.2 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file Decleration of a bus object.
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*/
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#ifndef __MEM_BUS_HH__
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#define __MEM_BUS_HH__
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#include <string>
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#include <list>
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#include <inttypes.h>
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#include "base/range.hh"
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#include "mem/mem_object.hh"
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#include "mem/packet.hh"
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#include "mem/port.hh"
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#include "mem/request.hh"
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class Bus : public MemObject
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{
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struct DevMap {
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int portId;
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Range<Addr> range;
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};
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std::vector<DevMap> portList;
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/** Function called by the port when the bus is recieving a Timing
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transaction.*/
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bool recvTiming(Packet &pkt, int id);
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/** Function called by the port when the bus is recieving a Atomic
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transaction.*/
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Tick recvAtomic(Packet &pkt, int id);
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/** Function called by the port when the bus is recieving a Functional
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transaction.*/
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void recvFunctional(Packet &pkt, int id);
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/** Function called by the port when the bus is recieving a status change.*/
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void recvStatusChange(Port::Status status, int id);
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/** Find which port connected to this bus (if any) should be given a packet
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* with this address.
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* @param addr Address to find port for.
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* @param id Id of the port this packet was received from (to prevent
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* loops)
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* @return pointer to port that the packet should be sent out of.
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*/
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Port *
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Bus::findPort(Addr addr, int id);
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/** Decleration of the buses port type, one will be instantiated for each
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of the interfaces connecting to the bus. */
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class BusPort : public Port
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{
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/** A pointer to the bus to which this port belongs. */
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Bus *bus;
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/** A id to keep track of the intercafe ID this port is connected to. */
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int id;
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public:
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/** Constructor for the BusPort.*/
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BusPort(Bus *_bus, int _id)
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: bus(_bus), id(_id)
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{ }
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protected:
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/** When reciving a timing request from the peer port (at id),
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pass it to the bus. */
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virtual bool recvTiming(Packet &pkt)
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{ return bus->recvTiming(pkt, id); }
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/** When reciving a Atomic requestfrom the peer port (at id),
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pass it to the bus. */
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virtual Tick recvAtomic(Packet &pkt)
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{ return bus->recvAtomic(pkt, id); }
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/** When reciving a Functional requestfrom the peer port (at id),
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pass it to the bus. */
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virtual void recvFunctional(Packet &pkt)
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{ bus->recvFunctional(pkt, id); }
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/** When reciving a status changefrom the peer port (at id),
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pass it to the bus. */
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virtual void recvStatusChange(Status status)
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{ bus->recvStatusChange(status, id); }
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// This should return all the 'owned' addresses that are
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// downstream from this bus, yes? That is, the union of all
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// the 'owned' address ranges of all the other interfaces on
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// this bus...
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virtual void addressRanges(AddrRangeList &range_list, bool &owner);
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// Hack to make translating port work without changes
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virtual int deviceBlockSize() { return 32; }
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};
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/** A count of the number of interfaces connected to this bus. */
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int num_interfaces;
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/** An array of pointers to the peer port interfaces
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connected to this bus.*/
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Port *interfaces[];
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public:
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/** A function used to return the port associated with this bus object. */
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virtual Port *getPort(const std::string &if_name)
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{
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// if_name ignored? forced to be empty?
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int id = num_interfaces++;
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interfaces[id] = new BusPort(this, id);
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return interfaces[id];
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}
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Bus(const std::string &n)
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: MemObject(n), num_interfaces(0) {}
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};
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#endif //__MEM_BUS_HH__
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