gem5/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
Steve Reinhardt d486700149 Add short memtest run to quick regressions.
Caveats:
- Even though memtest is ISA-independent, it will only
run for the Alpha builds, since there's no way to specify
ISA-independent reference files and I didn't want to commit
3 copies since I'm not sure we want to run it for all the
different ISAs anyway.
- Reference outputs were generated on my laptop,
so performance numbers will be low compared to zizzer.

--HG--
extra : convert_revision : 210fe4abecc19fbab0b15402c6cb4863650bab66
2007-02-06 21:16:33 -08:00

621 lines
11 KiB
INI

[root]
type=Root
children=system
checkpoint=
clock=1000000000000
max_tick=0
output_file=cout
progress_interval=0
[exetrace]
intel_format=false
legion_lockstep=false
pc_symbol=true
print_cpseq=false
print_cycle=true
print_data=true
print_effaddr=true
print_fetchseq=false
print_iregs=false
print_opclass=true
print_thread=true
speculative=true
trace_system=client
[serialize]
count=10
cycle=0
dir=cpt.%012d
period=0
[stats]
descriptions=true
dump_cycle=0
dump_period=0
dump_reset=false
ignore_events=
mysql_db=
mysql_host=
mysql_password=
mysql_user=
project_name=test
simulation_name=test
simulation_sample=0
text_compat=true
text_file=m5stats.txt
[system]
type=System
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem l2c membus physmem toL2Bus
mem_mode=timing
physmem=system.physmem
[system.cpu0]
type=MemTest
children=l1c
atomic=false
max_loads=100000
memory_size=65536
percent_dest_unaligned=50
percent_functional=50
percent_reads=65
percent_source_unaligned=50
percent_uncacheable=10
progress_interval=10000
trace_addr=0
functional=system.funcmem.port
test=system.cpu0.l1c.cpu_side
[system.cpu0.l1c]
type=BaseCache
children=protocol
adaptive_compression=false
assoc=4
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
lifo=false
max_miss_count=0
mshrs=12
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=system.cpu0.l1c.protocol
repl=Null
size=32768
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.test
mem_side=system.toL2Bus.port[1]
[system.cpu0.l1c.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=moesi
[system.cpu1]
type=MemTest
children=l1c
atomic=false
max_loads=100000
memory_size=65536
percent_dest_unaligned=50
percent_functional=50
percent_reads=65
percent_source_unaligned=50
percent_uncacheable=10
progress_interval=10000
trace_addr=0
functional=system.funcmem.functional
test=system.cpu1.l1c.cpu_side
[system.cpu1.l1c]
type=BaseCache
children=protocol
adaptive_compression=false
assoc=4
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
lifo=false
max_miss_count=0
mshrs=12
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=system.cpu1.l1c.protocol
repl=Null
size=32768
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.test
mem_side=system.toL2Bus.port[2]
[system.cpu1.l1c.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=moesi
[system.cpu2]
type=MemTest
children=l1c
atomic=false
max_loads=100000
memory_size=65536
percent_dest_unaligned=50
percent_functional=50
percent_reads=65
percent_source_unaligned=50
percent_uncacheable=10
progress_interval=10000
trace_addr=0
functional=system.funcmem.functional
test=system.cpu2.l1c.cpu_side
[system.cpu2.l1c]
type=BaseCache
children=protocol
adaptive_compression=false
assoc=4
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
lifo=false
max_miss_count=0
mshrs=12
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=system.cpu2.l1c.protocol
repl=Null
size=32768
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu2.test
mem_side=system.toL2Bus.port[3]
[system.cpu2.l1c.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=moesi
[system.cpu3]
type=MemTest
children=l1c
atomic=false
max_loads=100000
memory_size=65536
percent_dest_unaligned=50
percent_functional=50
percent_reads=65
percent_source_unaligned=50
percent_uncacheable=10
progress_interval=10000
trace_addr=0
functional=system.funcmem.functional
test=system.cpu3.l1c.cpu_side
[system.cpu3.l1c]
type=BaseCache
children=protocol
adaptive_compression=false
assoc=4
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
lifo=false
max_miss_count=0
mshrs=12
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=system.cpu3.l1c.protocol
repl=Null
size=32768
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu3.test
mem_side=system.toL2Bus.port[4]
[system.cpu3.l1c.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=moesi
[system.cpu4]
type=MemTest
children=l1c
atomic=false
max_loads=100000
memory_size=65536
percent_dest_unaligned=50
percent_functional=50
percent_reads=65
percent_source_unaligned=50
percent_uncacheable=10
progress_interval=10000
trace_addr=0
functional=system.funcmem.functional
test=system.cpu4.l1c.cpu_side
[system.cpu4.l1c]
type=BaseCache
children=protocol
adaptive_compression=false
assoc=4
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
lifo=false
max_miss_count=0
mshrs=12
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=system.cpu4.l1c.protocol
repl=Null
size=32768
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu4.test
mem_side=system.toL2Bus.port[5]
[system.cpu4.l1c.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=moesi
[system.cpu5]
type=MemTest
children=l1c
atomic=false
max_loads=100000
memory_size=65536
percent_dest_unaligned=50
percent_functional=50
percent_reads=65
percent_source_unaligned=50
percent_uncacheable=10
progress_interval=10000
trace_addr=0
functional=system.funcmem.functional
test=system.cpu5.l1c.cpu_side
[system.cpu5.l1c]
type=BaseCache
children=protocol
adaptive_compression=false
assoc=4
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
lifo=false
max_miss_count=0
mshrs=12
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=system.cpu5.l1c.protocol
repl=Null
size=32768
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu5.test
mem_side=system.toL2Bus.port[6]
[system.cpu5.l1c.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=moesi
[system.cpu6]
type=MemTest
children=l1c
atomic=false
max_loads=100000
memory_size=65536
percent_dest_unaligned=50
percent_functional=50
percent_reads=65
percent_source_unaligned=50
percent_uncacheable=10
progress_interval=10000
trace_addr=0
functional=system.funcmem.functional
test=system.cpu6.l1c.cpu_side
[system.cpu6.l1c]
type=BaseCache
children=protocol
adaptive_compression=false
assoc=4
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
lifo=false
max_miss_count=0
mshrs=12
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=system.cpu6.l1c.protocol
repl=Null
size=32768
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu6.test
mem_side=system.toL2Bus.port[7]
[system.cpu6.l1c.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=moesi
[system.cpu7]
type=MemTest
children=l1c
atomic=false
max_loads=100000
memory_size=65536
percent_dest_unaligned=50
percent_functional=50
percent_reads=65
percent_source_unaligned=50
percent_uncacheable=10
progress_interval=10000
trace_addr=0
functional=system.funcmem.functional
test=system.cpu7.l1c.cpu_side
[system.cpu7.l1c]
type=BaseCache
children=protocol
adaptive_compression=false
assoc=4
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
lifo=false
max_miss_count=0
mshrs=12
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=system.cpu7.l1c.protocol
repl=Null
size=32768
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu7.test
mem_side=system.toL2Bus.port[8]
[system.cpu7.l1c.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=moesi
[system.funcmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
zero=false
functional=system.cpu7.functional
port=system.cpu0.functional
[system.l2c]
type=BaseCache
adaptive_compression=false
assoc=8
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=10
lifo=false
max_miss_count=0
mshrs=92
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=65536
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=16
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.port[0]
mem_side=system.membus.port[0]
[system.membus]
type=Bus
bus_id=0
clock=2
responder_set=false
width=16
port=system.l2c.mem_side system.physmem.port
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
zero=false
port=system.membus.port[1]
[system.toL2Bus]
type=Bus
bus_id=0
clock=2
responder_set=false
width=16
port=system.l2c.cpu_side system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side
[trace]
bufsize=0
cycle=0
dump_on_exit=false
file=cout
flags=
ignore=
start=0