c552b06a8c
Auxiliary Functions and Formats for FP in general
arch/mips/isa/decoder.isa:
ISA Parser doesnt accept operands of different types in one instruction so fix this for unorderedFP functions...
Add basic support for Paired Singled (PS) FP ops which happen to be part of the MIPS 32-ASE but turned out to
be included in the MIPS32ISA manual... The PS instructions allow SIMD in a pipeline...
arch/mips/isa/formats/fp.isa:
Add some more Formats for FP operation. I will add some auxiliary code through these formats
to alleviate code redundancy in the decoder.isa
arch/mips/isa/operands.isa:
Add operands for Paired Singles Ops
arch/mips/isa_traits.cc:
removed convert&round function and replace with fpConvert.
The whole "rounding mode" stuff is something that should be considered for full-system mode...
Also added skeletons for the unorderedFP,truncFP,and condition code funcs.
arch/mips/isa_traits.hh:
declare some Functions
arch/mips/types.hh:
add new conversion types
--HG--
extra : convert_revision : 79251d590a27b74a3d6a62a2fbb937df3e59963f
46 lines
1.6 KiB
Plaintext
46 lines
1.6 KiB
Plaintext
def operand_types {{
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'sb' : ('signed int', 8),
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'ub' : ('unsigned int', 8),
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'sh' : ('signed int', 16),
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'uh' : ('unsigned int', 16),
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'sw' : ('signed int', 32),
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'uw' : ('unsigned int', 32),
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'sd' : ('signed int', 64),
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'ud' : ('unsigned int', 64),
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'sf' : ('float', 32),
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'df' : ('float', 64),
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'qf' : ('float', 128)
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}};
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def operands {{
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'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
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'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2),
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'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
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'r31': ('IntReg', 'uw','R31','IsInteger', 4),
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'R0': ('IntReg', 'uw','R0', 'IsInteger', 5),
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'R2': ('IntReg', 'uw','2', 'IsInteger', 5),
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'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
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'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1),
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'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
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'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
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'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
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#Operands For Paired Singles FP Operations
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'Fd1': ('FloatReg', 'sf', 'FD', 'IsFloating', 4),
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'Fd2': ('FloatReg', 'sf', 'FD+1', 'IsFloating', 4),
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'Fs1': ('FloatReg', 'sf', 'FS', 'IsFloating', 5),
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'Fs2': ('FloatReg', 'sf', 'FS+1', 'IsFloating', 5),
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'Ft1': ('FloatReg', 'sf', 'FT', 'IsFloating', 6),
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'Ft2': ('FloatReg', 'sf', 'FT+1', 'IsFloating', 6),
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'Fr1': ('FloatReg', 'sf', 'FR', 'IsFloating', 7),
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'Fr2': ('FloatReg', 'sf', 'FR+1', 'IsFloating', 7),
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'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
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'NPC': ('NPC', 'uw', None, ( None, None, 'IsControl' ), 4),
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'NNPC':('NNPC', 'uw', None, ( None, None, 'IsControl' ), 4)
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}};
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