203 lines
7.1 KiB
C++
203 lines
7.1 KiB
C++
// Copyright (c) 2015 ARM Limited
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// All rights reserved.
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// Copyright 2009-2014 Sandia Coporation. Under the terms
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// of Contract DE-AC04-94AL85000 with Sandia Corporation, the U.S.
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// Government retains certain rights in this software.
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//
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// Copyright (c) 2009-2014, Sandia Corporation
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// All rights reserved.
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//
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// For license information, see the LICENSE file in the current directory.
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#include "gem5.hh"
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#include <sst_config.h>
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#include <sst/core/serialization.h>
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#include <sst/core/params.h>
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#include <sst/core/output.h>
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#include <sst/core/link.h>
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#ifdef fatal // gem5 sets this
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#undef fatal
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#endif
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using namespace SST;
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using namespace SST::gem5;
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using namespace SST::MemHierarchy;
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ExtSlave::ExtSlave(gem5Component *g5c, Output &out,
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::ExternalSlave& port, std::string &name) :
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Port(name, port),
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comp(g5c), out(out), simPhase(CONSTRUCTION), initPackets(NULL),
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link(comp->configureLink(name, new Event::Handler<ExtSlave>(this,
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&ExtSlave::handleEvent)))
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{
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if (!link) {
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out.fatal(CALL_INFO, 1, "Failed to configure link %s\n", name.c_str());
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}
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}
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void ExtSlave::init(unsigned phase)
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{
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simPhase = INIT;
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if (initPackets) {
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while (!initPackets->empty()) {
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link->sendInitData(initPackets->front());
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initPackets->pop_front();
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}
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delete initPackets;
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initPackets = NULL;
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}
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}
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void
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ExtSlave::recvFunctional(PacketPtr pkt)
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{
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if (simPhase == CONSTRUCTION) {
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if (initPackets == NULL) {
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initPackets = new std::list<MemEvent*>;
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}
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::MemCmd::Command pktCmd = (::MemCmd::Command)pkt->cmd.toInt();
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assert(pktCmd == ::MemCmd::WriteReq);
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Addr a = pkt->getAddr();
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MemEvent* ev = new MemEvent(comp, a, a, GetX);
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ev->setPayload(pkt->getSize(), pkt->getPtr<uint8_t>());
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initPackets->push_back(ev);
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} else {
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panic("Functional accesses not allowed after construction phase");
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}
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}
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bool
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ExtSlave::recvTimingReq(PacketPtr pkt)
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{
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Command cmd;
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switch ((::MemCmd::Command)pkt->cmd.toInt()) {
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case ::MemCmd::HardPFReq:
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case ::MemCmd::SoftPFReq:
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case ::MemCmd::LoadLockedReq:
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case ::MemCmd::ReadExReq:
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case ::MemCmd::ReadReq: cmd = GetS; break;
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case ::MemCmd::StoreCondReq:
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case ::MemCmd::WriteReq: cmd = GetX; break;
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default:
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out.fatal(CALL_INFO, 1, "Don't know how to convert gem5 packet "
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"command %s to SST\n", pkt->cmd.toString().c_str());
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}
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auto ev = new MemEvent(comp, pkt->getAddr(), pkt->getAddr(), cmd);
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ev->setPayload(pkt->getSize(), pkt->getPtr<uint8_t>());
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if ((::MemCmd::Command)pkt->cmd.toInt() == ::MemCmd::LoadLockedReq)
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ev->setLoadLink();
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else if ((::MemCmd::Command)pkt->cmd.toInt() == ::MemCmd::StoreCondReq)
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ev->setStoreConditional();
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if (pkt->req->isLockedRMW()) ev->setFlag(MemEvent::F_LOCKED);
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if (pkt->req->isUncacheable()) ev->setFlag(MemEvent::F_NONCACHEABLE);
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if (pkt->req->hasContextId()) ev->setGroupId(pkt->req->contextId());
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// Prefetches not working with SST; it maybe be dropping them, treating them
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// as not deserving of responses, or something else -- not sure yet.
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// ev->setPrefetchFlag(pkt->req->isPrefetch());
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if (simPhase == INIT) {
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link->sendInitData(ev);
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delete pkt->req;
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delete pkt;
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} else {
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if (pkt->needsResponse()) {
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PacketMap[ev->getID()] = pkt;
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}
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link->send(ev);
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}
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return true;
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}
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void
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ExtSlave::handleEvent(Event* ev)
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{
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MemEvent* event = dynamic_cast<MemEvent*>(ev);
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if (!event) {
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out.fatal(CALL_INFO, 1, "ExtSlave handleEvent received non-MemEvent\n");
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delete ev;
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return;
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}
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Event::id_type id = event->getID();
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PacketMap_t::iterator mi = PacketMap.find(id);
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if (mi != PacketMap.end()) { // replying to prior request
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PacketPtr pkt = mi->second;
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PacketMap.erase(mi);
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pkt->makeResponse(); // Convert to a response packet
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pkt->setData(event->getPayload().data());
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// Resolve the success of Store Conditionals
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if (pkt->isLLSC() && pkt->isWrite()) {
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pkt->req->setExtraData(event->isAtomic());
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}
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// Clear out bus delay notifications
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pkt->headerDelay = pkt->payloadDelay = 0;
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if (blocked() || !sendTimingResp(pkt)) {
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respQ.push_back(pkt);
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}
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} else { // we can handle unexpected invalidates, but nothing else.
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Command cmd = event->getCmd();
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assert(cmd == Inv);
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// make Req/Pkt for Snoop/no response needed
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// presently no consideration for masterId, packet type, flags...
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RequestPtr req = new Request(event->getAddr(), event->getSize(), 0, 0);
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auto pkt = new Packet(req, ::MemCmd::InvalidateReq);
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// Clear out bus delay notifications
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pkt->headerDelay = pkt->payloadDelay = 0;
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sendTimingSnoopReq(pkt);
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}
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delete event;
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}
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void
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ExtSlave::recvRespRetry()
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{
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while (blocked() && sendTimingResp(respQ.front())) {
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respQ.pop_front();
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}
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}
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