782 lines
23 KiB
C++
782 lines
23 KiB
C++
/*
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* Copyright (c) 2009 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include "arch/sparc/asi.hh"
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#include "arch/sparc/isa.hh"
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#include "base/bitfield.hh"
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#include "base/trace.hh"
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#include "config/full_system.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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namespace SparcISA
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{
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enum RegMask
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{
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PSTATE_MASK = (((1 << 4) - 1) << 1) | (((1 << 4) - 1) << 6) | (1 << 12)
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};
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void
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ISA::reloadRegMap()
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{
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installGlobals(gl, CurrentGlobalsOffset);
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installWindow(cwp, CurrentWindowOffset);
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// Microcode registers.
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for (int i = 0; i < NumMicroIntRegs; i++)
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intRegMap[MicroIntOffset + i] = i + TotalGlobals + NWindows * 16;
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installGlobals(gl, NextGlobalsOffset);
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installWindow(cwp - 1, NextWindowOffset);
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installGlobals(gl, PreviousGlobalsOffset);
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installWindow(cwp + 1, PreviousWindowOffset);
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}
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void
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ISA::installWindow(int cwp, int offset)
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{
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assert(offset >= 0 && offset + NumWindowedRegs <= NumIntRegs);
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RegIndex *mapChunk = intRegMap + offset;
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for (int i = 0; i < NumWindowedRegs; i++)
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mapChunk[i] = TotalGlobals +
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((i - cwp * RegsPerWindow + TotalWindowed) % (TotalWindowed));
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}
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void
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ISA::installGlobals(int gl, int offset)
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{
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assert(offset >= 0 && offset + NumGlobalRegs <= NumIntRegs);
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RegIndex *mapChunk = intRegMap + offset;
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mapChunk[0] = 0;
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for (int i = 1; i < NumGlobalRegs; i++)
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mapChunk[i] = i + gl * NumGlobalRegs;
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}
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void
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ISA::clear()
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{
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cwp = 0;
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gl = 0;
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reloadRegMap();
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// y = 0;
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// ccr = 0;
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asi = 0;
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tick = ULL(1) << 63;
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fprs = 0;
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gsr = 0;
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softint = 0;
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tick_cmpr = 0;
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stick = 0;
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stick_cmpr = 0;
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memset(tpc, 0, sizeof(tpc));
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memset(tnpc, 0, sizeof(tnpc));
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memset(tstate, 0, sizeof(tstate));
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memset(tt, 0, sizeof(tt));
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tba = 0;
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pstate = 0;
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tl = 0;
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pil = 0;
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// cansave = 0;
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// canrestore = 0;
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// cleanwin = 0;
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// otherwin = 0;
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// wstate = 0;
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// In a T1, bit 11 is apparently always 1
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hpstate = (1 << 11);
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memset(htstate, 0, sizeof(htstate));
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hintp = 0;
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htba = 0;
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hstick_cmpr = 0;
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// This is set this way in Legion for some reason
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strandStatusReg = 0x50000;
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fsr = 0;
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priContext = 0;
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secContext = 0;
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partId = 0;
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lsuCtrlReg = 0;
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memset(scratchPad, 0, sizeof(scratchPad));
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cpu_mondo_head = 0;
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cpu_mondo_tail = 0;
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dev_mondo_head = 0;
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dev_mondo_tail = 0;
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res_error_head = 0;
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res_error_tail = 0;
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nres_error_head = 0;
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nres_error_tail = 0;
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#if FULL_SYSTEM
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// If one of these events is active, it's not obvious to me how to get
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// rid of it cleanly. For now we'll just assert that they're not.
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if (tickCompare != NULL && sTickCompare != NULL && hSTickCompare != NULL)
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panic("Tick comparison event active when clearing the ISA object.\n");
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#endif
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}
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MiscReg
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ISA::readMiscRegNoEffect(int miscReg)
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{
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// The three miscRegs are moved up from the switch statement
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// due to more frequent calls.
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if (miscReg == MISCREG_GL)
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return gl;
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if (miscReg == MISCREG_CWP)
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return cwp;
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if (miscReg == MISCREG_TLB_DATA) {
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/* Package up all the data for the tlb:
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* 6666555555555544444444443333333333222222222211111111110000000000
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* 3210987654321098765432109876543210987654321098765432109876543210
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* secContext | priContext | |tl|partid| |||||^hpriv
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* ||||^red
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* |||^priv
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* ||^am
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* |^lsuim
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* ^lsudm
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*/
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return bits((uint64_t)hpstate,2,2) |
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bits((uint64_t)hpstate,5,5) << 1 |
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bits((uint64_t)pstate,3,2) << 2 |
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bits((uint64_t)lsuCtrlReg,3,2) << 4 |
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bits((uint64_t)partId,7,0) << 8 |
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bits((uint64_t)tl,2,0) << 16 |
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(uint64_t)priContext << 32 |
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(uint64_t)secContext << 48;
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}
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switch (miscReg) {
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// case MISCREG_TLB_DATA:
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// [original contents see above]
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// case MISCREG_Y:
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// return y;
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// case MISCREG_CCR:
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// return ccr;
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case MISCREG_ASI:
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return asi;
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case MISCREG_FPRS:
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return fprs;
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case MISCREG_TICK:
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return tick;
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case MISCREG_PCR:
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panic("PCR not implemented\n");
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case MISCREG_PIC:
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panic("PIC not implemented\n");
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case MISCREG_GSR:
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return gsr;
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case MISCREG_SOFTINT:
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return softint;
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case MISCREG_TICK_CMPR:
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return tick_cmpr;
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case MISCREG_STICK:
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return stick;
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case MISCREG_STICK_CMPR:
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return stick_cmpr;
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/** Privilged Registers */
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case MISCREG_TPC:
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return tpc[tl-1];
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case MISCREG_TNPC:
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return tnpc[tl-1];
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case MISCREG_TSTATE:
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return tstate[tl-1];
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case MISCREG_TT:
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return tt[tl-1];
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case MISCREG_PRIVTICK:
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panic("Priviliged access to tick registers not implemented\n");
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case MISCREG_TBA:
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return tba;
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case MISCREG_PSTATE:
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return pstate;
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case MISCREG_TL:
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return tl;
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case MISCREG_PIL:
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return pil;
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// CWP, GL moved
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// case MISCREG_CWP:
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// return cwp;
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// case MISCREG_CANSAVE:
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// return cansave;
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// case MISCREG_CANRESTORE:
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// return canrestore;
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// case MISCREG_CLEANWIN:
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// return cleanwin;
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// case MISCREG_OTHERWIN:
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// return otherwin;
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// case MISCREG_WSTATE:
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// return wstate;
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// case MISCREG_GL:
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// return gl;
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/** Hyper privileged registers */
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case MISCREG_HPSTATE:
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return hpstate;
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case MISCREG_HTSTATE:
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return htstate[tl-1];
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case MISCREG_HINTP:
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return hintp;
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case MISCREG_HTBA:
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return htba;
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case MISCREG_STRAND_STS_REG:
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return strandStatusReg;
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case MISCREG_HSTICK_CMPR:
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return hstick_cmpr;
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/** Floating Point Status Register */
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case MISCREG_FSR:
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DPRINTF(MiscRegs, "FSR read as: %#x\n", fsr);
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return fsr;
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case MISCREG_MMU_P_CONTEXT:
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return priContext;
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case MISCREG_MMU_S_CONTEXT:
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return secContext;
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case MISCREG_MMU_PART_ID:
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return partId;
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case MISCREG_MMU_LSU_CTRL:
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return lsuCtrlReg;
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case MISCREG_SCRATCHPAD_R0:
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return scratchPad[0];
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case MISCREG_SCRATCHPAD_R1:
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return scratchPad[1];
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case MISCREG_SCRATCHPAD_R2:
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return scratchPad[2];
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case MISCREG_SCRATCHPAD_R3:
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return scratchPad[3];
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case MISCREG_SCRATCHPAD_R4:
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return scratchPad[4];
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case MISCREG_SCRATCHPAD_R5:
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return scratchPad[5];
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case MISCREG_SCRATCHPAD_R6:
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return scratchPad[6];
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case MISCREG_SCRATCHPAD_R7:
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return scratchPad[7];
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case MISCREG_QUEUE_CPU_MONDO_HEAD:
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return cpu_mondo_head;
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case MISCREG_QUEUE_CPU_MONDO_TAIL:
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return cpu_mondo_tail;
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case MISCREG_QUEUE_DEV_MONDO_HEAD:
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return dev_mondo_head;
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case MISCREG_QUEUE_DEV_MONDO_TAIL:
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return dev_mondo_tail;
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case MISCREG_QUEUE_RES_ERROR_HEAD:
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return res_error_head;
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case MISCREG_QUEUE_RES_ERROR_TAIL:
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return res_error_tail;
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case MISCREG_QUEUE_NRES_ERROR_HEAD:
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return nres_error_head;
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case MISCREG_QUEUE_NRES_ERROR_TAIL:
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return nres_error_tail;
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default:
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panic("Miscellaneous register %d not implemented\n", miscReg);
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}
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}
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MiscReg
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ISA::readMiscReg(int miscReg, ThreadContext * tc)
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{
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switch (miscReg) {
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// tick and stick are aliased to each other in niagra
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// well store the tick data in stick and the interrupt bit in tick
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case MISCREG_STICK:
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case MISCREG_TICK:
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case MISCREG_PRIVTICK:
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// I'm not sure why legion ignores the lowest two bits, but we'll go
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// with it
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// change from curCycle() to instCount() until we're done with legion
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DPRINTF(Timer, "Instruction Count when TICK read: %#X stick=%#X\n",
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tc->getCpuPtr()->instCount(), stick);
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return mbits(tc->getCpuPtr()->instCount() + (int64_t)stick,62,2) |
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mbits(tick,63,63);
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case MISCREG_FPRS:
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// in legion if fp is enabled du and dl are set
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return fprs | 0x3;
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case MISCREG_PCR:
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case MISCREG_PIC:
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panic("Performance Instrumentation not impl\n");
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case MISCREG_SOFTINT_CLR:
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case MISCREG_SOFTINT_SET:
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panic("Can read from softint clr/set\n");
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case MISCREG_SOFTINT:
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case MISCREG_TICK_CMPR:
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case MISCREG_STICK_CMPR:
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case MISCREG_HINTP:
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case MISCREG_HTSTATE:
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case MISCREG_HTBA:
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case MISCREG_HVER:
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case MISCREG_STRAND_STS_REG:
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case MISCREG_HSTICK_CMPR:
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case MISCREG_QUEUE_CPU_MONDO_HEAD:
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case MISCREG_QUEUE_CPU_MONDO_TAIL:
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case MISCREG_QUEUE_DEV_MONDO_HEAD:
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case MISCREG_QUEUE_DEV_MONDO_TAIL:
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case MISCREG_QUEUE_RES_ERROR_HEAD:
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case MISCREG_QUEUE_RES_ERROR_TAIL:
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case MISCREG_QUEUE_NRES_ERROR_HEAD:
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case MISCREG_QUEUE_NRES_ERROR_TAIL:
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#if FULL_SYSTEM
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case MISCREG_HPSTATE:
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return readFSReg(miscReg, tc);
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#else
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case MISCREG_HPSTATE:
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// HPSTATE is special because because sometimes in privilege
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// checks for instructions it will read HPSTATE to make sure
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// the priv. level is ok So, we'll just have to tell it it
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// isn't, instead of panicing.
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return 0;
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panic("Accessing Fullsystem register %d in SE mode\n", miscReg);
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#endif
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}
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return readMiscRegNoEffect(miscReg);
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}
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void
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ISA::setMiscRegNoEffect(int miscReg, MiscReg val)
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{
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switch (miscReg) {
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// case MISCREG_Y:
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// y = val;
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// break;
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// case MISCREG_CCR:
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// ccr = val;
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// break;
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case MISCREG_ASI:
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asi = val;
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break;
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case MISCREG_FPRS:
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fprs = val;
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break;
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case MISCREG_TICK:
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tick = val;
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break;
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case MISCREG_PCR:
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panic("PCR not implemented\n");
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case MISCREG_PIC:
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panic("PIC not implemented\n");
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case MISCREG_GSR:
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gsr = val;
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break;
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case MISCREG_SOFTINT:
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softint = val;
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break;
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case MISCREG_TICK_CMPR:
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tick_cmpr = val;
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break;
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case MISCREG_STICK:
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stick = val;
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break;
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case MISCREG_STICK_CMPR:
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stick_cmpr = val;
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break;
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/** Privilged Registers */
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case MISCREG_TPC:
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tpc[tl-1] = val;
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break;
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case MISCREG_TNPC:
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tnpc[tl-1] = val;
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break;
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case MISCREG_TSTATE:
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tstate[tl-1] = val;
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break;
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case MISCREG_TT:
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tt[tl-1] = val;
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break;
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case MISCREG_PRIVTICK:
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panic("Priviliged access to tick regesiters not implemented\n");
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case MISCREG_TBA:
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// clear lower 7 bits on writes.
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tba = val & ULL(~0x7FFF);
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break;
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case MISCREG_PSTATE:
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pstate = (val & PSTATE_MASK);
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break;
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case MISCREG_TL:
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tl = val;
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break;
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case MISCREG_PIL:
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pil = val;
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break;
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case MISCREG_CWP:
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cwp = val;
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break;
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// case MISCREG_CANSAVE:
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// cansave = val;
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// break;
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// case MISCREG_CANRESTORE:
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// canrestore = val;
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// break;
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// case MISCREG_CLEANWIN:
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// cleanwin = val;
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// break;
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// case MISCREG_OTHERWIN:
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// otherwin = val;
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// break;
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// case MISCREG_WSTATE:
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// wstate = val;
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// break;
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case MISCREG_GL:
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gl = val;
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break;
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/** Hyper privileged registers */
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case MISCREG_HPSTATE:
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hpstate = val;
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break;
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case MISCREG_HTSTATE:
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htstate[tl-1] = val;
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break;
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case MISCREG_HINTP:
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hintp = val;
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case MISCREG_HTBA:
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htba = val;
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break;
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case MISCREG_STRAND_STS_REG:
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strandStatusReg = val;
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break;
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case MISCREG_HSTICK_CMPR:
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hstick_cmpr = val;
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break;
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/** Floating Point Status Register */
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case MISCREG_FSR:
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fsr = val;
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DPRINTF(MiscRegs, "FSR written with: %#x\n", fsr);
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break;
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case MISCREG_MMU_P_CONTEXT:
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priContext = val;
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break;
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case MISCREG_MMU_S_CONTEXT:
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secContext = val;
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break;
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case MISCREG_MMU_PART_ID:
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partId = val;
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break;
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case MISCREG_MMU_LSU_CTRL:
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lsuCtrlReg = val;
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break;
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case MISCREG_SCRATCHPAD_R0:
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scratchPad[0] = val;
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break;
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case MISCREG_SCRATCHPAD_R1:
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scratchPad[1] = val;
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break;
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case MISCREG_SCRATCHPAD_R2:
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scratchPad[2] = val;
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break;
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case MISCREG_SCRATCHPAD_R3:
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scratchPad[3] = val;
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break;
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case MISCREG_SCRATCHPAD_R4:
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scratchPad[4] = val;
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break;
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case MISCREG_SCRATCHPAD_R5:
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scratchPad[5] = val;
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break;
|
|
case MISCREG_SCRATCHPAD_R6:
|
|
scratchPad[6] = val;
|
|
break;
|
|
case MISCREG_SCRATCHPAD_R7:
|
|
scratchPad[7] = val;
|
|
break;
|
|
case MISCREG_QUEUE_CPU_MONDO_HEAD:
|
|
cpu_mondo_head = val;
|
|
break;
|
|
case MISCREG_QUEUE_CPU_MONDO_TAIL:
|
|
cpu_mondo_tail = val;
|
|
break;
|
|
case MISCREG_QUEUE_DEV_MONDO_HEAD:
|
|
dev_mondo_head = val;
|
|
break;
|
|
case MISCREG_QUEUE_DEV_MONDO_TAIL:
|
|
dev_mondo_tail = val;
|
|
break;
|
|
case MISCREG_QUEUE_RES_ERROR_HEAD:
|
|
res_error_head = val;
|
|
break;
|
|
case MISCREG_QUEUE_RES_ERROR_TAIL:
|
|
res_error_tail = val;
|
|
break;
|
|
case MISCREG_QUEUE_NRES_ERROR_HEAD:
|
|
nres_error_head = val;
|
|
break;
|
|
case MISCREG_QUEUE_NRES_ERROR_TAIL:
|
|
nres_error_tail = val;
|
|
break;
|
|
default:
|
|
panic("Miscellaneous register %d not implemented\n", miscReg);
|
|
}
|
|
}
|
|
|
|
void
|
|
ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
|
|
{
|
|
MiscReg new_val = val;
|
|
|
|
switch (miscReg) {
|
|
case MISCREG_STICK:
|
|
case MISCREG_TICK:
|
|
// stick and tick are same thing on niagra
|
|
// use stick for offset and tick for holding intrrupt bit
|
|
stick = mbits(val,62,0) - tc->getCpuPtr()->instCount();
|
|
tick = mbits(val,63,63);
|
|
DPRINTF(Timer, "Writing TICK=%#X\n", val);
|
|
break;
|
|
case MISCREG_FPRS:
|
|
// Configure the fpu based on the fprs
|
|
break;
|
|
case MISCREG_PCR:
|
|
// Set up performance counting based on pcr value
|
|
break;
|
|
case MISCREG_PSTATE:
|
|
pstate = val & PSTATE_MASK;
|
|
return;
|
|
case MISCREG_TL:
|
|
tl = val;
|
|
#if FULL_SYSTEM
|
|
if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
|
|
tc->getCpuPtr()->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
|
|
else
|
|
tc->getCpuPtr()->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
|
|
#endif
|
|
return;
|
|
case MISCREG_CWP:
|
|
new_val = val >= NWindows ? NWindows - 1 : val;
|
|
if (val >= NWindows)
|
|
new_val = NWindows - 1;
|
|
|
|
installWindow(new_val, CurrentWindowOffset);
|
|
installWindow(new_val - 1, NextWindowOffset);
|
|
installWindow(new_val + 1, PreviousWindowOffset);
|
|
break;
|
|
case MISCREG_GL:
|
|
installGlobals(val, CurrentGlobalsOffset);
|
|
installGlobals(val, NextGlobalsOffset);
|
|
installGlobals(val, PreviousGlobalsOffset);
|
|
break;
|
|
case MISCREG_PIL:
|
|
case MISCREG_SOFTINT:
|
|
case MISCREG_SOFTINT_SET:
|
|
case MISCREG_SOFTINT_CLR:
|
|
case MISCREG_TICK_CMPR:
|
|
case MISCREG_STICK_CMPR:
|
|
case MISCREG_HINTP:
|
|
case MISCREG_HTSTATE:
|
|
case MISCREG_HTBA:
|
|
case MISCREG_HVER:
|
|
case MISCREG_STRAND_STS_REG:
|
|
case MISCREG_HSTICK_CMPR:
|
|
case MISCREG_QUEUE_CPU_MONDO_HEAD:
|
|
case MISCREG_QUEUE_CPU_MONDO_TAIL:
|
|
case MISCREG_QUEUE_DEV_MONDO_HEAD:
|
|
case MISCREG_QUEUE_DEV_MONDO_TAIL:
|
|
case MISCREG_QUEUE_RES_ERROR_HEAD:
|
|
case MISCREG_QUEUE_RES_ERROR_TAIL:
|
|
case MISCREG_QUEUE_NRES_ERROR_HEAD:
|
|
case MISCREG_QUEUE_NRES_ERROR_TAIL:
|
|
#if FULL_SYSTEM
|
|
case MISCREG_HPSTATE:
|
|
setFSReg(miscReg, val, tc);
|
|
return;
|
|
#else
|
|
case MISCREG_HPSTATE:
|
|
// HPSTATE is special because normal trap processing saves HPSTATE when
|
|
// it goes into a trap, and restores it when it returns.
|
|
return;
|
|
panic("Accessing Fullsystem register %d to %#x in SE mode\n",
|
|
miscReg, val);
|
|
#endif
|
|
}
|
|
setMiscRegNoEffect(miscReg, new_val);
|
|
}
|
|
|
|
void
|
|
ISA::serialize(EventManager *em, std::ostream &os)
|
|
{
|
|
SERIALIZE_SCALAR(asi);
|
|
SERIALIZE_SCALAR(tick);
|
|
SERIALIZE_SCALAR(fprs);
|
|
SERIALIZE_SCALAR(gsr);
|
|
SERIALIZE_SCALAR(softint);
|
|
SERIALIZE_SCALAR(tick_cmpr);
|
|
SERIALIZE_SCALAR(stick);
|
|
SERIALIZE_SCALAR(stick_cmpr);
|
|
SERIALIZE_ARRAY(tpc,MaxTL);
|
|
SERIALIZE_ARRAY(tnpc,MaxTL);
|
|
SERIALIZE_ARRAY(tstate,MaxTL);
|
|
SERIALIZE_ARRAY(tt,MaxTL);
|
|
SERIALIZE_SCALAR(tba);
|
|
SERIALIZE_SCALAR(pstate);
|
|
SERIALIZE_SCALAR(tl);
|
|
SERIALIZE_SCALAR(pil);
|
|
SERIALIZE_SCALAR(cwp);
|
|
SERIALIZE_SCALAR(gl);
|
|
SERIALIZE_SCALAR(hpstate);
|
|
SERIALIZE_ARRAY(htstate,MaxTL);
|
|
SERIALIZE_SCALAR(hintp);
|
|
SERIALIZE_SCALAR(htba);
|
|
SERIALIZE_SCALAR(hstick_cmpr);
|
|
SERIALIZE_SCALAR(strandStatusReg);
|
|
SERIALIZE_SCALAR(fsr);
|
|
SERIALIZE_SCALAR(priContext);
|
|
SERIALIZE_SCALAR(secContext);
|
|
SERIALIZE_SCALAR(partId);
|
|
SERIALIZE_SCALAR(lsuCtrlReg);
|
|
SERIALIZE_ARRAY(scratchPad,8);
|
|
SERIALIZE_SCALAR(cpu_mondo_head);
|
|
SERIALIZE_SCALAR(cpu_mondo_tail);
|
|
SERIALIZE_SCALAR(dev_mondo_head);
|
|
SERIALIZE_SCALAR(dev_mondo_tail);
|
|
SERIALIZE_SCALAR(res_error_head);
|
|
SERIALIZE_SCALAR(res_error_tail);
|
|
SERIALIZE_SCALAR(nres_error_head);
|
|
SERIALIZE_SCALAR(nres_error_tail);
|
|
#if FULL_SYSTEM
|
|
Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0;
|
|
ThreadContext *tc = NULL;
|
|
BaseCPU *cpu = NULL;
|
|
int tc_num = 0;
|
|
bool tick_intr_sched = true;
|
|
|
|
if (tickCompare)
|
|
tc = tickCompare->getTC();
|
|
else if (sTickCompare)
|
|
tc = sTickCompare->getTC();
|
|
else if (hSTickCompare)
|
|
tc = hSTickCompare->getTC();
|
|
else
|
|
tick_intr_sched = false;
|
|
|
|
SERIALIZE_SCALAR(tick_intr_sched);
|
|
|
|
if (tc) {
|
|
cpu = tc->getCpuPtr();
|
|
tc_num = cpu->findContext(tc);
|
|
if (tickCompare && tickCompare->scheduled())
|
|
tick_cmp = tickCompare->when();
|
|
if (sTickCompare && sTickCompare->scheduled())
|
|
stick_cmp = sTickCompare->when();
|
|
if (hSTickCompare && hSTickCompare->scheduled())
|
|
hstick_cmp = hSTickCompare->when();
|
|
|
|
SERIALIZE_OBJPTR(cpu);
|
|
SERIALIZE_SCALAR(tc_num);
|
|
SERIALIZE_SCALAR(tick_cmp);
|
|
SERIALIZE_SCALAR(stick_cmp);
|
|
SERIALIZE_SCALAR(hstick_cmp);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
void
|
|
ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string §ion)
|
|
{
|
|
UNSERIALIZE_SCALAR(asi);
|
|
UNSERIALIZE_SCALAR(tick);
|
|
UNSERIALIZE_SCALAR(fprs);
|
|
UNSERIALIZE_SCALAR(gsr);
|
|
UNSERIALIZE_SCALAR(softint);
|
|
UNSERIALIZE_SCALAR(tick_cmpr);
|
|
UNSERIALIZE_SCALAR(stick);
|
|
UNSERIALIZE_SCALAR(stick_cmpr);
|
|
UNSERIALIZE_ARRAY(tpc,MaxTL);
|
|
UNSERIALIZE_ARRAY(tnpc,MaxTL);
|
|
UNSERIALIZE_ARRAY(tstate,MaxTL);
|
|
UNSERIALIZE_ARRAY(tt,MaxTL);
|
|
UNSERIALIZE_SCALAR(tba);
|
|
UNSERIALIZE_SCALAR(pstate);
|
|
UNSERIALIZE_SCALAR(tl);
|
|
UNSERIALIZE_SCALAR(pil);
|
|
UNSERIALIZE_SCALAR(cwp);
|
|
UNSERIALIZE_SCALAR(gl);
|
|
reloadRegMap();
|
|
UNSERIALIZE_SCALAR(hpstate);
|
|
UNSERIALIZE_ARRAY(htstate,MaxTL);
|
|
UNSERIALIZE_SCALAR(hintp);
|
|
UNSERIALIZE_SCALAR(htba);
|
|
UNSERIALIZE_SCALAR(hstick_cmpr);
|
|
UNSERIALIZE_SCALAR(strandStatusReg);
|
|
UNSERIALIZE_SCALAR(fsr);
|
|
UNSERIALIZE_SCALAR(priContext);
|
|
UNSERIALIZE_SCALAR(secContext);
|
|
UNSERIALIZE_SCALAR(partId);
|
|
UNSERIALIZE_SCALAR(lsuCtrlReg);
|
|
UNSERIALIZE_ARRAY(scratchPad,8);
|
|
UNSERIALIZE_SCALAR(cpu_mondo_head);
|
|
UNSERIALIZE_SCALAR(cpu_mondo_tail);
|
|
UNSERIALIZE_SCALAR(dev_mondo_head);
|
|
UNSERIALIZE_SCALAR(dev_mondo_tail);
|
|
UNSERIALIZE_SCALAR(res_error_head);
|
|
UNSERIALIZE_SCALAR(res_error_tail);
|
|
UNSERIALIZE_SCALAR(nres_error_head);
|
|
UNSERIALIZE_SCALAR(nres_error_tail);
|
|
|
|
#if FULL_SYSTEM
|
|
Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0;
|
|
ThreadContext *tc = NULL;
|
|
BaseCPU *cpu = NULL;
|
|
int tc_num;
|
|
bool tick_intr_sched;
|
|
UNSERIALIZE_SCALAR(tick_intr_sched);
|
|
if (tick_intr_sched) {
|
|
UNSERIALIZE_OBJPTR(cpu);
|
|
if (cpu) {
|
|
UNSERIALIZE_SCALAR(tc_num);
|
|
UNSERIALIZE_SCALAR(tick_cmp);
|
|
UNSERIALIZE_SCALAR(stick_cmp);
|
|
UNSERIALIZE_SCALAR(hstick_cmp);
|
|
tc = cpu->getContext(tc_num);
|
|
|
|
if (tick_cmp) {
|
|
tickCompare = new TickCompareEvent(this, tc);
|
|
em->schedule(tickCompare, tick_cmp);
|
|
}
|
|
if (stick_cmp) {
|
|
sTickCompare = new STickCompareEvent(this, tc);
|
|
em->schedule(sTickCompare, stick_cmp);
|
|
}
|
|
if (hstick_cmp) {
|
|
hSTickCompare = new HSTickCompareEvent(this, tc);
|
|
em->schedule(hSTickCompare, hstick_cmp);
|
|
}
|
|
}
|
|
}
|
|
|
|
#endif
|
|
}
|
|
|
|
}
|