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gem5/src/sim
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Korey Sewell c355df5bfe Fix so that O3CPU doesnt segfault on exit. 
Major thing was to not execute commit if there are no active threads in CPU.

src/cpu/o3/alpha/thread_context.hh:
    call deallocate instead of deallocateContext
src/cpu/o3/commit_impl.hh:
    dont run commit stage if there are no instructions
src/cpu/o3/cpu.cc:
    add deallocate event, deactivateThread function, and edit deallocateContext.
src/cpu/o3/cpu.hh:
    add deallocate event and add optional delay to deallocateContext
src/cpu/o3/thread_context.hh:
    optional delay for deallocate
src/cpu/o3/thread_context_impl.hh:
    edit DPRINTFs to say Thread Context instead of Alpha TC
src/cpu/thread_context.hh:
    optional delay
src/sim/syscall_emul.hh:
    name stuff

--HG--
extra : convert_revision : f4033e1f66b3043d30ad98dcc70d8b193dea70b6
2006-07-07 04:06:26 -04:00
..
async.hh Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
builder.cc Move SimObject creation and Port connection loops 2006-06-13 23:19:28 -04:00
builder.hh Move SimObject creation and Port connection loops 2006-06-13 23:19:28 -04:00
byteswap.hh include misc.hh for panic 2006-06-17 19:18:53 -04:00
debug.cc remove extern "C" from the functions we all from gdb. This isn't requried and trips up GDB sometimes when i thinks the extern 2006-06-26 17:49:49 -04:00
debug.hh Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
eventq.cc Move main control from C++ into Python. 2006-06-09 23:01:31 -04:00
eventq.hh Move main control from C++ into Python. 2006-06-09 23:01:31 -04:00
faults.cc Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh. 2006-06-06 17:32:21 -04:00
faults.hh add syscall emulation page table fault so we can allocate more stack pages 2006-06-26 16:49:05 -04:00
host.hh Move main control from C++ into Python. 2006-06-09 23:01:31 -04:00
main.cc Rename quiesce to drain to avoid confusion with the pseudo instruction. 2006-07-05 17:59:33 -04:00
param.cc Move SimObject creation and Port connection loops 2006-06-13 23:19:28 -04:00
param.hh Move SimObject creation and Port connection loops 2006-06-13 23:19:28 -04:00
process.cc Make O3CPU model independent of the ISA 2006-06-30 19:52:08 -04:00
process.hh Move LiveProcess::create() from arch-specific files 2006-06-11 21:49:46 -04:00
pseudo_inst.cc For now using the checkpoint or switchcpu pseudo instructions will return control to Python, returning the cause to be the instruction name. The user's script must then interpret the reason for exiting the simulation loop and handle the action accordingly. This may change in the future. 2006-07-05 23:38:11 -04:00
pseudo_inst.hh Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh. 2006-06-06 17:32:21 -04:00
root.cc Move main control from C++ into Python. 2006-06-09 23:01:31 -04:00
serialize.cc Add in support for quiescing the system, taking checkpoints, restoring from checkpoints, changing memory modes, and switching CPUs. 2006-06-29 19:40:12 -04:00
serialize.hh Remove function that no longer can be used. We should figure out if we want to allow the m5checkpoint pseudoinstruction or not. 2006-06-29 21:34:01 -04:00
sim_events.cc Rename quiesce to drain to avoid confusion with the pseudo instruction. 2006-07-05 17:59:33 -04:00
sim_events.hh Rename quiesce to drain to avoid confusion with the pseudo instruction. 2006-07-05 17:59:33 -04:00
sim_exit.hh Move main control from C++ into Python. 2006-06-09 23:01:31 -04:00
sim_object.cc Remove sampler and serializer. Now they are handled through C++ interacting with Python. 2006-07-05 21:14:36 -04:00
sim_object.hh Rename quiesce to drain to avoid confusion with the pseudo instruction. 2006-07-05 17:59:33 -04:00
startup.cc Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
startup.hh Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
stat_control.cc remove extern "C" from the functions we all from gdb. This isn't requried and trips up GDB sometimes when i thinks the extern 2006-06-26 17:49:49 -04:00
stat_control.hh Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
stats.hh Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
syscall_emul.cc Fix for FS O3CPU compile ... missing forward class declaration/header file after files got split for ISA-independence 2006-07-03 12:19:35 -04:00
syscall_emul.hh Fix so that O3CPU doesnt segfault on exit. 2006-07-07 04:06:26 -04:00
system.cc remove extern "C" from the functions we all from gdb. This isn't requried and trips up GDB sometimes when i thinks the extern 2006-06-26 17:49:49 -04:00
system.hh Merge iceaxe.:/Volumes/work/research/m5/head 2006-06-11 22:01:34 -04:00
vptr.hh Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh. 2006-06-06 17:32:21 -04:00