d2b57a7473
This patch simply bumps the stats to reflect the introduction of a bandwidth limit of 12.8GB/s for SimpleMemory.
1710 lines
197 KiB
Text
1710 lines
197 KiB
Text
|
|
---------- Begin Simulation Statistics ----------
|
|
sim_seconds 2.617165 # Number of seconds simulated
|
|
sim_ticks 2617165375500 # Number of ticks simulated
|
|
final_tick 2617165375500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
host_inst_rate 89131 # Simulator instruction rate (inst/s)
|
|
host_op_rate 114699 # Simulator op (including micro ops) rate (op/s)
|
|
host_tick_rate 3698456604 # Simulator tick rate (ticks/s)
|
|
host_mem_usage 391036 # Number of bytes of host memory used
|
|
host_seconds 707.64 # Real time elapsed on the host
|
|
sim_insts 63072219 # Number of instructions simulated
|
|
sim_ops 81165616 # Number of ops (including micro ops) simulated
|
|
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.bw_read::cpu0.inst 24 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::total 171 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu0.inst 24 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu1.inst 147 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::total 171 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu0.inst 24 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::total 171 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu0.inst 388160 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu0.data 4317812 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu1.inst 434112 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu1.data 5305072 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::total 131557540 # Number of bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu0.inst 388160 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu1.inst 434112 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::total 822272 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_written::writebacks 4272576 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::total 7301712 # Number of bytes written to this memory
|
|
system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu0.dtb.walker 9 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu0.inst 6065 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu0.data 67538 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu1.inst 6783 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu1.data 82918 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::total 15302149 # Number of read requests responded to by this memory
|
|
system.physmem.num_writes::writebacks 66759 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::total 824043 # Number of write requests responded to by this memory
|
|
system.physmem.bw_read::realview.clcd 46275459 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu0.dtb.walker 220 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu0.itb.walker 24 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu0.inst 148313 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu0.data 1649805 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu1.dtb.walker 440 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu1.itb.walker 24 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu1.inst 165871 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu1.data 2027030 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::total 50267186 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu0.inst 148313 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu1.inst 165871 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::total 314184 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::writebacks 1632520 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::cpu0.data 6496 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::cpu1.data 1150915 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::total 2789931 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_total::writebacks 1632520 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::realview.clcd 46275459 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu0.dtb.walker 220 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu0.itb.walker 24 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu0.inst 148313 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu0.data 1656300 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu1.dtb.walker 440 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu1.itb.walker 24 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu1.inst 165871 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu1.data 3177945 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::total 53057118 # Total bandwidth to/from this memory (bytes/s)
|
|
system.l2c.replacements 72943 # number of replacements
|
|
system.l2c.tagsinuse 53116.867697 # Cycle average of tags in use
|
|
system.l2c.total_refs 1971460 # Total number of references to valid blocks.
|
|
system.l2c.sampled_refs 138142 # Sample count of references to valid blocks.
|
|
system.l2c.avg_refs 14.271257 # Average number of references to valid blocks.
|
|
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.occ_blocks::writebacks 37786.311031 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu0.dtb.walker 4.267723 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu0.itb.walker 0.000236 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu0.inst 4199.901742 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu0.data 2938.535340 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu1.dtb.walker 12.943065 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu1.itb.walker 0.004375 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu1.inst 4043.458423 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu1.data 4131.445760 # Average occupied blocks per requestor
|
|
system.l2c.occ_percent::writebacks 0.576573 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu0.dtb.walker 0.000065 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu0.inst 0.064085 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu0.data 0.044838 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu1.dtb.walker 0.000197 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu1.inst 0.061698 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu1.data 0.063041 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::total 0.810499 # Average percentage of cache occupancy
|
|
system.l2c.ReadReq_hits::cpu0.dtb.walker 37150 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.itb.walker 4929 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.inst 329878 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.data 130970 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.dtb.walker 97479 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.itb.walker 7353 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.inst 687490 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.data 235857 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 1531106 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::writebacks 583482 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 583482 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 871 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 957 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 1828 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu0.data 218 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu1.data 135 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 353 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 38368 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 68483 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 106851 # number of ReadExReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 37150 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 4929 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 329878 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 169338 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.dtb.walker 97479 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.itb.walker 7353 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 687490 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 304340 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 1637957 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.dtb.walker 37150 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.itb.walker 4929 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.inst 329878 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 169338 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.dtb.walker 97479 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.itb.walker 7353 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 687490 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 304340 # number of overall hits
|
|
system.l2c.overall_hits::total 1637957 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.dtb.walker 9 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.inst 5936 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.data 6281 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.dtb.walker 18 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.inst 6745 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.data 6387 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 25378 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_misses::cpu0.data 4577 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 5411 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 9988 # number of UpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu0.data 789 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu1.data 588 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 1377 # number of SCUpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 62166 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 78219 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 140385 # number of ReadExReq misses
|
|
system.l2c.demand_misses::cpu0.dtb.walker 9 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.inst 5936 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 68447 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.dtb.walker 18 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 6745 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 84606 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 165763 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.dtb.walker 9 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.inst 5936 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 68447 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.dtb.walker 18 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 6745 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 84606 # number of overall misses
|
|
system.l2c.overall_misses::total 165763 # number of overall misses
|
|
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 470500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 60000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.inst 316492998 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.data 329723499 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 951500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.itb.walker 52000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.inst 358728999 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.data 335824498 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::total 1342303994 # number of ReadReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu0.data 17317975 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 30484500 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::total 47802475 # number of UpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1723000 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6877500 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::total 8600500 # number of SCUpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 3309650478 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 4148841993 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 7458492471 # number of ReadExReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.dtb.walker 470500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.itb.walker 60000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 316492998 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 3639373977 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.dtb.walker 951500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.itb.walker 52000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 358728999 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 4484666491 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 8800796465 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.dtb.walker 470500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.itb.walker 60000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 316492998 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 3639373977 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.dtb.walker 951500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.itb.walker 52000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 358728999 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 4484666491 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 8800796465 # number of overall miss cycles
|
|
system.l2c.ReadReq_accesses::cpu0.dtb.walker 37159 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.itb.walker 4930 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.inst 335814 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.data 137251 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.dtb.walker 97497 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.itb.walker 7354 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.inst 694235 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.data 242244 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 1556484 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::writebacks 583482 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 583482 # number of Writeback accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 5448 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 6368 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 11816 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu0.data 1007 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu1.data 723 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 1730 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 100534 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 146702 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 247236 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.dtb.walker 37159 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.itb.walker 4930 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.inst 335814 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 237785 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.dtb.walker 97497 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.itb.walker 7354 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 694235 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 388946 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 1803720 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.dtb.walker 37159 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.itb.walker 4930 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 335814 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 237785 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.dtb.walker 97497 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.itb.walker 7354 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 694235 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 388946 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 1803720 # number of overall (read+write) accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000242 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000203 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.inst 0.017676 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.data 0.045763 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000185 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000136 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.inst 0.009716 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.data 0.026366 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::total 0.016305 # miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.840125 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.849717 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.845295 # miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.783515 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.813278 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::total 0.795954 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.618358 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.533183 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.567818 # miss rate for ReadExReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000242 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000203 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.017676 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.287852 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000185 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.itb.walker 0.000136 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.009716 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.217526 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.091901 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000242 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000203 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.017676 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.287852 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000185 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.itb.walker 0.000136 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.009716 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.217526 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.091901 # miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52277.777778 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 60000 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53317.553571 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52495.382742 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52861.111111 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52000 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53184.432765 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.data 52579.379677 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::total 52892.426275 # average ReadReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3783.695652 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5633.801515 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 4785.990689 # average UpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2183.776933 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11696.428571 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::total 6245.824256 # average SCUpgradeReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53238.916417 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53041.358148 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 53128.841906 # average ReadExReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52277.777778 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 60000 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.inst 53317.553571 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.data 53170.686473 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52861.111111 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 53184.432765 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 53006.482885 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 53092.647123 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52277.777778 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 60000 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.inst 53317.553571 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.data 53170.686473 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52861.111111 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 53184.432765 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 53006.482885 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 53092.647123 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.writebacks::writebacks 66759 # number of writebacks
|
|
system.l2c.writebacks::total 66759 # number of writebacks
|
|
system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu0.data 40 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu1.data 24 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu0.data 40 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1.data 24 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu0.data 40 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1.data 24 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::total 75 # number of overall MSHR hits
|
|
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 9 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu0.inst 5932 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu0.data 6241 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 18 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.inst 6738 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.data 6363 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::total 25303 # number of ReadReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu0.data 4577 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 5411 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 9988 # number of UpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 789 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 588 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::total 1377 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu0.data 62166 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 78219 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 140385 # number of ReadExReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.dtb.walker 9 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.inst 5932 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.data 68407 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.dtb.walker 18 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 6738 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 84582 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 165688 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.dtb.walker 9 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.inst 5932 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.data 68407 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.dtb.walker 18 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 6738 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 84582 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 165688 # number of overall MSHR misses
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 360000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 48000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 243887498 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 252067500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 733500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 40000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 276182999 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 257217500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::total 1030536997 # number of ReadReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 183213000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 216585500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 399798500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 31577000 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 23526500 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::total 55103500 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2553542997 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3188267494 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 5741810491 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 360000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 48000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.inst 243887498 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.data 2805610497 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 733500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 40000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 276182999 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 3445484994 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 6772347488 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 360000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 48000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.inst 243887498 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.data 2805610497 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 733500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 40000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 276182999 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 3445484994 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 6772347488 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5576000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 11089188500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2170500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 155938912500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 167035847500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1148012499 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31165946489 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::total 32313958988 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5576000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 12237200999 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2170500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 187104858989 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::total 199349806488 # number of overall MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000242 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000203 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.017665 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.045471 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000185 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000136 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009706 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.026267 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.016257 # mshr miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.840125 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.849717 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.845295 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.783515 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.813278 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.795954 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.618358 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.533183 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.567818 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000242 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000203 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.017665 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.287684 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000185 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000136 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009706 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.217465 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.091859 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000242 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000203 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.017665 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.287684 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000185 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000136 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009706 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.217465 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.091859 # mshr miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41113.873567 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40388.960103 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40988.868952 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40423.935251 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 40727.858238 # average ReadReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40029.058335 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40026.889669 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40027.883460 # average UpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40021.546261 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40011.054422 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40017.066086 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41076.199160 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40760.780552 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40900.455825 # average ReadExReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41113.873567 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41013.500037 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40988.868952 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40735.440094 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 40874.097629 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41113.873567 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41013.500037 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40988.868952 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40735.440094 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 40874.097629 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
|
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dtb.read_hits 7439931 # DTB read hits
|
|
system.cpu0.dtb.read_misses 24509 # DTB read misses
|
|
system.cpu0.dtb.write_hits 4439969 # DTB write hits
|
|
system.cpu0.dtb.write_misses 3332 # DTB write misses
|
|
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dtb.flush_entries 2072 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dtb.align_faults 1349 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dtb.prefetch_faults 232 # Number of TLB faults due to prefetch
|
|
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dtb.perms_faults 509 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dtb.read_accesses 7464440 # DTB read accesses
|
|
system.cpu0.dtb.write_accesses 4443301 # DTB write accesses
|
|
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dtb.hits 11879900 # DTB hits
|
|
system.cpu0.dtb.misses 27841 # DTB misses
|
|
system.cpu0.dtb.accesses 11907741 # DTB accesses
|
|
system.cpu0.itb.inst_hits 3552097 # ITB inst hits
|
|
system.cpu0.itb.inst_misses 3937 # ITB inst misses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu0.itb.flush_entries 1380 # Number of entries that have been flushed from TLB
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.itb.perms_faults 929 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.inst_accesses 3556034 # ITB inst accesses
|
|
system.cpu0.itb.hits 3552097 # DTB hits
|
|
system.cpu0.itb.misses 3937 # DTB misses
|
|
system.cpu0.itb.accesses 3556034 # DTB accesses
|
|
system.cpu0.numCycles 63548405 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.BPredUnit.lookups 5090505 # Number of BP lookups
|
|
system.cpu0.BPredUnit.condPredicted 3902323 # Number of conditional branches predicted
|
|
system.cpu0.BPredUnit.condIncorrect 231356 # Number of conditional branches incorrect
|
|
system.cpu0.BPredUnit.BTBLookups 3310708 # Number of BTB lookups
|
|
system.cpu0.BPredUnit.BTBHits 2517095 # Number of BTB hits
|
|
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu0.BPredUnit.usedRAS 576022 # Number of times the RAS was used to get a target.
|
|
system.cpu0.BPredUnit.RASInCorrect 23707 # Number of incorrect RAS predictions.
|
|
system.cpu0.fetch.icacheStallCycles 10651881 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu0.fetch.Insts 26843573 # Number of instructions fetch has processed
|
|
system.cpu0.fetch.Branches 5090505 # Number of branches that fetch encountered
|
|
system.cpu0.fetch.predictedBranches 3093117 # Number of branches that fetch has predicted taken
|
|
system.cpu0.fetch.Cycles 6356133 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu0.fetch.SquashCycles 1209317 # Number of cycles fetch has spent squashing
|
|
system.cpu0.fetch.TlbCycles 66372 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu0.fetch.BlockedCycles 20477375 # Number of cycles fetch has spent blocked
|
|
system.cpu0.fetch.MiscStallCycles 5743 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu0.fetch.PendingTrapStallCycles 36616 # Number of stall cycles due to pending traps
|
|
system.cpu0.fetch.PendingQuiesceStallCycles 72183 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu0.fetch.IcacheWaitRetryStallCycles 198 # Number of stall cycles due to full MSHR
|
|
system.cpu0.fetch.CacheLines 3550824 # Number of cache lines fetched
|
|
system.cpu0.fetch.IcacheSquashes 136175 # Number of outstanding Icache misses that were squashed
|
|
system.cpu0.fetch.ItlbSquashes 2156 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu0.fetch.rateDist::samples 38533087 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::mean 0.905766 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::stdev 2.281431 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::0 32183362 83.52% 83.52% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::1 497864 1.29% 84.81% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::2 649099 1.68% 86.50% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::3 569855 1.48% 87.98% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::4 713173 1.85% 89.83% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::5 461238 1.20% 91.02% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::6 562037 1.46% 92.48% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::7 306432 0.80% 93.28% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::8 2590027 6.72% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::total 38533087 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.branchRate 0.080104 # Number of branch fetches per cycle
|
|
system.cpu0.fetch.rate 0.422411 # Number of inst fetches per cycle
|
|
system.cpu0.decode.IdleCycles 11016691 # Number of cycles decode is idle
|
|
system.cpu0.decode.BlockedCycles 20495843 # Number of cycles decode is blocked
|
|
system.cpu0.decode.RunCycles 5693231 # Number of cycles decode is running
|
|
system.cpu0.decode.UnblockCycles 512184 # Number of cycles decode is unblocking
|
|
system.cpu0.decode.SquashCycles 815138 # Number of cycles decode is squashing
|
|
system.cpu0.decode.BranchResolved 784502 # Number of times decode resolved a branch
|
|
system.cpu0.decode.BranchMispred 52422 # Number of times decode detected a branch misprediction
|
|
system.cpu0.decode.DecodedInsts 33794983 # Number of instructions handled by decode
|
|
system.cpu0.decode.SquashedInsts 170156 # Number of squashed instructions handled by decode
|
|
system.cpu0.rename.SquashCycles 815138 # Number of cycles rename is squashing
|
|
system.cpu0.rename.IdleCycles 11512212 # Number of cycles rename is idle
|
|
system.cpu0.rename.BlockCycles 6110309 # Number of cycles rename is blocking
|
|
system.cpu0.rename.serializeStallCycles 12456624 # count of cycles rename stalled for serializing inst
|
|
system.cpu0.rename.RunCycles 5662288 # Number of cycles rename is running
|
|
system.cpu0.rename.UnblockCycles 1976516 # Number of cycles rename is unblocking
|
|
system.cpu0.rename.RenamedInsts 32836773 # Number of instructions processed by rename
|
|
system.cpu0.rename.ROBFullEvents 1958 # Number of times rename has blocked due to ROB full
|
|
system.cpu0.rename.IQFullEvents 434728 # Number of times rename has blocked due to IQ full
|
|
system.cpu0.rename.LSQFullEvents 1081609 # Number of times rename has blocked due to LSQ full
|
|
system.cpu0.rename.FullRegisterEvents 147 # Number of times there has been no free registers
|
|
system.cpu0.rename.RenamedOperands 32827027 # Number of destination operands rename has renamed
|
|
system.cpu0.rename.RenameLookups 148293172 # Number of register rename lookups that rename has made
|
|
system.cpu0.rename.int_rename_lookups 148253410 # Number of integer rename lookups
|
|
system.cpu0.rename.fp_rename_lookups 39762 # Number of floating rename lookups
|
|
system.cpu0.rename.CommittedMaps 25938752 # Number of HB maps that are committed
|
|
system.cpu0.rename.UndoneMaps 6888275 # Number of HB maps that are undone due to squashing
|
|
system.cpu0.rename.serializingInsts 379434 # count of serializing insts renamed
|
|
system.cpu0.rename.tempSerializingInsts 344458 # count of temporary serializing insts renamed
|
|
system.cpu0.rename.skidInsts 4684493 # count of insts added to the skid buffer
|
|
system.cpu0.memDep0.insertedLoads 6313022 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.insertedStores 4948082 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.conflictingLoads 931233 # Number of conflicting loads.
|
|
system.cpu0.memDep0.conflictingStores 932024 # Number of conflicting stores.
|
|
system.cpu0.iq.iqInstsAdded 31038582 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu0.iq.iqNonSpecInstsAdded 848484 # Number of non-speculative instructions added to the IQ
|
|
system.cpu0.iq.iqInstsIssued 31613010 # Number of instructions issued
|
|
system.cpu0.iq.iqSquashedInstsIssued 68951 # Number of squashed instructions issued
|
|
system.cpu0.iq.iqSquashedInstsExamined 5311616 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu0.iq.iqSquashedOperandsExamined 10469723 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu0.iq.iqSquashedNonSpecRemoved 281141 # Number of squashed non-spec instructions that were removed
|
|
system.cpu0.iq.issued_per_cycle::samples 38533087 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::mean 0.820412 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::stdev 1.447904 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::0 25332313 65.74% 65.74% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::1 5318332 13.80% 79.54% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::2 2653261 6.89% 86.43% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::3 2120070 5.50% 91.93% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::4 1758280 4.56% 96.49% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::5 743996 1.93% 98.43% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::6 416585 1.08% 99.51% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::7 146664 0.38% 99.89% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::8 43586 0.11% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::total 38533087 # Number of insts issued each cycle
|
|
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntAlu 17185 1.90% 1.90% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntMult 452 0.05% 1.95% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntDiv 0 0.00% 1.95% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 1.95% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 1.95% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 1.95% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatMult 0 0.00% 1.95% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 1.95% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 1.95% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 1.95% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 1.95% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 1.95% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 1.95% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 1.95% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 1.95% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMult 0 0.00% 1.95% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 1.95% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShift 0 0.00% 1.95% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 1.95% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 1.95% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 1.95% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 1.95% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 1.95% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 1.95% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 1.95% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 1.95% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 1.95% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.95% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 1.95% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemRead 711308 78.54% 80.49% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemWrite 176706 19.51% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.FU_type_0::No_OpClass 39793 0.13% 0.13% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntAlu 18975009 60.02% 60.15% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntMult 42063 0.13% 60.28% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.28% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.28% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.28% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.28% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.28% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.28% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.28% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.28% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.28% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.28% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.28% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.28% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMisc 2 0.00% 60.28% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.28% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.28% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.28% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShiftAcc 2 0.00% 60.28% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.28% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.28% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.28% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.28% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.28% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.28% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMisc 627 0.00% 60.28% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.28% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 60.28% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.28% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemRead 7818427 24.73% 85.02% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemWrite 4737084 14.98% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::total 31613010 # Type of FU issued
|
|
system.cpu0.iq.rate 0.497463 # Inst issue rate
|
|
system.cpu0.iq.fu_busy_cnt 905651 # FU busy when requested
|
|
system.cpu0.iq.fu_busy_rate 0.028648 # FU busy rate (busy events/executed inst)
|
|
system.cpu0.iq.int_inst_queue_reads 102751361 # Number of integer instruction queue reads
|
|
system.cpu0.iq.int_inst_queue_writes 37203152 # Number of integer instruction queue writes
|
|
system.cpu0.iq.int_inst_queue_wakeup_accesses 29110459 # Number of integer instruction queue wakeup accesses
|
|
system.cpu0.iq.fp_inst_queue_reads 9929 # Number of floating instruction queue reads
|
|
system.cpu0.iq.fp_inst_queue_writes 5392 # Number of floating instruction queue writes
|
|
system.cpu0.iq.fp_inst_queue_wakeup_accesses 4352 # Number of floating instruction queue wakeup accesses
|
|
system.cpu0.iq.int_alu_accesses 32473546 # Number of integer alu accesses
|
|
system.cpu0.iq.fp_alu_accesses 5322 # Number of floating point alu accesses
|
|
system.cpu0.iew.lsq.thread0.forwLoads 253493 # Number of loads that had data forwarded from stores
|
|
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.squashedLoads 1084760 # Number of loads squashed
|
|
system.cpu0.iew.lsq.thread0.ignoredResponses 3550 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu0.iew.lsq.thread0.memOrderViolation 10332 # Number of memory ordering violations
|
|
system.cpu0.iew.lsq.thread0.squashedStores 476904 # Number of stores squashed
|
|
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu0.iew.lsq.thread0.rescheduledLoads 1893731 # Number of loads that were rescheduled
|
|
system.cpu0.iew.lsq.thread0.cacheBlocked 4858 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu0.iew.iewSquashCycles 815138 # Number of cycles IEW is squashing
|
|
system.cpu0.iew.iewBlockCycles 4299477 # Number of cycles IEW is blocking
|
|
system.cpu0.iew.iewUnblockCycles 104449 # Number of cycles IEW is unblocking
|
|
system.cpu0.iew.iewDispatchedInsts 31945570 # Number of instructions dispatched to IQ
|
|
system.cpu0.iew.iewDispSquashedInsts 72737 # Number of squashed instructions skipped by dispatch
|
|
system.cpu0.iew.iewDispLoadInsts 6313022 # Number of dispatched load instructions
|
|
system.cpu0.iew.iewDispStoreInsts 4948082 # Number of dispatched store instructions
|
|
system.cpu0.iew.iewDispNonSpecInsts 576088 # Number of dispatched non-speculative instructions
|
|
system.cpu0.iew.iewIQFullEvents 33936 # Number of times the IQ has become full, causing a stall
|
|
system.cpu0.iew.iewLSQFullEvents 17434 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu0.iew.memOrderViolationEvents 10332 # Number of memory order violations
|
|
system.cpu0.iew.predictedTakenIncorrect 115531 # Number of branches that were predicted taken incorrectly
|
|
system.cpu0.iew.predictedNotTakenIncorrect 108245 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu0.iew.branchMispredicts 223776 # Number of branch mispredicts detected at execute
|
|
system.cpu0.iew.iewExecutedInsts 31278568 # Number of executed instructions
|
|
system.cpu0.iew.iewExecLoadInsts 7699224 # Number of load instructions executed
|
|
system.cpu0.iew.iewExecSquashedInsts 334442 # Number of squashed instructions skipped in execute
|
|
system.cpu0.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu0.iew.exec_nop 58504 # number of nop insts executed
|
|
system.cpu0.iew.exec_refs 12394115 # number of memory reference insts executed
|
|
system.cpu0.iew.exec_branches 4158454 # Number of branches executed
|
|
system.cpu0.iew.exec_stores 4694891 # Number of stores executed
|
|
system.cpu0.iew.exec_rate 0.492201 # Inst execution rate
|
|
system.cpu0.iew.wb_sent 31120630 # cumulative count of insts sent to commit
|
|
system.cpu0.iew.wb_count 29114811 # cumulative count of insts written-back
|
|
system.cpu0.iew.wb_producers 15418480 # num instructions producing a value
|
|
system.cpu0.iew.wb_consumers 29202336 # num instructions consuming a value
|
|
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu0.iew.wb_rate 0.458152 # insts written-back per cycle
|
|
system.cpu0.iew.wb_fanout 0.527988 # average fanout of values written-back
|
|
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu0.commit.commitSquashedInsts 5043051 # The number of squashed insts skipped by commit
|
|
system.cpu0.commit.commitNonSpecStalls 567343 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu0.commit.branchMispredicts 195875 # The number of times a branch was mispredicted
|
|
system.cpu0.commit.committed_per_cycle::samples 37746791 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::mean 0.699150 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::stdev 1.656907 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::0 27673007 73.31% 73.31% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::1 5099673 13.51% 86.82% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::2 1632700 4.33% 91.15% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::3 816219 2.16% 93.31% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::4 659263 1.75% 95.06% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::5 376754 1.00% 96.05% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::6 343613 0.91% 96.97% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::7 170043 0.45% 97.42% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::8 975519 2.58% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::total 37746791 # Number of insts commited each cycle
|
|
system.cpu0.commit.committedInsts 19900047 # Number of instructions committed
|
|
system.cpu0.commit.committedOps 26390683 # Number of ops (including micro ops) committed
|
|
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu0.commit.refs 9699440 # Number of memory references committed
|
|
system.cpu0.commit.loads 5228262 # Number of loads committed
|
|
system.cpu0.commit.membars 194354 # Number of memory barriers committed
|
|
system.cpu0.commit.branches 3620828 # Number of branches committed
|
|
system.cpu0.commit.fp_insts 4336 # Number of committed floating point instructions.
|
|
system.cpu0.commit.int_insts 23422561 # Number of committed integer instructions.
|
|
system.cpu0.commit.function_calls 422942 # Number of function calls committed.
|
|
system.cpu0.commit.bw_lim_events 975519 # number cycles where commit BW limit reached
|
|
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu0.rob.rob_reads 67501483 # The number of ROB reads
|
|
system.cpu0.rob.rob_writes 63684069 # The number of ROB writes
|
|
system.cpu0.timesIdled 366948 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu0.idleCycles 25015318 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu0.quiesceCycles 5170100782 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu0.committedInsts 19875493 # Number of Instructions Simulated
|
|
system.cpu0.committedOps 26366129 # Number of Ops (including micro ops) Simulated
|
|
system.cpu0.committedInsts_total 19875493 # Number of Instructions Simulated
|
|
system.cpu0.cpi 3.197325 # CPI: Cycles Per Instruction
|
|
system.cpu0.cpi_total 3.197325 # CPI: Total CPI of All Threads
|
|
system.cpu0.ipc 0.312761 # IPC: Instructions Per Cycle
|
|
system.cpu0.ipc_total 0.312761 # IPC: Total IPC of All Threads
|
|
system.cpu0.int_regfile_reads 145756307 # number of integer regfile reads
|
|
system.cpu0.int_regfile_writes 28747856 # number of integer regfile writes
|
|
system.cpu0.fp_regfile_reads 4243 # number of floating regfile reads
|
|
system.cpu0.fp_regfile_writes 404 # number of floating regfile writes
|
|
system.cpu0.misc_regfile_reads 38262536 # number of misc regfile reads
|
|
system.cpu0.misc_regfile_writes 444175 # number of misc regfile writes
|
|
system.cpu0.icache.replacements 335591 # number of replacements
|
|
system.cpu0.icache.tagsinuse 511.578004 # Cycle average of tags in use
|
|
system.cpu0.icache.total_refs 3187209 # Total number of references to valid blocks.
|
|
system.cpu0.icache.sampled_refs 336103 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.avg_refs 9.482834 # Average number of references to valid blocks.
|
|
system.cpu0.icache.warmup_cycle 7275076000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.occ_blocks::cpu0.inst 511.578004 # Average occupied blocks per requestor
|
|
system.cpu0.icache.occ_percent::cpu0.inst 0.999176 # Average percentage of cache occupancy
|
|
system.cpu0.icache.occ_percent::total 0.999176 # Average percentage of cache occupancy
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 3187209 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 3187209 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 3187209 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 3187209 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 3187209 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 3187209 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 363477 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 363477 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 363477 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 363477 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 363477 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 363477 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5925752494 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 5925752494 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 5925752494 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 5925752494 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 5925752494 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 5925752494 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 3550686 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 3550686 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 3550686 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 3550686 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 3550686 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 3550686 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.102368 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.102368 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.102368 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.102368 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.102368 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.102368 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16302.964133 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 16302.964133 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16302.964133 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 16302.964133 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16302.964133 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 16302.964133 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 1276494 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 156 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs 8182.653846 # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 27366 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::total 27366 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu0.inst 27366 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::total 27366 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu0.inst 27366 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::total 27366 # number of overall MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 336111 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 336111 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 336111 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 336111 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 336111 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 336111 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4556806494 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 4556806494 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4556806494 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 4556806494 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4556806494 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 4556806494 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8394000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8394000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8394000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::total 8394000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.094661 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.094661 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.094661 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.094661 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.094661 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.094661 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13557.445290 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13557.445290 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13557.445290 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13557.445290 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13557.445290 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13557.445290 # average overall mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.dcache.replacements 225959 # number of replacements
|
|
system.cpu0.dcache.tagsinuse 476.340528 # Cycle average of tags in use
|
|
system.cpu0.dcache.total_refs 7674381 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.sampled_refs 226327 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.avg_refs 33.908376 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.warmup_cycle 51455000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.occ_blocks::cpu0.data 476.340528 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.occ_percent::cpu0.data 0.930353 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.occ_percent::total 0.930353 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 4719087 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 4719087 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 2610456 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 2610456 # number of WriteReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 155489 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 155489 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 152427 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 152427 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 7329543 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 7329543 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 7329543 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 7329543 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 331165 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 331165 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 1441313 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 1441313 # number of WriteReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8607 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 8607 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7989 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 7989 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 1772478 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 1772478 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 1772478 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 1772478 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6024148000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 6024148000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 68192376390 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 68192376390 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 105659500 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 105659500 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 91795500 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 91795500 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 74216524390 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 74216524390 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 74216524390 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 74216524390 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 5050252 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 5050252 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4051769 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 4051769 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 164096 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 164096 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160416 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 160416 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 9102021 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 9102021 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 9102021 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 9102021 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.065574 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.065574 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.355724 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.355724 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.052451 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052451 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049802 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049802 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.194735 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.194735 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.194735 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.194735 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18190.774991 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 18190.774991 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 47312.676976 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 47312.676976 # average WriteReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12275.996282 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12275.996282 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11490.236575 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11490.236575 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41871.619501 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 41871.619501 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41871.619501 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 41871.619501 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 5649995 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 1774500 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 1210 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 93 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4669.417355 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets 19080.645161 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 209818 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 209818 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 177491 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 177491 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1323875 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::total 1323875 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 700 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 700 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1501366 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 1501366 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1501366 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 1501366 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 153674 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 153674 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 117438 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 117438 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7907 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7907 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7979 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 7979 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 271112 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 271112 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 271112 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 271112 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2311816775 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2311816775 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4408331005 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4408331005 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 70347504 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 70347504 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 66656537 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 66656537 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6720147780 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 6720147780 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6720147780 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 6720147780 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12100601500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12100601500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1292553399 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1292553399 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13393154899 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13393154899 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030429 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030429 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028984 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.028984 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048185 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.048185 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.049739 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.049739 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029786 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.029786 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029786 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.029786 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15043.642874 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15043.642874 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37537.517711 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37537.517711 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8896.864045 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8896.864045 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8353.996365 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8353.996365 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24787.349066 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24787.349066 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24787.349066 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24787.349066 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 45088968 # DTB read hits
|
|
system.cpu1.dtb.read_misses 60619 # DTB read misses
|
|
system.cpu1.dtb.write_hits 7938217 # DTB write hits
|
|
system.cpu1.dtb.write_misses 15813 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 2729 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 3748 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 541 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 727 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 45149587 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 7954030 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 53027185 # DTB hits
|
|
system.cpu1.dtb.misses 76432 # DTB misses
|
|
system.cpu1.dtb.accesses 53103617 # DTB accesses
|
|
system.cpu1.itb.inst_hits 10093689 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 8052 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 1586 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 2426 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 10101741 # ITB inst accesses
|
|
system.cpu1.itb.hits 10093689 # DTB hits
|
|
system.cpu1.itb.misses 8052 # DTB misses
|
|
system.cpu1.itb.accesses 10101741 # DTB accesses
|
|
system.cpu1.numCycles 430376404 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.BPredUnit.lookups 11102078 # Number of BP lookups
|
|
system.cpu1.BPredUnit.condPredicted 9036479 # Number of conditional branches predicted
|
|
system.cpu1.BPredUnit.condIncorrect 529963 # Number of conditional branches incorrect
|
|
system.cpu1.BPredUnit.BTBLookups 7542756 # Number of BTB lookups
|
|
system.cpu1.BPredUnit.BTBHits 6181694 # Number of BTB hits
|
|
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu1.BPredUnit.usedRAS 958293 # Number of times the RAS was used to get a target.
|
|
system.cpu1.BPredUnit.RASInCorrect 57467 # Number of incorrect RAS predictions.
|
|
system.cpu1.fetch.icacheStallCycles 24500240 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu1.fetch.Insts 78456444 # Number of instructions fetch has processed
|
|
system.cpu1.fetch.Branches 11102078 # Number of branches that fetch encountered
|
|
system.cpu1.fetch.predictedBranches 7139987 # Number of branches that fetch has predicted taken
|
|
system.cpu1.fetch.Cycles 16800094 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu1.fetch.SquashCycles 5031478 # Number of cycles fetch has spent squashing
|
|
system.cpu1.fetch.TlbCycles 107954 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu1.fetch.BlockedCycles 84138717 # Number of cycles fetch has spent blocked
|
|
system.cpu1.fetch.MiscStallCycles 5959 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu1.fetch.PendingTrapStallCycles 105572 # Number of stall cycles due to pending traps
|
|
system.cpu1.fetch.PendingQuiesceStallCycles 161210 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu1.fetch.IcacheWaitRetryStallCycles 156 # Number of stall cycles due to full MSHR
|
|
system.cpu1.fetch.CacheLines 10091008 # Number of cache lines fetched
|
|
system.cpu1.fetch.IcacheSquashes 896138 # Number of outstanding Icache misses that were squashed
|
|
system.cpu1.fetch.ItlbSquashes 4286 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu1.fetch.rateDist::samples 129269647 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::mean 0.735584 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::stdev 2.091589 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::0 112479856 87.01% 87.01% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::1 952035 0.74% 87.75% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::2 1186228 0.92% 88.67% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::3 2188812 1.69% 90.36% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::4 1732150 1.34% 91.70% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::5 728800 0.56% 92.26% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::6 2428875 1.88% 94.14% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::7 531185 0.41% 94.55% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::8 7041706 5.45% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::total 129269647 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.branchRate 0.025796 # Number of branch fetches per cycle
|
|
system.cpu1.fetch.rate 0.182297 # Number of inst fetches per cycle
|
|
system.cpu1.decode.IdleCycles 26260600 # Number of cycles decode is idle
|
|
system.cpu1.decode.BlockedCycles 83914684 # Number of cycles decode is blocked
|
|
system.cpu1.decode.RunCycles 15106265 # Number of cycles decode is running
|
|
system.cpu1.decode.UnblockCycles 652780 # Number of cycles decode is unblocking
|
|
system.cpu1.decode.SquashCycles 3335318 # Number of cycles decode is squashing
|
|
system.cpu1.decode.BranchResolved 1450901 # Number of times decode resolved a branch
|
|
system.cpu1.decode.BranchMispred 116510 # Number of times decode detected a branch misprediction
|
|
system.cpu1.decode.DecodedInsts 88966869 # Number of instructions handled by decode
|
|
system.cpu1.decode.SquashedInsts 389379 # Number of squashed instructions handled by decode
|
|
system.cpu1.rename.SquashCycles 3335318 # Number of cycles rename is squashing
|
|
system.cpu1.rename.IdleCycles 27931781 # Number of cycles rename is idle
|
|
system.cpu1.rename.BlockCycles 34696050 # Number of cycles rename is blocking
|
|
system.cpu1.rename.serializeStallCycles 44327698 # count of cycles rename stalled for serializing inst
|
|
system.cpu1.rename.RunCycles 14003132 # Number of cycles rename is running
|
|
system.cpu1.rename.UnblockCycles 4975668 # Number of cycles rename is unblocking
|
|
system.cpu1.rename.RenamedInsts 82212740 # Number of instructions processed by rename
|
|
system.cpu1.rename.ROBFullEvents 21319 # Number of times rename has blocked due to ROB full
|
|
system.cpu1.rename.IQFullEvents 759400 # Number of times rename has blocked due to IQ full
|
|
system.cpu1.rename.LSQFullEvents 3532141 # Number of times rename has blocked due to LSQ full
|
|
system.cpu1.rename.FullRegisterEvents 33925 # Number of times there has been no free registers
|
|
system.cpu1.rename.RenamedOperands 86942184 # Number of destination operands rename has renamed
|
|
system.cpu1.rename.RenameLookups 378153831 # Number of register rename lookups that rename has made
|
|
system.cpu1.rename.int_rename_lookups 378105448 # Number of integer rename lookups
|
|
system.cpu1.rename.fp_rename_lookups 48383 # Number of floating rename lookups
|
|
system.cpu1.rename.CommittedMaps 55944710 # Number of HB maps that are committed
|
|
system.cpu1.rename.UndoneMaps 30997473 # Number of HB maps that are undone due to squashing
|
|
system.cpu1.rename.serializingInsts 570448 # count of serializing insts renamed
|
|
system.cpu1.rename.tempSerializingInsts 494970 # count of temporary serializing insts renamed
|
|
system.cpu1.rename.skidInsts 9410070 # count of insts added to the skid buffer
|
|
system.cpu1.memDep0.insertedLoads 15640035 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.insertedStores 9547074 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.conflictingLoads 1284923 # Number of conflicting loads.
|
|
system.cpu1.memDep0.conflictingStores 1813164 # Number of conflicting stores.
|
|
system.cpu1.iq.iqInstsAdded 74425843 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu1.iq.iqNonSpecInstsAdded 1310750 # Number of non-speculative instructions added to the IQ
|
|
system.cpu1.iq.iqInstsIssued 98630822 # Number of instructions issued
|
|
system.cpu1.iq.iqSquashedInstsIssued 132915 # Number of squashed instructions issued
|
|
system.cpu1.iq.iqSquashedInstsExamined 20366425 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu1.iq.iqSquashedOperandsExamined 57377380 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu1.iq.iqSquashedNonSpecRemoved 269048 # Number of squashed non-spec instructions that were removed
|
|
system.cpu1.iq.issued_per_cycle::samples 129269647 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::mean 0.762985 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::stdev 1.495609 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::0 94766617 73.31% 73.31% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::1 10139907 7.84% 81.15% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::2 5158815 3.99% 85.14% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::3 4427747 3.43% 88.57% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::4 11055431 8.55% 97.12% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::5 2157635 1.67% 98.79% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::6 1155512 0.89% 99.68% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::7 316791 0.25% 99.93% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::8 91192 0.07% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::total 129269647 # Number of insts issued each cycle
|
|
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntAlu 39597 0.49% 0.49% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntMult 1008 0.01% 0.50% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.50% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.50% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.50% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.50% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.50% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.50% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.50% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.50% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.50% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.50% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.50% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.50% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.50% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.50% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.50% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.50% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.50% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.50% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.50% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.50% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.50% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.50% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.50% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.50% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.50% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.50% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.50% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemRead 7696421 95.46% 95.96% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemWrite 325487 4.04% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.FU_type_0::No_OpClass 326092 0.33% 0.33% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntAlu 43501050 44.10% 44.44% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntMult 69634 0.07% 44.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 44.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 44.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 44.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 44.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 44.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 44.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 44.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 44.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 44.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 44.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 44.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 44.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMisc 16 0.00% 44.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 44.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 44.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShift 6 0.00% 44.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 44.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 44.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 44.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 44.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 44.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 44.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 44.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMisc 1718 0.00% 44.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 44.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 44.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 44.51% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemRead 46384595 47.03% 91.54% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemWrite 8347697 8.46% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::total 98630822 # Type of FU issued
|
|
system.cpu1.iq.rate 0.229173 # Inst issue rate
|
|
system.cpu1.iq.fu_busy_cnt 8062513 # FU busy when requested
|
|
system.cpu1.iq.fu_busy_rate 0.081744 # FU busy rate (busy events/executed inst)
|
|
system.cpu1.iq.int_inst_queue_reads 334791339 # Number of integer instruction queue reads
|
|
system.cpu1.iq.int_inst_queue_writes 96121166 # Number of integer instruction queue writes
|
|
system.cpu1.iq.int_inst_queue_wakeup_accesses 62008917 # Number of integer instruction queue wakeup accesses
|
|
system.cpu1.iq.fp_inst_queue_reads 11647 # Number of floating instruction queue reads
|
|
system.cpu1.iq.fp_inst_queue_writes 6672 # Number of floating instruction queue writes
|
|
system.cpu1.iq.fp_inst_queue_wakeup_accesses 5500 # Number of floating instruction queue wakeup accesses
|
|
system.cpu1.iq.int_alu_accesses 106361230 # Number of integer alu accesses
|
|
system.cpu1.iq.fp_alu_accesses 6013 # Number of floating point alu accesses
|
|
system.cpu1.iew.lsq.thread0.forwLoads 441985 # Number of loads that had data forwarded from stores
|
|
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.squashedLoads 4452276 # Number of loads squashed
|
|
system.cpu1.iew.lsq.thread0.ignoredResponses 7115 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu1.iew.lsq.thread0.memOrderViolation 25628 # Number of memory ordering violations
|
|
system.cpu1.iew.lsq.thread0.squashedStores 1723414 # Number of stores squashed
|
|
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu1.iew.lsq.thread0.rescheduledLoads 32221586 # Number of loads that were rescheduled
|
|
system.cpu1.iew.lsq.thread0.cacheBlocked 1050708 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu1.iew.iewSquashCycles 3335318 # Number of cycles IEW is squashing
|
|
system.cpu1.iew.iewBlockCycles 26012639 # Number of cycles IEW is blocking
|
|
system.cpu1.iew.iewUnblockCycles 434151 # Number of cycles IEW is unblocking
|
|
system.cpu1.iew.iewDispatchedInsts 75941872 # Number of instructions dispatched to IQ
|
|
system.cpu1.iew.iewDispSquashedInsts 151121 # Number of squashed instructions skipped by dispatch
|
|
system.cpu1.iew.iewDispLoadInsts 15640035 # Number of dispatched load instructions
|
|
system.cpu1.iew.iewDispStoreInsts 9547074 # Number of dispatched store instructions
|
|
system.cpu1.iew.iewDispNonSpecInsts 940187 # Number of dispatched non-speculative instructions
|
|
system.cpu1.iew.iewIQFullEvents 96009 # Number of times the IQ has become full, causing a stall
|
|
system.cpu1.iew.iewLSQFullEvents 15502 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu1.iew.memOrderViolationEvents 25628 # Number of memory order violations
|
|
system.cpu1.iew.predictedTakenIncorrect 268769 # Number of branches that were predicted taken incorrectly
|
|
system.cpu1.iew.predictedNotTakenIncorrect 233332 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu1.iew.branchMispredicts 502101 # Number of branch mispredicts detected at execute
|
|
system.cpu1.iew.iewExecutedInsts 95691641 # Number of executed instructions
|
|
system.cpu1.iew.iewExecLoadInsts 45532774 # Number of load instructions executed
|
|
system.cpu1.iew.iewExecSquashedInsts 2939181 # Number of squashed instructions skipped in execute
|
|
system.cpu1.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu1.iew.exec_nop 205279 # number of nop insts executed
|
|
system.cpu1.iew.exec_refs 53793996 # number of memory reference insts executed
|
|
system.cpu1.iew.exec_branches 8312135 # Number of branches executed
|
|
system.cpu1.iew.exec_stores 8261222 # Number of stores executed
|
|
system.cpu1.iew.exec_rate 0.222344 # Inst execution rate
|
|
system.cpu1.iew.wb_sent 94462198 # cumulative count of insts sent to commit
|
|
system.cpu1.iew.wb_count 62014417 # cumulative count of insts written-back
|
|
system.cpu1.iew.wb_producers 34071785 # num instructions producing a value
|
|
system.cpu1.iew.wb_consumers 60996509 # num instructions consuming a value
|
|
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu1.iew.wb_rate 0.144093 # insts written-back per cycle
|
|
system.cpu1.iew.wb_fanout 0.558586 # average fanout of values written-back
|
|
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu1.commit.commitSquashedInsts 20655264 # The number of squashed insts skipped by commit
|
|
system.cpu1.commit.commitNonSpecStalls 1041702 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu1.commit.branchMispredicts 445913 # The number of times a branch was mispredicted
|
|
system.cpu1.commit.committed_per_cycle::samples 125990352 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::mean 0.435949 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::stdev 1.396620 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::0 106643597 84.64% 84.64% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::1 9506424 7.55% 92.19% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::2 2528568 2.01% 94.20% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::3 1530167 1.21% 95.41% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::4 1425850 1.13% 96.54% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::5 711007 0.56% 97.11% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::6 1063442 0.84% 97.95% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::7 518210 0.41% 98.36% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::8 2063087 1.64% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::total 125990352 # Number of insts commited each cycle
|
|
system.cpu1.commit.committedInsts 43322553 # Number of instructions committed
|
|
system.cpu1.commit.committedOps 54925314 # Number of ops (including micro ops) committed
|
|
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu1.commit.refs 19011419 # Number of memory references committed
|
|
system.cpu1.commit.loads 11187759 # Number of loads committed
|
|
system.cpu1.commit.membars 242679 # Number of memory barriers committed
|
|
system.cpu1.commit.branches 7019269 # Number of branches committed
|
|
system.cpu1.commit.fp_insts 5428 # Number of committed floating point instructions.
|
|
system.cpu1.commit.int_insts 48550450 # Number of committed integer instructions.
|
|
system.cpu1.commit.function_calls 633769 # Number of function calls committed.
|
|
system.cpu1.commit.bw_lim_events 2063087 # number cycles where commit BW limit reached
|
|
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu1.rob.rob_reads 198211439 # The number of ROB reads
|
|
system.cpu1.rob.rob_writes 154591902 # The number of ROB writes
|
|
system.cpu1.timesIdled 1579473 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu1.idleCycles 301106757 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu1.quiesceCycles 4803892671 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu1.committedInsts 43196726 # Number of Instructions Simulated
|
|
system.cpu1.committedOps 54799487 # Number of Ops (including micro ops) Simulated
|
|
system.cpu1.committedInsts_total 43196726 # Number of Instructions Simulated
|
|
system.cpu1.cpi 9.963172 # CPI: Cycles Per Instruction
|
|
system.cpu1.cpi_total 9.963172 # CPI: Total CPI of All Threads
|
|
system.cpu1.ipc 0.100370 # IPC: Instructions Per Cycle
|
|
system.cpu1.ipc_total 0.100370 # IPC: Total IPC of All Threads
|
|
system.cpu1.int_regfile_reads 429674423 # number of integer regfile reads
|
|
system.cpu1.int_regfile_writes 64872300 # number of integer regfile writes
|
|
system.cpu1.fp_regfile_reads 3964 # number of floating regfile reads
|
|
system.cpu1.fp_regfile_writes 1982 # number of floating regfile writes
|
|
system.cpu1.misc_regfile_reads 101230364 # number of misc regfile reads
|
|
system.cpu1.misc_regfile_writes 513642 # number of misc regfile writes
|
|
system.cpu1.icache.replacements 694768 # number of replacements
|
|
system.cpu1.icache.tagsinuse 498.623067 # Cycle average of tags in use
|
|
system.cpu1.icache.total_refs 9339186 # Total number of references to valid blocks.
|
|
system.cpu1.icache.sampled_refs 695280 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.avg_refs 13.432266 # Average number of references to valid blocks.
|
|
system.cpu1.icache.warmup_cycle 75785789000 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.occ_blocks::cpu1.inst 498.623067 # Average occupied blocks per requestor
|
|
system.cpu1.icache.occ_percent::cpu1.inst 0.973873 # Average percentage of cache occupancy
|
|
system.cpu1.icache.occ_percent::total 0.973873 # Average percentage of cache occupancy
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 9339186 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 9339186 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 9339186 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 9339186 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 9339186 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 9339186 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 751768 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 751768 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 751768 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 751768 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 751768 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 751768 # number of overall misses
|
|
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11830653994 # number of ReadReq miss cycles
|
|
system.cpu1.icache.ReadReq_miss_latency::total 11830653994 # number of ReadReq miss cycles
|
|
system.cpu1.icache.demand_miss_latency::cpu1.inst 11830653994 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_latency::total 11830653994 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.overall_miss_latency::cpu1.inst 11830653994 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_latency::total 11830653994 # number of overall miss cycles
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 10090954 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 10090954 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 10090954 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 10090954 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 10090954 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 10090954 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.074499 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.074499 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.074499 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.074499 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.074499 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.074499 # miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15737.107717 # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total 15737.107717 # average ReadReq miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15737.107717 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::total 15737.107717 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15737.107717 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::total 15737.107717 # average overall miss latency
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 1257996 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 215 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs 5851.144186 # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 56459 # number of ReadReq MSHR hits
|
|
system.cpu1.icache.ReadReq_mshr_hits::total 56459 # number of ReadReq MSHR hits
|
|
system.cpu1.icache.demand_mshr_hits::cpu1.inst 56459 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.demand_mshr_hits::total 56459 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.overall_mshr_hits::cpu1.inst 56459 # number of overall MSHR hits
|
|
system.cpu1.icache.overall_mshr_hits::total 56459 # number of overall MSHR hits
|
|
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 695309 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_misses::total 695309 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::cpu1.inst 695309 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::total 695309 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::cpu1.inst 695309 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::total 695309 # number of overall MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 9048159496 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::total 9048159496 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 9048159496 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::total 9048159496 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 9048159496 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::total 9048159496 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3211500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3211500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3211500 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency::total 3211500 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068904 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.068904 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068904 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::total 0.068904 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068904 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::total 0.068904 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13013.148824 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13013.148824 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13013.148824 # average overall mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::total 13013.148824 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13013.148824 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::total 13013.148824 # average overall mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dcache.replacements 413009 # number of replacements
|
|
system.cpu1.dcache.tagsinuse 487.394187 # Cycle average of tags in use
|
|
system.cpu1.dcache.total_refs 14990250 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.sampled_refs 413521 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.avg_refs 36.250275 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.warmup_cycle 71474582000 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.occ_blocks::cpu1.data 487.394187 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.occ_percent::cpu1.data 0.951942 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.occ_percent::total 0.951942 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 9825576 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 9825576 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 4872589 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 4872589 # number of WriteReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 123205 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::total 123205 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 119861 # number of StoreCondReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::total 119861 # number of StoreCondReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 14698165 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 14698165 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 14698165 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 14698165 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 478795 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 478795 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 1745196 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 1745196 # number of WriteReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14728 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::total 14728 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10805 # number of StoreCondReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::total 10805 # number of StoreCondReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 2223991 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 2223991 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 2223991 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 2223991 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9322511500 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.ReadReq_miss_latency::total 9322511500 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 69699331710 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::total 69699331710 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 175643000 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::total 175643000 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 94845500 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::total 94845500 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::cpu1.data 79021843210 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::total 79021843210 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::cpu1.data 79021843210 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::total 79021843210 # number of overall miss cycles
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 10304371 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 10304371 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 6617785 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 6617785 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 137933 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::total 137933 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 130666 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::total 130666 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 16922156 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 16922156 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 16922156 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 16922156 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.046465 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.046465 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.263713 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.263713 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.106776 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.106776 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.082692 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.082692 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.131425 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.131425 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.131425 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.131425 # miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19470.778726 # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total 19470.778726 # average ReadReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39937.824582 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total 39937.824582 # average WriteReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11925.787615 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11925.787615 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8777.926886 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8777.926886 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 35531.548109 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::total 35531.548109 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 35531.548109 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::total 35531.548109 # average overall miss latency
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 31184009 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 5513500 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 6926 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 166 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4502.455819 # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets 33213.855422 # average number of cycles each access was blocked
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.writebacks::writebacks 373664 # number of writebacks
|
|
system.cpu1.dcache.writebacks::total 373664 # number of writebacks
|
|
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 211355 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_hits::total 211355 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1568704 # number of WriteReq MSHR hits
|
|
system.cpu1.dcache.WriteReq_mshr_hits::total 1568704 # number of WriteReq MSHR hits
|
|
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1302 # number of LoadLockedReq MSHR hits
|
|
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1302 # number of LoadLockedReq MSHR hits
|
|
system.cpu1.dcache.demand_mshr_hits::cpu1.data 1780059 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.demand_mshr_hits::total 1780059 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.overall_mshr_hits::cpu1.data 1780059 # number of overall MSHR hits
|
|
system.cpu1.dcache.overall_mshr_hits::total 1780059 # number of overall MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 267440 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_misses::total 267440 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 176492 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::total 176492 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13426 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13426 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10800 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::total 10800 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::cpu1.data 443932 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::total 443932 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::cpu1.data 443932 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::total 443932 # number of overall MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 4040609191 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 4040609191 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5818534579 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5818534579 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 114031007 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 114031007 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 61142007 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 61142007 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9859143770 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::total 9859143770 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9859143770 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::total 9859143770 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 170666816500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 170666816500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40957900116 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40957900116 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 211624716616 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 211624716616 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025954 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025954 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026669 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026669 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.097337 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.097337 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.082653 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.082653 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026234 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total 0.026234 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026234 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total 0.026234 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15108.469904 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15108.469904 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32967.695867 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32967.695867 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8493.297110 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8493.297110 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5661.296944 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5661.296944 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22208.680091 # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22208.680091 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22208.680091 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22208.680091 # average overall mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.iocache.replacements 0 # number of replacements
|
|
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
|
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
|
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323290279244 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::total 1323290279244 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323290279244 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::total 1323290279244 # number of overall MSHR uncacheable cycles
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 36101 # number of quiesce instructions executed
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 61677 # number of quiesce instructions executed
|
|
|
|
---------- End Simulation Statistics ----------
|