350 lines
11 KiB
C++
350 lines
11 KiB
C++
/*
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* Copyright (c) 2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/** @file
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* Implements a 8250 UART
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*/
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#include <string>
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#include <vector>
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#include "arch/alpha/ev5.hh"
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#include "base/inifile.hh"
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#include "base/str.hh" // for to_number
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#include "base/trace.hh"
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#include "dev/simconsole.hh"
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#include "dev/uart8250.hh"
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#include "dev/platform.hh"
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#include "mem/bus/bus.hh"
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#include "mem/bus/pio_interface.hh"
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#include "mem/bus/pio_interface_impl.hh"
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#include "mem/functional/memory_control.hh"
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#include "sim/builder.hh"
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using namespace std;
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using namespace TheISA;
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Uart8250::IntrEvent::IntrEvent(Uart8250 *u, int bit)
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: Event(&mainEventQueue), uart(u)
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{
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DPRINTF(Uart, "UART Interrupt Event Initilizing\n");
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intrBit = bit;
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}
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const char *
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Uart8250::IntrEvent::description()
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{
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return "uart interrupt delay event";
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}
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void
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Uart8250::IntrEvent::process()
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{
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if (intrBit & uart->IER) {
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DPRINTF(Uart, "UART InterEvent, interrupting\n");
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uart->platform->postConsoleInt();
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uart->status |= intrBit;
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}
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else
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DPRINTF(Uart, "UART InterEvent, not interrupting\n");
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}
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/* The linux serial driver (8250.c about line 1182) loops reading from
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* the device until the device reports it has no more data to
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* read. After a maximum of 255 iterations the code prints "serial8250
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* too much work for irq X," and breaks out of the loop. Since the
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* simulated system is so much slower than the actual system, if a
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* user is typing on the keyboard it is very easy for them to provide
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* input at a fast enough rate to not allow the loop to exit and thus
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* the error to be printed. This magic number provides a delay between
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* the time the UART receives a character to send to the simulated
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* system and the time it actually notifies the system it has a
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* character to send to alleviate this problem. --Ali
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*/
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void
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Uart8250::IntrEvent::scheduleIntr()
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{
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static const Tick interval = (Tick)((Clock::Float::s / 2e9) * 450);
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DPRINTF(Uart, "Scheduling IER interrupt for %#x, at cycle %lld\n", intrBit,
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curTick + interval);
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if (!scheduled())
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schedule(curTick + interval);
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else
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reschedule(curTick + interval);
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}
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Uart8250::Uart8250(const string &name, SimConsole *c, MemoryController *mmu,
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Addr a, Addr s, HierParams *hier, Bus *pio_bus,
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Tick pio_latency, Platform *p)
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: Uart(name, c, mmu, a, s, hier, pio_bus, pio_latency, p),
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txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT)
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{
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IER = 0;
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DLAB = 0;
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LCR = 0;
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MCR = 0;
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}
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Fault
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Uart8250::read(MemReqPtr &req, uint8_t *data)
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{
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Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
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DPRINTF(Uart, " read register %#x\n", daddr);
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assert(req->size == 1);
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switch (daddr) {
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case 0x0:
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if (!(LCR & 0x80)) { // read byte
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if (cons->dataAvailable())
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cons->in(*data);
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else {
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*(uint8_t*)data = 0;
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// A limited amount of these are ok.
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DPRINTF(Uart, "empty read of RX register\n");
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}
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status &= ~RX_INT;
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platform->clearConsoleInt();
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if (cons->dataAvailable() && (IER & UART_IER_RDI))
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rxIntrEvent.scheduleIntr();
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} else { // dll divisor latch
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;
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}
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break;
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case 0x1:
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if (!(LCR & 0x80)) { // Intr Enable Register(IER)
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*(uint8_t*)data = IER;
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} else { // DLM divisor latch MSB
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;
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}
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break;
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case 0x2: // Intr Identification Register (IIR)
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DPRINTF(Uart, "IIR Read, status = %#x\n", (uint32_t)status);
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if (status & RX_INT) /* Rx data interrupt has a higher priority */
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*(uint8_t*)data = IIR_RXID;
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else if (status & TX_INT)
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*(uint8_t*)data = IIR_TXID;
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else
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*(uint8_t*)data = IIR_NOPEND;
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//Tx interrupts are cleared on IIR reads
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status &= ~TX_INT;
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break;
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case 0x3: // Line Control Register (LCR)
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*(uint8_t*)data = LCR;
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break;
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case 0x4: // Modem Control Register (MCR)
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break;
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case 0x5: // Line Status Register (LSR)
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uint8_t lsr;
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lsr = 0;
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// check if there are any bytes to be read
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if (cons->dataAvailable())
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lsr = UART_LSR_DR;
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lsr |= UART_LSR_TEMT | UART_LSR_THRE;
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*(uint8_t*)data = lsr;
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break;
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case 0x6: // Modem Status Register (MSR)
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*(uint8_t*)data = 0;
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break;
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case 0x7: // Scratch Register (SCR)
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*(uint8_t*)data = 0; // doesn't exist with at 8250.
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break;
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default:
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panic("Tried to access a UART port that doesn't exist\n");
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break;
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}
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return NoFault;
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}
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Fault
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Uart8250::write(MemReqPtr &req, const uint8_t *data)
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{
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Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
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DPRINTF(Uart, " write register %#x value %#x\n", daddr, *(uint8_t*)data);
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switch (daddr) {
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case 0x0:
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if (!(LCR & 0x80)) { // write byte
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cons->out(*(uint8_t *)data);
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platform->clearConsoleInt();
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status &= ~TX_INT;
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if (UART_IER_THRI & IER)
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txIntrEvent.scheduleIntr();
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} else { // dll divisor latch
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;
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}
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break;
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case 0x1:
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if (!(LCR & 0x80)) { // Intr Enable Register(IER)
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IER = *(uint8_t*)data;
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if (UART_IER_THRI & IER)
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{
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DPRINTF(Uart, "IER: IER_THRI set, scheduling TX intrrupt\n");
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txIntrEvent.scheduleIntr();
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}
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else
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{
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DPRINTF(Uart, "IER: IER_THRI cleared, descheduling TX intrrupt\n");
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if (txIntrEvent.scheduled())
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txIntrEvent.deschedule();
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if (status & TX_INT)
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platform->clearConsoleInt();
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status &= ~TX_INT;
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}
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if ((UART_IER_RDI & IER) && cons->dataAvailable()) {
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DPRINTF(Uart, "IER: IER_RDI set, scheduling RX intrrupt\n");
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rxIntrEvent.scheduleIntr();
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} else {
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DPRINTF(Uart, "IER: IER_RDI cleared, descheduling RX intrrupt\n");
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if (rxIntrEvent.scheduled())
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rxIntrEvent.deschedule();
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if (status & RX_INT)
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platform->clearConsoleInt();
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status &= ~RX_INT;
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}
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} else { // DLM divisor latch MSB
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;
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}
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break;
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case 0x2: // FIFO Control Register (FCR)
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break;
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case 0x3: // Line Control Register (LCR)
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LCR = *(uint8_t*)data;
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break;
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case 0x4: // Modem Control Register (MCR)
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if (*(uint8_t*)data == (UART_MCR_LOOP | 0x0A))
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MCR = 0x9A;
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break;
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case 0x7: // Scratch Register (SCR)
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// We are emulating a 8250 so we don't have a scratch reg
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break;
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default:
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panic("Tried to access a UART port that doesn't exist\n");
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break;
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}
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return NoFault;
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}
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void
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Uart8250::dataAvailable()
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{
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// if the kernel wants an interrupt when we have data
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if (IER & UART_IER_RDI)
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{
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platform->postConsoleInt();
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status |= RX_INT;
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}
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}
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void
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Uart8250::serialize(ostream &os)
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{
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SERIALIZE_SCALAR(status);
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SERIALIZE_SCALAR(IER);
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SERIALIZE_SCALAR(DLAB);
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SERIALIZE_SCALAR(LCR);
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SERIALIZE_SCALAR(MCR);
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Tick rxintrwhen;
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if (rxIntrEvent.scheduled())
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rxintrwhen = rxIntrEvent.when();
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else
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rxintrwhen = 0;
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Tick txintrwhen;
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if (txIntrEvent.scheduled())
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txintrwhen = txIntrEvent.when();
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else
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txintrwhen = 0;
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SERIALIZE_SCALAR(rxintrwhen);
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SERIALIZE_SCALAR(txintrwhen);
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}
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void
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Uart8250::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_SCALAR(status);
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UNSERIALIZE_SCALAR(IER);
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UNSERIALIZE_SCALAR(DLAB);
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UNSERIALIZE_SCALAR(LCR);
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UNSERIALIZE_SCALAR(MCR);
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Tick rxintrwhen;
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Tick txintrwhen;
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UNSERIALIZE_SCALAR(rxintrwhen);
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UNSERIALIZE_SCALAR(txintrwhen);
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if (rxintrwhen != 0)
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rxIntrEvent.schedule(rxintrwhen);
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if (txintrwhen != 0)
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txIntrEvent.schedule(txintrwhen);
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
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SimObjectParam<SimConsole *> console;
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SimObjectParam<MemoryController *> mmu;
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SimObjectParam<Platform *> platform;
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Param<Addr> addr;
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Param<Addr> size;
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SimObjectParam<Bus*> pio_bus;
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Param<Tick> pio_latency;
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SimObjectParam<HierParams *> hier;
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END_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
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BEGIN_INIT_SIM_OBJECT_PARAMS(Uart8250)
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INIT_PARAM(console, "The console"),
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INIT_PARAM(mmu, "Memory Controller"),
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INIT_PARAM(platform, "Pointer to platfrom"),
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INIT_PARAM(addr, "Device Address"),
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INIT_PARAM_DFLT(size, "Device size", 0x8),
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INIT_PARAM(pio_bus, ""),
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INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
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INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
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END_INIT_SIM_OBJECT_PARAMS(Uart8250)
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CREATE_SIM_OBJECT(Uart8250)
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{
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return new Uart8250(getInstanceName(), console, mmu, addr, size, hier,
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pio_bus, pio_latency, platform);
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}
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REGISTER_SIM_OBJECT("Uart8250", Uart8250)
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