1359 lines
41 KiB
C++
1359 lines
41 KiB
C++
/*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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* Korey Sewell
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*/
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#include <list>
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#include "arch/isa_traits.hh"
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#include "arch/regfile.hh"
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#include "config/full_system.hh"
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#include "cpu/o3/rename.hh"
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template <class Impl>
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DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, Params *params)
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: cpu(_cpu),
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iewToRenameDelay(params->iewToRenameDelay),
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decodeToRenameDelay(params->decodeToRenameDelay),
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commitToRenameDelay(params->commitToRenameDelay),
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renameWidth(params->renameWidth),
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commitWidth(params->commitWidth),
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resumeSerialize(false),
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resumeUnblocking(false),
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numThreads(params->numberOfThreads),
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maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs)
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{
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_status = Inactive;
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for (int i=0; i< numThreads; i++) {
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renameStatus[i] = Idle;
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freeEntries[i].iqEntries = 0;
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freeEntries[i].lsqEntries = 0;
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freeEntries[i].robEntries = 0;
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stalls[i].iew = false;
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stalls[i].commit = false;
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serializeInst[i] = NULL;
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instsInProgress[i] = 0;
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emptyROB[i] = true;
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serializeOnNextInst[i] = false;
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}
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// @todo: Make into a parameter.
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skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth;
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}
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template <class Impl>
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std::string
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DefaultRename<Impl>::name() const
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{
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return cpu->name() + ".rename";
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}
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template <class Impl>
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void
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DefaultRename<Impl>::regStats()
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{
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renameSquashCycles
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.name(name() + ".RENAME:SquashCycles")
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.desc("Number of cycles rename is squashing")
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.prereq(renameSquashCycles);
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renameIdleCycles
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.name(name() + ".RENAME:IdleCycles")
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.desc("Number of cycles rename is idle")
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.prereq(renameIdleCycles);
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renameBlockCycles
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.name(name() + ".RENAME:BlockCycles")
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.desc("Number of cycles rename is blocking")
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.prereq(renameBlockCycles);
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renameSerializeStallCycles
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.name(name() + ".RENAME:serializeStallCycles")
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.desc("count of cycles rename stalled for serializing inst")
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.flags(Stats::total);
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renameRunCycles
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.name(name() + ".RENAME:RunCycles")
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.desc("Number of cycles rename is running")
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.prereq(renameIdleCycles);
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renameUnblockCycles
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.name(name() + ".RENAME:UnblockCycles")
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.desc("Number of cycles rename is unblocking")
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.prereq(renameUnblockCycles);
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renameRenamedInsts
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.name(name() + ".RENAME:RenamedInsts")
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.desc("Number of instructions processed by rename")
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.prereq(renameRenamedInsts);
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renameSquashedInsts
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.name(name() + ".RENAME:SquashedInsts")
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.desc("Number of squashed instructions processed by rename")
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.prereq(renameSquashedInsts);
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renameROBFullEvents
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.name(name() + ".RENAME:ROBFullEvents")
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.desc("Number of times rename has blocked due to ROB full")
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.prereq(renameROBFullEvents);
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renameIQFullEvents
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.name(name() + ".RENAME:IQFullEvents")
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.desc("Number of times rename has blocked due to IQ full")
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.prereq(renameIQFullEvents);
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renameLSQFullEvents
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.name(name() + ".RENAME:LSQFullEvents")
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.desc("Number of times rename has blocked due to LSQ full")
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.prereq(renameLSQFullEvents);
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renameFullRegistersEvents
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.name(name() + ".RENAME:FullRegisterEvents")
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.desc("Number of times there has been no free registers")
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.prereq(renameFullRegistersEvents);
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renameRenamedOperands
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.name(name() + ".RENAME:RenamedOperands")
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.desc("Number of destination operands rename has renamed")
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.prereq(renameRenamedOperands);
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renameRenameLookups
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.name(name() + ".RENAME:RenameLookups")
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.desc("Number of register rename lookups that rename has made")
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.prereq(renameRenameLookups);
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renameCommittedMaps
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.name(name() + ".RENAME:CommittedMaps")
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.desc("Number of HB maps that are committed")
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.prereq(renameCommittedMaps);
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renameUndoneMaps
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.name(name() + ".RENAME:UndoneMaps")
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.desc("Number of HB maps that are undone due to squashing")
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.prereq(renameUndoneMaps);
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renamedSerializing
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.name(name() + ".RENAME:serializingInsts")
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.desc("count of serializing insts renamed")
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.flags(Stats::total)
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;
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renamedTempSerializing
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.name(name() + ".RENAME:tempSerializingInsts")
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.desc("count of temporary serializing insts renamed")
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.flags(Stats::total)
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;
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renameSkidInsts
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.name(name() + ".RENAME:skidInsts")
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.desc("count of insts added to the skid buffer")
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.flags(Stats::total)
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;
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}
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template <class Impl>
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void
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DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
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{
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timeBuffer = tb_ptr;
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// Setup wire to read information from time buffer, from IEW stage.
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fromIEW = timeBuffer->getWire(-iewToRenameDelay);
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// Setup wire to read infromation from time buffer, from commit stage.
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fromCommit = timeBuffer->getWire(-commitToRenameDelay);
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// Setup wire to write information to previous stages.
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toDecode = timeBuffer->getWire(0);
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}
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template <class Impl>
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void
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DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
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{
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renameQueue = rq_ptr;
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// Setup wire to write information to future stages.
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toIEW = renameQueue->getWire(0);
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}
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template <class Impl>
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void
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DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
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{
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decodeQueue = dq_ptr;
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// Setup wire to get information from decode.
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fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
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}
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template <class Impl>
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void
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DefaultRename<Impl>::initStage()
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{
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// Grab the number of free entries directly from the stages.
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for (int tid=0; tid < numThreads; tid++) {
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freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
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freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
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freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
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emptyROB[tid] = true;
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}
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}
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template<class Impl>
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void
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DefaultRename<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
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{
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activeThreads = at_ptr;
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}
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template <class Impl>
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void
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DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
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{
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for (int i=0; i<numThreads; i++) {
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renameMap[i] = &rm_ptr[i];
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}
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}
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template <class Impl>
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void
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DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
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{
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freeList = fl_ptr;
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}
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template<class Impl>
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void
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DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
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{
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scoreboard = _scoreboard;
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}
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template <class Impl>
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bool
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DefaultRename<Impl>::drain()
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{
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// Rename is ready to switch out at any time.
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cpu->signalDrained();
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return true;
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}
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template <class Impl>
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void
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DefaultRename<Impl>::switchOut()
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{
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// Clear any state, fix up the rename map.
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for (int i = 0; i < numThreads; i++) {
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typename std::list<RenameHistory>::iterator hb_it =
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historyBuffer[i].begin();
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while (!historyBuffer[i].empty()) {
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assert(hb_it != historyBuffer[i].end());
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DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
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"number %i.\n", i, (*hb_it).instSeqNum);
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// Tell the rename map to set the architected register to the
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// previous physical register that it was renamed to.
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renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
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// Put the renamed physical register back on the free list.
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freeList->addReg(hb_it->newPhysReg);
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// Be sure to mark its register as ready if it's a misc register.
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if (hb_it->newPhysReg >= maxPhysicalRegs) {
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scoreboard->setReg(hb_it->newPhysReg);
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}
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historyBuffer[i].erase(hb_it++);
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}
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insts[i].clear();
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skidBuffer[i].clear();
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}
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}
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template <class Impl>
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void
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DefaultRename<Impl>::takeOverFrom()
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{
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_status = Inactive;
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initStage();
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// Reset all state prior to taking over from the other CPU.
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for (int i=0; i< numThreads; i++) {
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renameStatus[i] = Idle;
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stalls[i].iew = false;
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stalls[i].commit = false;
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serializeInst[i] = NULL;
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instsInProgress[i] = 0;
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emptyROB[i] = true;
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serializeOnNextInst[i] = false;
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}
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}
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template <class Impl>
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void
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DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid)
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{
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DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
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// Clear the stall signal if rename was blocked or unblocking before.
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// If it still needs to block, the blocking should happen the next
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// cycle and there should be space to hold everything due to the squash.
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if (renameStatus[tid] == Blocked ||
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renameStatus[tid] == Unblocking) {
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toDecode->renameUnblock[tid] = 1;
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resumeSerialize = false;
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serializeInst[tid] = NULL;
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} else if (renameStatus[tid] == SerializeStall) {
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if (serializeInst[tid]->seqNum <= squash_seq_num) {
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DPRINTF(Rename, "Rename will resume serializing after squash\n");
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resumeSerialize = true;
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assert(serializeInst[tid]);
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} else {
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resumeSerialize = false;
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toDecode->renameUnblock[tid] = 1;
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serializeInst[tid] = NULL;
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}
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}
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// Set the status to Squashing.
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renameStatus[tid] = Squashing;
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// Squash any instructions from decode.
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unsigned squashCount = 0;
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for (int i=0; i<fromDecode->size; i++) {
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if (fromDecode->insts[i]->threadNumber == tid &&
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fromDecode->insts[i]->seqNum > squash_seq_num) {
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fromDecode->insts[i]->setSquashed();
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wroteToTimeBuffer = true;
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squashCount++;
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}
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}
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// Clear the instruction list and skid buffer in case they have any
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// insts in them.
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insts[tid].clear();
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// Clear the skid buffer in case it has any data in it.
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skidBuffer[tid].clear();
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doSquash(squash_seq_num, tid);
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}
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template <class Impl>
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void
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DefaultRename<Impl>::tick()
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{
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wroteToTimeBuffer = false;
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blockThisCycle = false;
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bool status_change = false;
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toIEWIndex = 0;
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sortInsts();
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std::list<unsigned>::iterator threads = activeThreads->begin();
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std::list<unsigned>::iterator end = activeThreads->end();
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// Check stall and squash signals.
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while (threads != end) {
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unsigned tid = *threads++;
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DPRINTF(Rename, "Processing [tid:%i]\n", tid);
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status_change = checkSignalsAndUpdate(tid) || status_change;
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rename(status_change, tid);
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}
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if (status_change) {
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updateStatus();
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}
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if (wroteToTimeBuffer) {
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DPRINTF(Activity, "Activity this cycle.\n");
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cpu->activityThisCycle();
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}
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threads = activeThreads->begin();
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while (threads != end) {
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unsigned tid = *threads++;
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// If we committed this cycle then doneSeqNum will be > 0
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if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
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!fromCommit->commitInfo[tid].squash &&
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renameStatus[tid] != Squashing) {
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removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
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tid);
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}
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}
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// @todo: make into updateProgress function
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for (int tid=0; tid < numThreads; tid++) {
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instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
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assert(instsInProgress[tid] >=0);
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}
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}
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template<class Impl>
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void
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DefaultRename<Impl>::rename(bool &status_change, unsigned tid)
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{
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// If status is Running or idle,
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// call renameInsts()
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// If status is Unblocking,
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// buffer any instructions coming from decode
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// continue trying to empty skid buffer
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// check if stall conditions have passed
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if (renameStatus[tid] == Blocked) {
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++renameBlockCycles;
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} else if (renameStatus[tid] == Squashing) {
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++renameSquashCycles;
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} else if (renameStatus[tid] == SerializeStall) {
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++renameSerializeStallCycles;
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// If we are currently in SerializeStall and resumeSerialize
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// was set, then that means that we are resuming serializing
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// this cycle. Tell the previous stages to block.
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if (resumeSerialize) {
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resumeSerialize = false;
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block(tid);
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toDecode->renameUnblock[tid] = false;
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}
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} else if (renameStatus[tid] == Unblocking) {
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if (resumeUnblocking) {
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block(tid);
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resumeUnblocking = false;
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toDecode->renameUnblock[tid] = false;
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}
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}
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if (renameStatus[tid] == Running ||
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renameStatus[tid] == Idle) {
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DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
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"stage.\n", tid);
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renameInsts(tid);
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} else if (renameStatus[tid] == Unblocking) {
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renameInsts(tid);
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if (validInsts()) {
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// Add the current inputs to the skid buffer so they can be
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// reprocessed when this stage unblocks.
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skidInsert(tid);
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}
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// If we switched over to blocking, then there's a potential for
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// an overall status change.
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status_change = unblock(tid) || status_change || blockThisCycle;
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}
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}
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template <class Impl>
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void
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DefaultRename<Impl>::renameInsts(unsigned tid)
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{
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// Instructions can be either in the skid buffer or the queue of
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// instructions coming from decode, depending on the status.
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int insts_available = renameStatus[tid] == Unblocking ?
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skidBuffer[tid].size() : insts[tid].size();
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// Check the decode queue to see if instructions are available.
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// If there are no available instructions to rename, then do nothing.
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if (insts_available == 0) {
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DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
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tid);
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// Should I change status to idle?
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++renameIdleCycles;
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return;
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} else if (renameStatus[tid] == Unblocking) {
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++renameUnblockCycles;
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} else if (renameStatus[tid] == Running) {
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++renameRunCycles;
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}
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DynInstPtr inst;
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// Will have to do a different calculation for the number of free
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// entries.
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int free_rob_entries = calcFreeROBEntries(tid);
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int free_iq_entries = calcFreeIQEntries(tid);
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int free_lsq_entries = calcFreeLSQEntries(tid);
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int min_free_entries = free_rob_entries;
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FullSource source = ROB;
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if (free_iq_entries < min_free_entries) {
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min_free_entries = free_iq_entries;
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source = IQ;
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}
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if (free_lsq_entries < min_free_entries) {
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min_free_entries = free_lsq_entries;
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source = LSQ;
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}
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// Check if there's any space left.
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if (min_free_entries <= 0) {
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DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
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"entries.\n"
|
|
"ROB has %i free entries.\n"
|
|
"IQ has %i free entries.\n"
|
|
"LSQ has %i free entries.\n",
|
|
tid,
|
|
free_rob_entries,
|
|
free_iq_entries,
|
|
free_lsq_entries);
|
|
|
|
blockThisCycle = true;
|
|
|
|
block(tid);
|
|
|
|
incrFullStat(source);
|
|
|
|
return;
|
|
} else if (min_free_entries < insts_available) {
|
|
DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
|
|
"%i insts available, but only %i insts can be "
|
|
"renamed due to ROB/IQ/LSQ limits.\n",
|
|
tid, insts_available, min_free_entries);
|
|
|
|
insts_available = min_free_entries;
|
|
|
|
blockThisCycle = true;
|
|
|
|
incrFullStat(source);
|
|
}
|
|
|
|
InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
|
|
skidBuffer[tid] : insts[tid];
|
|
|
|
DPRINTF(Rename, "[tid:%u]: %i available instructions to "
|
|
"send iew.\n", tid, insts_available);
|
|
|
|
DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
|
|
"dispatched to IQ last cycle.\n",
|
|
tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
|
|
|
|
// Handle serializing the next instruction if necessary.
|
|
if (serializeOnNextInst[tid]) {
|
|
if (emptyROB[tid] && instsInProgress[tid] == 0) {
|
|
// ROB already empty; no need to serialize.
|
|
serializeOnNextInst[tid] = false;
|
|
} else if (!insts_to_rename.empty()) {
|
|
insts_to_rename.front()->setSerializeBefore();
|
|
}
|
|
}
|
|
|
|
int renamed_insts = 0;
|
|
|
|
while (insts_available > 0 && toIEWIndex < renameWidth) {
|
|
DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
|
|
|
|
assert(!insts_to_rename.empty());
|
|
|
|
inst = insts_to_rename.front();
|
|
|
|
insts_to_rename.pop_front();
|
|
|
|
if (renameStatus[tid] == Unblocking) {
|
|
DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename "
|
|
"skidBuffer\n",
|
|
tid, inst->seqNum, inst->readPC());
|
|
}
|
|
|
|
if (inst->isSquashed()) {
|
|
DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is "
|
|
"squashed, skipping.\n",
|
|
tid, inst->seqNum, inst->readPC());
|
|
|
|
++renameSquashedInsts;
|
|
|
|
// Decrement how many instructions are available.
|
|
--insts_available;
|
|
|
|
continue;
|
|
}
|
|
|
|
DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
|
|
"PC %#x.\n",
|
|
tid, inst->seqNum, inst->readPC());
|
|
|
|
// Handle serializeAfter/serializeBefore instructions.
|
|
// serializeAfter marks the next instruction as serializeBefore.
|
|
// serializeBefore makes the instruction wait in rename until the ROB
|
|
// is empty.
|
|
|
|
// In this model, IPR accesses are serialize before
|
|
// instructions, and store conditionals are serialize after
|
|
// instructions. This is mainly due to lack of support for
|
|
// out-of-order operations of either of those classes of
|
|
// instructions.
|
|
if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
|
|
!inst->isSerializeHandled()) {
|
|
DPRINTF(Rename, "Serialize before instruction encountered.\n");
|
|
|
|
if (!inst->isTempSerializeBefore()) {
|
|
renamedSerializing++;
|
|
inst->setSerializeHandled();
|
|
} else {
|
|
renamedTempSerializing++;
|
|
}
|
|
|
|
// Change status over to SerializeStall so that other stages know
|
|
// what this is blocked on.
|
|
renameStatus[tid] = SerializeStall;
|
|
|
|
serializeInst[tid] = inst;
|
|
|
|
blockThisCycle = true;
|
|
|
|
break;
|
|
} else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
|
|
!inst->isSerializeHandled()) {
|
|
DPRINTF(Rename, "Serialize after instruction encountered.\n");
|
|
|
|
renamedSerializing++;
|
|
|
|
inst->setSerializeHandled();
|
|
|
|
serializeAfter(insts_to_rename, tid);
|
|
}
|
|
|
|
// Check here to make sure there are enough destination registers
|
|
// to rename to. Otherwise block.
|
|
if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
|
|
DPRINTF(Rename, "Blocking due to lack of free "
|
|
"physical registers to rename to.\n");
|
|
blockThisCycle = true;
|
|
insts_to_rename.push_front(inst);
|
|
++renameFullRegistersEvents;
|
|
|
|
break;
|
|
}
|
|
|
|
renameSrcRegs(inst, inst->threadNumber);
|
|
|
|
renameDestRegs(inst, inst->threadNumber);
|
|
|
|
++renamed_insts;
|
|
|
|
// Put instruction in rename queue.
|
|
toIEW->insts[toIEWIndex] = inst;
|
|
++(toIEW->size);
|
|
|
|
// Increment which instruction we're on.
|
|
++toIEWIndex;
|
|
|
|
// Decrement how many instructions are available.
|
|
--insts_available;
|
|
}
|
|
|
|
instsInProgress[tid] += renamed_insts;
|
|
renameRenamedInsts += renamed_insts;
|
|
|
|
// If we wrote to the time buffer, record this.
|
|
if (toIEWIndex) {
|
|
wroteToTimeBuffer = true;
|
|
}
|
|
|
|
// Check if there's any instructions left that haven't yet been renamed.
|
|
// If so then block.
|
|
if (insts_available) {
|
|
blockThisCycle = true;
|
|
}
|
|
|
|
if (blockThisCycle) {
|
|
block(tid);
|
|
toDecode->renameUnblock[tid] = false;
|
|
}
|
|
}
|
|
|
|
template<class Impl>
|
|
void
|
|
DefaultRename<Impl>::skidInsert(unsigned tid)
|
|
{
|
|
DynInstPtr inst = NULL;
|
|
|
|
while (!insts[tid].empty()) {
|
|
inst = insts[tid].front();
|
|
|
|
insts[tid].pop_front();
|
|
|
|
assert(tid == inst->threadNumber);
|
|
|
|
DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename "
|
|
"skidBuffer\n", tid, inst->seqNum, inst->readPC());
|
|
|
|
++renameSkidInsts;
|
|
|
|
skidBuffer[tid].push_back(inst);
|
|
}
|
|
|
|
if (skidBuffer[tid].size() > skidBufferMax)
|
|
{
|
|
typename InstQueue::iterator it;
|
|
warn("Skidbuffer contents:\n");
|
|
for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++)
|
|
{
|
|
warn("[tid:%u]: %s [sn:%i].\n", tid,
|
|
(*it)->staticInst->disassemble(inst->readPC()),
|
|
(*it)->seqNum);
|
|
}
|
|
panic("Skidbuffer Exceeded Max Size");
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
DefaultRename<Impl>::sortInsts()
|
|
{
|
|
int insts_from_decode = fromDecode->size;
|
|
#ifdef DEBUG
|
|
for (int i=0; i < numThreads; i++)
|
|
assert(insts[i].empty());
|
|
#endif
|
|
for (int i = 0; i < insts_from_decode; ++i) {
|
|
DynInstPtr inst = fromDecode->insts[i];
|
|
insts[inst->threadNumber].push_back(inst);
|
|
}
|
|
}
|
|
|
|
template<class Impl>
|
|
bool
|
|
DefaultRename<Impl>::skidsEmpty()
|
|
{
|
|
std::list<unsigned>::iterator threads = activeThreads->begin();
|
|
std::list<unsigned>::iterator end = activeThreads->end();
|
|
|
|
while (threads != end) {
|
|
unsigned tid = *threads++;
|
|
|
|
if (!skidBuffer[tid].empty())
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
template<class Impl>
|
|
void
|
|
DefaultRename<Impl>::updateStatus()
|
|
{
|
|
bool any_unblocking = false;
|
|
|
|
std::list<unsigned>::iterator threads = activeThreads->begin();
|
|
std::list<unsigned>::iterator end = activeThreads->end();
|
|
|
|
while (threads != end) {
|
|
unsigned tid = *threads++;
|
|
|
|
if (renameStatus[tid] == Unblocking) {
|
|
any_unblocking = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
// Rename will have activity if it's unblocking.
|
|
if (any_unblocking) {
|
|
if (_status == Inactive) {
|
|
_status = Active;
|
|
|
|
DPRINTF(Activity, "Activating stage.\n");
|
|
|
|
cpu->activateStage(O3CPU::RenameIdx);
|
|
}
|
|
} else {
|
|
// If it's not unblocking, then rename will not have any internal
|
|
// activity. Switch it to inactive.
|
|
if (_status == Active) {
|
|
_status = Inactive;
|
|
DPRINTF(Activity, "Deactivating stage.\n");
|
|
|
|
cpu->deactivateStage(O3CPU::RenameIdx);
|
|
}
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
bool
|
|
DefaultRename<Impl>::block(unsigned tid)
|
|
{
|
|
DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
|
|
|
|
// Add the current inputs onto the skid buffer, so they can be
|
|
// reprocessed when this stage unblocks.
|
|
skidInsert(tid);
|
|
|
|
// Only signal backwards to block if the previous stages do not think
|
|
// rename is already blocked.
|
|
if (renameStatus[tid] != Blocked) {
|
|
// If resumeUnblocking is set, we unblocked during the squash,
|
|
// but now we're have unblocking status. We need to tell earlier
|
|
// stages to block.
|
|
if (resumeUnblocking || renameStatus[tid] != Unblocking) {
|
|
toDecode->renameBlock[tid] = true;
|
|
toDecode->renameUnblock[tid] = false;
|
|
wroteToTimeBuffer = true;
|
|
}
|
|
|
|
// Rename can not go from SerializeStall to Blocked, otherwise
|
|
// it would not know to complete the serialize stall.
|
|
if (renameStatus[tid] != SerializeStall) {
|
|
// Set status to Blocked.
|
|
renameStatus[tid] = Blocked;
|
|
return true;
|
|
}
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
template <class Impl>
|
|
bool
|
|
DefaultRename<Impl>::unblock(unsigned tid)
|
|
{
|
|
DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
|
|
|
|
// Rename is done unblocking if the skid buffer is empty.
|
|
if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
|
|
|
|
DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
|
|
|
|
toDecode->renameUnblock[tid] = true;
|
|
wroteToTimeBuffer = true;
|
|
|
|
renameStatus[tid] = Running;
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, unsigned tid)
|
|
{
|
|
typename std::list<RenameHistory>::iterator hb_it =
|
|
historyBuffer[tid].begin();
|
|
|
|
// After a syscall squashes everything, the history buffer may be empty
|
|
// but the ROB may still be squashing instructions.
|
|
if (historyBuffer[tid].empty()) {
|
|
return;
|
|
}
|
|
|
|
// Go through the most recent instructions, undoing the mappings
|
|
// they did and freeing up the registers.
|
|
while (!historyBuffer[tid].empty() &&
|
|
(*hb_it).instSeqNum > squashed_seq_num) {
|
|
assert(hb_it != historyBuffer[tid].end());
|
|
|
|
DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
|
|
"number %i.\n", tid, (*hb_it).instSeqNum);
|
|
|
|
// Tell the rename map to set the architected register to the
|
|
// previous physical register that it was renamed to.
|
|
renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
|
|
|
|
// Put the renamed physical register back on the free list.
|
|
freeList->addReg(hb_it->newPhysReg);
|
|
|
|
// Be sure to mark its register as ready if it's a misc register.
|
|
if (hb_it->newPhysReg >= maxPhysicalRegs) {
|
|
scoreboard->setReg(hb_it->newPhysReg);
|
|
}
|
|
|
|
historyBuffer[tid].erase(hb_it++);
|
|
|
|
++renameUndoneMaps;
|
|
}
|
|
}
|
|
|
|
template<class Impl>
|
|
void
|
|
DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid)
|
|
{
|
|
DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
|
|
"history buffer %u (size=%i), until [sn:%lli].\n",
|
|
tid, tid, historyBuffer[tid].size(), inst_seq_num);
|
|
|
|
typename std::list<RenameHistory>::iterator hb_it =
|
|
historyBuffer[tid].end();
|
|
|
|
--hb_it;
|
|
|
|
if (historyBuffer[tid].empty()) {
|
|
DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
|
|
return;
|
|
} else if (hb_it->instSeqNum > inst_seq_num) {
|
|
DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure "
|
|
"that a syscall happened recently.\n", tid);
|
|
return;
|
|
}
|
|
|
|
// Commit all the renames up until (and including) the committed sequence
|
|
// number. Some or even all of the committed instructions may not have
|
|
// rename histories if they did not have destination registers that were
|
|
// renamed.
|
|
while (!historyBuffer[tid].empty() &&
|
|
hb_it != historyBuffer[tid].end() &&
|
|
(*hb_it).instSeqNum <= inst_seq_num) {
|
|
|
|
DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
|
|
"[sn:%lli].\n",
|
|
tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum);
|
|
|
|
freeList->addReg((*hb_it).prevPhysReg);
|
|
++renameCommittedMaps;
|
|
|
|
historyBuffer[tid].erase(hb_it--);
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
inline void
|
|
DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid)
|
|
{
|
|
assert(renameMap[tid] != 0);
|
|
|
|
unsigned num_src_regs = inst->numSrcRegs();
|
|
|
|
// Get the architectual register numbers from the source and
|
|
// destination operands, and redirect them to the right register.
|
|
// Will need to mark dependencies though.
|
|
for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
|
|
RegIndex src_reg = inst->srcRegIdx(src_idx);
|
|
RegIndex flat_src_reg = src_reg;
|
|
if (src_reg < TheISA::FP_Base_DepTag) {
|
|
flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg);
|
|
DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg);
|
|
} else {
|
|
// Floating point and Miscellaneous registers need their indexes
|
|
// adjusted to account for the expanded number of flattened int regs.
|
|
flat_src_reg = src_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs;
|
|
DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", src_reg, flat_src_reg);
|
|
}
|
|
|
|
inst->flattenSrcReg(src_idx, flat_src_reg);
|
|
|
|
// Look up the source registers to get the phys. register they've
|
|
// been renamed to, and set the sources to those registers.
|
|
PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg);
|
|
|
|
DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
|
|
"physical reg %i.\n", tid, (int)flat_src_reg,
|
|
(int)renamed_reg);
|
|
|
|
inst->renameSrcReg(src_idx, renamed_reg);
|
|
|
|
// See if the register is ready or not.
|
|
if (scoreboard->getReg(renamed_reg) == true) {
|
|
DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", tid, renamed_reg);
|
|
|
|
inst->markSrcRegReady(src_idx);
|
|
} else {
|
|
DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n", tid, renamed_reg);
|
|
}
|
|
|
|
++renameRenameLookups;
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
inline void
|
|
DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid)
|
|
{
|
|
typename RenameMap::RenameInfo rename_result;
|
|
|
|
unsigned num_dest_regs = inst->numDestRegs();
|
|
|
|
// Rename the destination registers.
|
|
for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
|
|
RegIndex dest_reg = inst->destRegIdx(dest_idx);
|
|
RegIndex flat_dest_reg = dest_reg;
|
|
if (dest_reg < TheISA::FP_Base_DepTag) {
|
|
// Integer registers are flattened.
|
|
flat_dest_reg = TheISA::flattenIntIndex(inst->tcBase(), dest_reg);
|
|
DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg);
|
|
} else {
|
|
// Floating point and Miscellaneous registers need their indexes
|
|
// adjusted to account for the expanded number of flattened int regs.
|
|
flat_dest_reg = dest_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs;
|
|
DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", dest_reg, flat_dest_reg);
|
|
}
|
|
|
|
inst->flattenDestReg(dest_idx, flat_dest_reg);
|
|
|
|
// Get the physical register that the destination will be
|
|
// renamed to.
|
|
rename_result = renameMap[tid]->rename(flat_dest_reg);
|
|
|
|
//Mark Scoreboard entry as not ready
|
|
scoreboard->unsetReg(rename_result.first);
|
|
|
|
DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
|
|
"reg %i.\n", tid, (int)flat_dest_reg,
|
|
(int)rename_result.first);
|
|
|
|
// Record the rename information so that a history can be kept.
|
|
RenameHistory hb_entry(inst->seqNum, flat_dest_reg,
|
|
rename_result.first,
|
|
rename_result.second);
|
|
|
|
historyBuffer[tid].push_front(hb_entry);
|
|
|
|
DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
|
|
"(size=%i), [sn:%lli].\n",tid,
|
|
historyBuffer[tid].size(),
|
|
(*historyBuffer[tid].begin()).instSeqNum);
|
|
|
|
// Tell the instruction to rename the appropriate destination
|
|
// register (dest_idx) to the new physical register
|
|
// (rename_result.first), and record the previous physical
|
|
// register that the same logical register was renamed to
|
|
// (rename_result.second).
|
|
inst->renameDestReg(dest_idx,
|
|
rename_result.first,
|
|
rename_result.second);
|
|
|
|
++renameRenamedOperands;
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
inline int
|
|
DefaultRename<Impl>::calcFreeROBEntries(unsigned tid)
|
|
{
|
|
int num_free = freeEntries[tid].robEntries -
|
|
(instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
|
|
|
|
//DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
|
|
|
|
return num_free;
|
|
}
|
|
|
|
template <class Impl>
|
|
inline int
|
|
DefaultRename<Impl>::calcFreeIQEntries(unsigned tid)
|
|
{
|
|
int num_free = freeEntries[tid].iqEntries -
|
|
(instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
|
|
|
|
//DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
|
|
|
|
return num_free;
|
|
}
|
|
|
|
template <class Impl>
|
|
inline int
|
|
DefaultRename<Impl>::calcFreeLSQEntries(unsigned tid)
|
|
{
|
|
int num_free = freeEntries[tid].lsqEntries -
|
|
(instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
|
|
|
|
//DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
|
|
|
|
return num_free;
|
|
}
|
|
|
|
template <class Impl>
|
|
unsigned
|
|
DefaultRename<Impl>::validInsts()
|
|
{
|
|
unsigned inst_count = 0;
|
|
|
|
for (int i=0; i<fromDecode->size; i++) {
|
|
if (!fromDecode->insts[i]->isSquashed())
|
|
inst_count++;
|
|
}
|
|
|
|
return inst_count;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
DefaultRename<Impl>::readStallSignals(unsigned tid)
|
|
{
|
|
if (fromIEW->iewBlock[tid]) {
|
|
stalls[tid].iew = true;
|
|
}
|
|
|
|
if (fromIEW->iewUnblock[tid]) {
|
|
assert(stalls[tid].iew);
|
|
stalls[tid].iew = false;
|
|
}
|
|
|
|
if (fromCommit->commitBlock[tid]) {
|
|
stalls[tid].commit = true;
|
|
}
|
|
|
|
if (fromCommit->commitUnblock[tid]) {
|
|
assert(stalls[tid].commit);
|
|
stalls[tid].commit = false;
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
bool
|
|
DefaultRename<Impl>::checkStall(unsigned tid)
|
|
{
|
|
bool ret_val = false;
|
|
|
|
if (stalls[tid].iew) {
|
|
DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
|
|
ret_val = true;
|
|
} else if (stalls[tid].commit) {
|
|
DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
|
|
ret_val = true;
|
|
} else if (calcFreeROBEntries(tid) <= 0) {
|
|
DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
|
|
ret_val = true;
|
|
} else if (calcFreeIQEntries(tid) <= 0) {
|
|
DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
|
|
ret_val = true;
|
|
} else if (calcFreeLSQEntries(tid) <= 0) {
|
|
DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
|
|
ret_val = true;
|
|
} else if (renameMap[tid]->numFreeEntries() <= 0) {
|
|
DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
|
|
ret_val = true;
|
|
} else if (renameStatus[tid] == SerializeStall &&
|
|
(!emptyROB[tid] || instsInProgress[tid])) {
|
|
DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
|
|
"empty.\n",
|
|
tid);
|
|
ret_val = true;
|
|
}
|
|
|
|
return ret_val;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
DefaultRename<Impl>::readFreeEntries(unsigned tid)
|
|
{
|
|
bool updated = false;
|
|
if (fromIEW->iewInfo[tid].usedIQ) {
|
|
freeEntries[tid].iqEntries =
|
|
fromIEW->iewInfo[tid].freeIQEntries;
|
|
updated = true;
|
|
}
|
|
|
|
if (fromIEW->iewInfo[tid].usedLSQ) {
|
|
freeEntries[tid].lsqEntries =
|
|
fromIEW->iewInfo[tid].freeLSQEntries;
|
|
updated = true;
|
|
}
|
|
|
|
if (fromCommit->commitInfo[tid].usedROB) {
|
|
freeEntries[tid].robEntries =
|
|
fromCommit->commitInfo[tid].freeROBEntries;
|
|
emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
|
|
updated = true;
|
|
}
|
|
|
|
DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
|
|
tid,
|
|
freeEntries[tid].iqEntries,
|
|
freeEntries[tid].robEntries,
|
|
freeEntries[tid].lsqEntries);
|
|
|
|
DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
|
|
tid, instsInProgress[tid]);
|
|
}
|
|
|
|
template <class Impl>
|
|
bool
|
|
DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid)
|
|
{
|
|
// Check if there's a squash signal, squash if there is
|
|
// Check stall signals, block if necessary.
|
|
// If status was blocked
|
|
// check if stall conditions have passed
|
|
// if so then go to unblocking
|
|
// If status was Squashing
|
|
// check if squashing is not high. Switch to running this cycle.
|
|
// If status was serialize stall
|
|
// check if ROB is empty and no insts are in flight to the ROB
|
|
|
|
readFreeEntries(tid);
|
|
readStallSignals(tid);
|
|
|
|
if (fromCommit->commitInfo[tid].squash) {
|
|
DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
|
|
"commit.\n", tid);
|
|
|
|
squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
|
|
|
|
return true;
|
|
}
|
|
|
|
if (fromCommit->commitInfo[tid].robSquashing) {
|
|
DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
|
|
|
|
renameStatus[tid] = Squashing;
|
|
|
|
return true;
|
|
}
|
|
|
|
if (checkStall(tid)) {
|
|
return block(tid);
|
|
}
|
|
|
|
if (renameStatus[tid] == Blocked) {
|
|
DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
|
|
tid);
|
|
|
|
renameStatus[tid] = Unblocking;
|
|
|
|
unblock(tid);
|
|
|
|
return true;
|
|
}
|
|
|
|
if (renameStatus[tid] == Squashing) {
|
|
// Switch status to running if rename isn't being told to block or
|
|
// squash this cycle.
|
|
if (resumeSerialize) {
|
|
DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n",
|
|
tid);
|
|
|
|
renameStatus[tid] = SerializeStall;
|
|
return true;
|
|
} else if (resumeUnblocking) {
|
|
DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n",
|
|
tid);
|
|
renameStatus[tid] = Unblocking;
|
|
return true;
|
|
} else {
|
|
DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
|
|
tid);
|
|
|
|
renameStatus[tid] = Running;
|
|
return false;
|
|
}
|
|
}
|
|
|
|
if (renameStatus[tid] == SerializeStall) {
|
|
// Stall ends once the ROB is free.
|
|
DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
|
|
"unblocking.\n", tid);
|
|
|
|
DynInstPtr serial_inst = serializeInst[tid];
|
|
|
|
renameStatus[tid] = Unblocking;
|
|
|
|
unblock(tid);
|
|
|
|
DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
|
|
"PC %#x.\n",
|
|
tid, serial_inst->seqNum, serial_inst->readPC());
|
|
|
|
// Put instruction into queue here.
|
|
serial_inst->clearSerializeBefore();
|
|
|
|
if (!skidBuffer[tid].empty()) {
|
|
skidBuffer[tid].push_front(serial_inst);
|
|
} else {
|
|
insts[tid].push_front(serial_inst);
|
|
}
|
|
|
|
DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
|
|
" Adding to front of list.\n", tid);
|
|
|
|
serializeInst[tid] = NULL;
|
|
|
|
return true;
|
|
}
|
|
|
|
// If we've reached this point, we have not gotten any signals that
|
|
// cause rename to change its status. Rename remains the same as before.
|
|
return false;
|
|
}
|
|
|
|
template<class Impl>
|
|
void
|
|
DefaultRename<Impl>::serializeAfter(InstQueue &inst_list,
|
|
unsigned tid)
|
|
{
|
|
if (inst_list.empty()) {
|
|
// Mark a bit to say that I must serialize on the next instruction.
|
|
serializeOnNextInst[tid] = true;
|
|
return;
|
|
}
|
|
|
|
// Set the next instruction as serializing.
|
|
inst_list.front()->setSerializeBefore();
|
|
}
|
|
|
|
template <class Impl>
|
|
inline void
|
|
DefaultRename<Impl>::incrFullStat(const FullSource &source)
|
|
{
|
|
switch (source) {
|
|
case ROB:
|
|
++renameROBFullEvents;
|
|
break;
|
|
case IQ:
|
|
++renameIQFullEvents;
|
|
break;
|
|
case LSQ:
|
|
++renameLSQFullEvents;
|
|
break;
|
|
default:
|
|
panic("Rename full stall stat should be incremented for a reason!");
|
|
break;
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
DefaultRename<Impl>::dumpHistory()
|
|
{
|
|
typename std::list<RenameHistory>::iterator buf_it;
|
|
|
|
for (int i = 0; i < numThreads; i++) {
|
|
|
|
buf_it = historyBuffer[i].begin();
|
|
|
|
while (buf_it != historyBuffer[i].end()) {
|
|
cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
|
|
"reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
|
|
(int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
|
|
|
|
buf_it++;
|
|
}
|
|
}
|
|
}
|