cpu/base_dyn_inst.cc: Remove unused commented out code. cpu/base_dyn_inst.hh: Fix up comments. cpu/beta_cpu/2bit_local_pred.cc: Reorder code to match header file. cpu/beta_cpu/2bit_local_pred.hh: Update comments. cpu/beta_cpu/alpha_dyn_inst.hh: Remove useless comments. cpu/beta_cpu/alpha_dyn_inst_impl.hh: cpu/beta_cpu/alpha_full_cpu_impl.hh: cpu/beta_cpu/comm.hh: cpu/beta_cpu/iew_impl.hh: Remove unused commented code. cpu/beta_cpu/alpha_full_cpu.hh: Remove obsolete comment. cpu/beta_cpu/alpha_impl.hh: cpu/beta_cpu/full_cpu.hh: Alphabetize includes. cpu/beta_cpu/bpred_unit.hh: Remove unused global history code. cpu/beta_cpu/btb.hh: cpu/beta_cpu/free_list.hh: Use full path in #defines. cpu/beta_cpu/commit.hh: cpu/beta_cpu/decode.hh: Reorder functions. cpu/beta_cpu/commit_impl.hh: Remove obsolete commented code. cpu/beta_cpu/fetch.hh: Remove obsolete comments. cpu/beta_cpu/fetch_impl.hh: cpu/beta_cpu/rename_impl.hh: Remove commented code. cpu/beta_cpu/full_cpu.cc: Remove useless defines. cpu/beta_cpu/inst_queue.hh: Use full path for #defines. cpu/beta_cpu/inst_queue_impl.hh: Reorder functions to match header file. cpu/beta_cpu/mem_dep_unit.hh: Use full path name for #defines. cpu/beta_cpu/ras.hh: Use full path names for #defines. Remove mod operation. cpu/beta_cpu/regfile.hh: Remove unused commented code, fix up current comments. cpu/beta_cpu/tournament_pred.cc: cpu/beta_cpu/tournament_pred.hh: Update programming style. --HG-- extra : convert_revision : fb9d18a853f58a1108ff827e3c123d5b52a0608a
309 lines
9.6 KiB
C++
309 lines
9.6 KiB
C++
#ifndef __CPU_BETA_CPU_INST_QUEUE_HH__
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#define __CPU_BETA_CPU_INST_QUEUE_HH__
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#include <list>
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#include <map>
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#include <queue>
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#include <stdint.h>
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#include <vector>
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#include "base/statistics.hh"
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#include "base/timebuf.hh"
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#include "cpu/inst_seq.hh"
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/**
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* A standard instruction queue class. It holds instructions in an
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* array, holds the ordering of the instructions within a linked list,
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* and tracks producer/consumer dependencies within a separate linked
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* list. Similar to the rename map and the free list, it expects that
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* floating point registers have their indices start after the integer
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* registers (ie with 96 int and 96 fp registers, regs 0-95 are integer
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* and 96-191 are fp). This remains true even for both logical and
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* physical register indices.
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*/
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template <class Impl>
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class InstructionQueue
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{
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public:
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//Typedefs from the Impl.
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typedef typename Impl::FullCPU FullCPU;
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typedef typename Impl::DynInstPtr DynInstPtr;
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typedef typename Impl::Params Params;
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typedef typename Impl::CPUPol::MemDepUnit MemDepUnit;
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typedef typename Impl::CPUPol::IssueStruct IssueStruct;
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typedef typename Impl::CPUPol::TimeStruct TimeStruct;
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// Typedef of iterator through the list of instructions. Might be
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// better to untie this from the FullCPU or pass its information to
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// the stages.
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typedef typename std::list<DynInstPtr>::iterator ListIt;
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/**
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* Struct for comparing entries to be added to the priority queue. This
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* gives reverse ordering to the instructions in terms of sequence
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* numbers: the instructions with smaller sequence numbers (and hence
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* are older) will be at the top of the priority queue.
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*/
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struct pqCompare
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{
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bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const
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{
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return lhs->seqNum > rhs->seqNum;
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}
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};
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/**
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* Struct for comparing entries to be added to the set. This gives
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* standard ordering in terms of sequence numbers.
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*/
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struct setCompare
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{
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bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const
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{
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return lhs->seqNum < rhs->seqNum;
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}
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};
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typedef std::priority_queue<DynInstPtr, vector<DynInstPtr>, pqCompare>
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ReadyInstQueue;
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InstructionQueue(Params ¶ms);
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void regStats();
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void setCPU(FullCPU *cpu);
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void setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2eQueue);
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void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
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unsigned numFreeEntries();
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bool isFull();
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void insert(DynInstPtr &new_inst);
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void insertNonSpec(DynInstPtr &new_inst);
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void advanceTail(DynInstPtr &inst);
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void scheduleReadyInsts();
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void scheduleNonSpec(const InstSeqNum &inst);
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void wakeDependents(DynInstPtr &completed_inst);
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void violation(DynInstPtr &store, DynInstPtr &faulting_load);
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// Change this to take in the sequence number
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void squash();
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void doSquash();
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void stopSquash();
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private:
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/** Pointer to the CPU. */
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FullCPU *cpu;
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/** The memory dependence unit, which tracks/predicts memory dependences
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* between instructions.
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*/
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MemDepUnit memDepUnit;
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/** The queue to the execute stage. Issued instructions will be written
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* into it.
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*/
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TimeBuffer<IssueStruct> *issueToExecuteQueue;
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/** The backwards time buffer. */
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TimeBuffer<TimeStruct> *timeBuffer;
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/** Wire to read information from timebuffer. */
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typename TimeBuffer<TimeStruct>::wire fromCommit;
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enum InstList {
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Int,
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Float,
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Branch,
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Memory,
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Misc,
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Squashed,
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None
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};
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/** List of ready int instructions. Used to keep track of the order in
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* which instructions should issue.
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*/
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ReadyInstQueue readyIntInsts;
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/** List of ready floating point instructions. */
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ReadyInstQueue readyFloatInsts;
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/** List of ready branch instructions. */
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ReadyInstQueue readyBranchInsts;
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/** List of ready miscellaneous instructions. */
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ReadyInstQueue readyMiscInsts;
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/** List of squashed instructions (which are still valid and in IQ).
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* Implemented using a priority queue; the entries must contain both
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* the IQ index and sequence number of each instruction so that
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* ordering based on sequence numbers can be used.
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*/
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ReadyInstQueue squashedInsts;
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/** List of non-speculative instructions that will be scheduled
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* once the IQ gets a signal from commit. While it's redundant to
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* have the key be a part of the value (the sequence number is stored
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* inside of DynInst), when these instructions are woken up only
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* the sequence number will be available. Thus it is most efficient to be
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* able to search by the sequence number alone.
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*/
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std::map<InstSeqNum, DynInstPtr> nonSpecInsts;
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typedef typename std::map<InstSeqNum, DynInstPtr>::iterator non_spec_it_t;
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/** Number of free IQ entries left. */
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unsigned freeEntries;
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/** The number of entries in the instruction queue. */
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unsigned numEntries;
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/** The number of integer instructions that can be issued in one
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* cycle.
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*/
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unsigned intWidth;
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/** The number of floating point instructions that can be issued
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* in one cycle.
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*/
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unsigned floatWidth;
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/** The number of branches that can be issued in one cycle. */
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unsigned branchWidth;
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/** The number of memory instructions that can be issued in one cycle. */
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unsigned memoryWidth;
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/** The total number of instructions that can be issued in one cycle. */
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unsigned totalWidth;
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//The number of physical registers in the CPU.
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unsigned numPhysRegs;
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/** The number of physical integer registers in the CPU. */
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unsigned numPhysIntRegs;
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/** The number of floating point registers in the CPU. */
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unsigned numPhysFloatRegs;
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/** Delay between commit stage and the IQ.
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* @todo: Make there be a distinction between the delays within IEW.
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*/
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unsigned commitToIEWDelay;
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//////////////////////////////////
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// Variables needed for squashing
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//////////////////////////////////
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/** The sequence number of the squashed instruction. */
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InstSeqNum squashedSeqNum;
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/** Iterator that points to the youngest instruction in the IQ. */
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ListIt tail;
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/** Iterator that points to the last instruction that has been squashed.
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* This will not be valid unless the IQ is in the process of squashing.
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*/
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ListIt squashIt;
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///////////////////////////////////
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// Dependency graph stuff
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///////////////////////////////////
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class DependencyEntry
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{
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public:
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DynInstPtr inst;
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//Might want to include data about what arch. register the
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//dependence is waiting on.
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DependencyEntry *next;
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//This function, and perhaps this whole class, stand out a little
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//bit as they don't fit a classification well. I want access
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//to the underlying structure of the linked list, yet at
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//the same time it feels like this should be something abstracted
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//away. So for now it will sit here, within the IQ, until
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//a better implementation is decided upon.
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// This function probably shouldn't be within the entry...
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void insert(DynInstPtr &new_inst);
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void remove(DynInstPtr &inst_to_remove);
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// Debug variable, remove when done testing.
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static unsigned mem_alloc_counter;
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};
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/** Array of linked lists. Each linked list is a list of all the
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* instructions that depend upon a given register. The actual
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* register's index is used to index into the graph; ie all
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* instructions in flight that are dependent upon r34 will be
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* in the linked list of dependGraph[34].
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*/
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DependencyEntry *dependGraph;
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/** A cache of the recently woken registers. It is 1 if the register
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* has been woken up recently, and 0 if the register has been added
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* to the dependency graph and has not yet received its value. It
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* is basically a secondary scoreboard, and should pretty much mirror
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* the scoreboard that exists in the rename map.
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*/
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vector<bool> regScoreboard;
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bool addToDependents(DynInstPtr &new_inst);
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void insertDependency(DynInstPtr &new_inst);
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void createDependency(DynInstPtr &new_inst);
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void addIfReady(DynInstPtr &inst);
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private:
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/** Debugging function to count how many entries are in the IQ. It does
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* a linear walk through the instructions, so do not call this function
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* during normal execution.
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*/
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int countInsts();
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/** Debugging function to dump out the dependency graph.
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*/
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void dumpDependGraph();
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/** Debugging function to dump all the list sizes, as well as print
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* out the list of nonspeculative instructions. Should not be used
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* in any other capacity, but it has no harmful sideaffects.
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*/
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void dumpLists();
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Stats::Scalar<> iqInstsAdded;
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Stats::Scalar<> iqNonSpecInstsAdded;
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// Stats::Scalar<> iqIntInstsAdded;
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Stats::Scalar<> iqIntInstsIssued;
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// Stats::Scalar<> iqFloatInstsAdded;
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Stats::Scalar<> iqFloatInstsIssued;
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// Stats::Scalar<> iqBranchInstsAdded;
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Stats::Scalar<> iqBranchInstsIssued;
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// Stats::Scalar<> iqMemInstsAdded;
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Stats::Scalar<> iqMemInstsIssued;
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// Stats::Scalar<> iqMiscInstsAdded;
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Stats::Scalar<> iqMiscInstsIssued;
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Stats::Scalar<> iqSquashedInstsIssued;
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Stats::Scalar<> iqLoopSquashStalls;
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Stats::Scalar<> iqSquashedInstsExamined;
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Stats::Scalar<> iqSquashedOperandsExamined;
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Stats::Scalar<> iqSquashedNonSpecRemoved;
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};
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#endif //__CPU_BETA_CPU_INST_QUEUE_HH__
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