c2d2ea99e3
This patch decouples the queueing and the port interactions to simplify the introduction of the master and slave ports. By separating the queueing functionality from the port itself, it becomes much easier to distinguish between master and slave ports, and still retain the queueing ability for both (without code duplication). As part of the split into a PacketQueue and a port, there is now also a hierarchy of two port classes, QueuedPort and SimpleTimingPort. The QueuedPort is useful for ports that want to leave the packet transmission of outgoing packets to the queue and is used by both master and slave ports. The SimpleTimingPort inherits from the QueuedPort and adds the implemention of recvTiming and recvFunctional through recvAtomic. The PioPort and MessagePort are cleaned up as part of the changes. --HG-- rename : src/mem/tport.cc => src/mem/packet_queue.cc rename : src/mem/tport.hh => src/mem/packet_queue.hh
742 lines
25 KiB
C++
742 lines
25 KiB
C++
/*
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* Copyright (c) 2012 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Erik Hallnor
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*/
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/**
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* @file
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* Definition of BaseCache functions.
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*/
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#include "cpu/base.hh"
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#include "cpu/smt.hh"
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#include "debug/Cache.hh"
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#include "mem/cache/base.hh"
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#include "mem/cache/mshr.hh"
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#include "sim/full_system.hh"
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using namespace std;
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BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name,
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BaseCache *_cache,
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const std::string &_label)
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: QueuedPort(_name, _cache, queue), queue(*_cache, *this, _label),
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blocked(false), mustSendRetry(false), sendRetryEvent(this)
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{
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}
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BaseCache::BaseCache(const Params *p)
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: MemObject(p),
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mshrQueue("MSHRs", p->mshrs, 4, MSHRQueue_MSHRs),
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writeBuffer("write buffer", p->write_buffers, p->mshrs+1000,
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MSHRQueue_WriteBuffer),
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blkSize(p->block_size),
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hitLatency(p->latency),
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numTarget(p->tgts_per_mshr),
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forwardSnoops(p->forward_snoops),
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isTopLevel(p->is_top_level),
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blocked(0),
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noTargetMSHR(NULL),
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missCount(p->max_miss_count),
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drainEvent(NULL),
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addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()),
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system(p->system)
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{
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}
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void
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BaseCache::CacheSlavePort::setBlocked()
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{
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assert(!blocked);
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DPRINTF(CachePort, "Cache port %s blocking new requests\n", name());
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blocked = true;
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}
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void
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BaseCache::CacheSlavePort::clearBlocked()
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{
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assert(blocked);
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DPRINTF(CachePort, "Cache port %s accepting new requests\n", name());
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blocked = false;
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if (mustSendRetry) {
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DPRINTF(CachePort, "Cache port %s sending retry\n", name());
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mustSendRetry = false;
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// @TODO: need to find a better time (next bus cycle?)
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owner->schedule(sendRetryEvent, curTick() + 1);
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}
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}
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void
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BaseCache::init()
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{
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if (!cpuSidePort->isConnected() || !memSidePort->isConnected())
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panic("Cache %s not hooked up on both sides\n", name());
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cpuSidePort->sendRangeChange();
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}
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void
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BaseCache::regStats()
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{
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using namespace Stats;
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// Hit statistics
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for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
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MemCmd cmd(access_idx);
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const string &cstr = cmd.toString();
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hits[access_idx]
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.init(system->maxMasters())
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.name(name() + "." + cstr + "_hits")
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.desc("number of " + cstr + " hits")
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.flags(total | nozero | nonan)
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;
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for (int i = 0; i < system->maxMasters(); i++) {
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hits[access_idx].subname(i, system->getMasterName(i));
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}
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}
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// These macros make it easier to sum the right subset of commands and
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// to change the subset of commands that are considered "demand" vs
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// "non-demand"
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#define SUM_DEMAND(s) \
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(s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::ReadExReq])
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// should writebacks be included here? prior code was inconsistent...
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#define SUM_NON_DEMAND(s) \
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(s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq])
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demandHits
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.name(name() + ".demand_hits")
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.desc("number of demand (read+write) hits")
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.flags(total | nozero | nonan)
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;
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demandHits = SUM_DEMAND(hits);
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for (int i = 0; i < system->maxMasters(); i++) {
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demandHits.subname(i, system->getMasterName(i));
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}
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overallHits
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.name(name() + ".overall_hits")
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.desc("number of overall hits")
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.flags(total | nozero | nonan)
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;
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overallHits = demandHits + SUM_NON_DEMAND(hits);
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for (int i = 0; i < system->maxMasters(); i++) {
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overallHits.subname(i, system->getMasterName(i));
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}
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// Miss statistics
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for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
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MemCmd cmd(access_idx);
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const string &cstr = cmd.toString();
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misses[access_idx]
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.init(system->maxMasters())
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.name(name() + "." + cstr + "_misses")
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.desc("number of " + cstr + " misses")
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.flags(total | nozero | nonan)
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;
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for (int i = 0; i < system->maxMasters(); i++) {
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misses[access_idx].subname(i, system->getMasterName(i));
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}
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}
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demandMisses
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.name(name() + ".demand_misses")
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.desc("number of demand (read+write) misses")
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.flags(total | nozero | nonan)
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;
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demandMisses = SUM_DEMAND(misses);
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for (int i = 0; i < system->maxMasters(); i++) {
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demandMisses.subname(i, system->getMasterName(i));
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}
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overallMisses
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.name(name() + ".overall_misses")
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.desc("number of overall misses")
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.flags(total | nozero | nonan)
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;
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overallMisses = demandMisses + SUM_NON_DEMAND(misses);
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for (int i = 0; i < system->maxMasters(); i++) {
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overallMisses.subname(i, system->getMasterName(i));
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}
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// Miss latency statistics
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for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
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MemCmd cmd(access_idx);
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const string &cstr = cmd.toString();
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missLatency[access_idx]
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.init(system->maxMasters())
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.name(name() + "." + cstr + "_miss_latency")
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.desc("number of " + cstr + " miss cycles")
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.flags(total | nozero | nonan)
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;
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for (int i = 0; i < system->maxMasters(); i++) {
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missLatency[access_idx].subname(i, system->getMasterName(i));
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}
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}
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demandMissLatency
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.name(name() + ".demand_miss_latency")
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.desc("number of demand (read+write) miss cycles")
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.flags(total | nozero | nonan)
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;
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demandMissLatency = SUM_DEMAND(missLatency);
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for (int i = 0; i < system->maxMasters(); i++) {
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demandMissLatency.subname(i, system->getMasterName(i));
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}
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overallMissLatency
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.name(name() + ".overall_miss_latency")
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.desc("number of overall miss cycles")
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.flags(total | nozero | nonan)
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;
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overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency);
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for (int i = 0; i < system->maxMasters(); i++) {
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overallMissLatency.subname(i, system->getMasterName(i));
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}
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// access formulas
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for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
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MemCmd cmd(access_idx);
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const string &cstr = cmd.toString();
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accesses[access_idx]
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.name(name() + "." + cstr + "_accesses")
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.desc("number of " + cstr + " accesses(hits+misses)")
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.flags(total | nozero | nonan)
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;
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accesses[access_idx] = hits[access_idx] + misses[access_idx];
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for (int i = 0; i < system->maxMasters(); i++) {
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accesses[access_idx].subname(i, system->getMasterName(i));
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}
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}
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demandAccesses
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.name(name() + ".demand_accesses")
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.desc("number of demand (read+write) accesses")
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.flags(total | nozero | nonan)
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;
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demandAccesses = demandHits + demandMisses;
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for (int i = 0; i < system->maxMasters(); i++) {
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demandAccesses.subname(i, system->getMasterName(i));
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}
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overallAccesses
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.name(name() + ".overall_accesses")
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.desc("number of overall (read+write) accesses")
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.flags(total | nozero | nonan)
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;
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overallAccesses = overallHits + overallMisses;
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for (int i = 0; i < system->maxMasters(); i++) {
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overallAccesses.subname(i, system->getMasterName(i));
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}
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// miss rate formulas
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for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
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MemCmd cmd(access_idx);
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const string &cstr = cmd.toString();
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missRate[access_idx]
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.name(name() + "." + cstr + "_miss_rate")
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.desc("miss rate for " + cstr + " accesses")
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.flags(total | nozero | nonan)
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;
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missRate[access_idx] = misses[access_idx] / accesses[access_idx];
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for (int i = 0; i < system->maxMasters(); i++) {
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missRate[access_idx].subname(i, system->getMasterName(i));
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}
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}
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demandMissRate
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.name(name() + ".demand_miss_rate")
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.desc("miss rate for demand accesses")
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.flags(total | nozero | nonan)
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;
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demandMissRate = demandMisses / demandAccesses;
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for (int i = 0; i < system->maxMasters(); i++) {
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demandMissRate.subname(i, system->getMasterName(i));
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}
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overallMissRate
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.name(name() + ".overall_miss_rate")
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.desc("miss rate for overall accesses")
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.flags(total | nozero | nonan)
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;
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overallMissRate = overallMisses / overallAccesses;
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for (int i = 0; i < system->maxMasters(); i++) {
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overallMissRate.subname(i, system->getMasterName(i));
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}
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// miss latency formulas
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for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
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MemCmd cmd(access_idx);
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const string &cstr = cmd.toString();
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avgMissLatency[access_idx]
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.name(name() + "." + cstr + "_avg_miss_latency")
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.desc("average " + cstr + " miss latency")
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.flags(total | nozero | nonan)
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;
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avgMissLatency[access_idx] =
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missLatency[access_idx] / misses[access_idx];
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for (int i = 0; i < system->maxMasters(); i++) {
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avgMissLatency[access_idx].subname(i, system->getMasterName(i));
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}
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}
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demandAvgMissLatency
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.name(name() + ".demand_avg_miss_latency")
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.desc("average overall miss latency")
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.flags(total | nozero | nonan)
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;
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demandAvgMissLatency = demandMissLatency / demandMisses;
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for (int i = 0; i < system->maxMasters(); i++) {
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demandAvgMissLatency.subname(i, system->getMasterName(i));
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}
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overallAvgMissLatency
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.name(name() + ".overall_avg_miss_latency")
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.desc("average overall miss latency")
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.flags(total | nozero | nonan)
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;
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overallAvgMissLatency = overallMissLatency / overallMisses;
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for (int i = 0; i < system->maxMasters(); i++) {
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overallAvgMissLatency.subname(i, system->getMasterName(i));
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}
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blocked_cycles.init(NUM_BLOCKED_CAUSES);
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blocked_cycles
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.name(name() + ".blocked_cycles")
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.desc("number of cycles access was blocked")
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.subname(Blocked_NoMSHRs, "no_mshrs")
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.subname(Blocked_NoTargets, "no_targets")
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;
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blocked_causes.init(NUM_BLOCKED_CAUSES);
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blocked_causes
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.name(name() + ".blocked")
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.desc("number of cycles access was blocked")
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.subname(Blocked_NoMSHRs, "no_mshrs")
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.subname(Blocked_NoTargets, "no_targets")
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;
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avg_blocked
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.name(name() + ".avg_blocked_cycles")
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.desc("average number of cycles each access was blocked")
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.subname(Blocked_NoMSHRs, "no_mshrs")
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.subname(Blocked_NoTargets, "no_targets")
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;
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avg_blocked = blocked_cycles / blocked_causes;
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fastWrites
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.name(name() + ".fast_writes")
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.desc("number of fast writes performed")
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;
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cacheCopies
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.name(name() + ".cache_copies")
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.desc("number of cache copies performed")
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;
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writebacks
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.init(system->maxMasters())
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.name(name() + ".writebacks")
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.desc("number of writebacks")
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.flags(total | nozero | nonan)
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;
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for (int i = 0; i < system->maxMasters(); i++) {
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writebacks.subname(i, system->getMasterName(i));
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}
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// MSHR statistics
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// MSHR hit statistics
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for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
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MemCmd cmd(access_idx);
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const string &cstr = cmd.toString();
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mshr_hits[access_idx]
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.init(system->maxMasters())
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.name(name() + "." + cstr + "_mshr_hits")
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.desc("number of " + cstr + " MSHR hits")
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.flags(total | nozero | nonan)
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;
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for (int i = 0; i < system->maxMasters(); i++) {
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mshr_hits[access_idx].subname(i, system->getMasterName(i));
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}
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}
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demandMshrHits
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.name(name() + ".demand_mshr_hits")
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.desc("number of demand (read+write) MSHR hits")
|
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.flags(total | nozero | nonan)
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;
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demandMshrHits = SUM_DEMAND(mshr_hits);
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for (int i = 0; i < system->maxMasters(); i++) {
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demandMshrHits.subname(i, system->getMasterName(i));
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}
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overallMshrHits
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.name(name() + ".overall_mshr_hits")
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.desc("number of overall MSHR hits")
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.flags(total | nozero | nonan)
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;
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overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits);
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for (int i = 0; i < system->maxMasters(); i++) {
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overallMshrHits.subname(i, system->getMasterName(i));
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}
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|
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// MSHR miss statistics
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for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
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MemCmd cmd(access_idx);
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const string &cstr = cmd.toString();
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|
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mshr_misses[access_idx]
|
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.init(system->maxMasters())
|
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.name(name() + "." + cstr + "_mshr_misses")
|
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.desc("number of " + cstr + " MSHR misses")
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.flags(total | nozero | nonan)
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;
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for (int i = 0; i < system->maxMasters(); i++) {
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mshr_misses[access_idx].subname(i, system->getMasterName(i));
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}
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}
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|
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demandMshrMisses
|
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.name(name() + ".demand_mshr_misses")
|
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.desc("number of demand (read+write) MSHR misses")
|
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.flags(total | nozero | nonan)
|
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;
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demandMshrMisses = SUM_DEMAND(mshr_misses);
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for (int i = 0; i < system->maxMasters(); i++) {
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demandMshrMisses.subname(i, system->getMasterName(i));
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}
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overallMshrMisses
|
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.name(name() + ".overall_mshr_misses")
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.desc("number of overall MSHR misses")
|
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.flags(total | nozero | nonan)
|
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;
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overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses);
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for (int i = 0; i < system->maxMasters(); i++) {
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overallMshrMisses.subname(i, system->getMasterName(i));
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}
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|
|
// MSHR miss latency statistics
|
|
for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
|
|
MemCmd cmd(access_idx);
|
|
const string &cstr = cmd.toString();
|
|
|
|
mshr_miss_latency[access_idx]
|
|
.init(system->maxMasters())
|
|
.name(name() + "." + cstr + "_mshr_miss_latency")
|
|
.desc("number of " + cstr + " MSHR miss cycles")
|
|
.flags(total | nozero | nonan)
|
|
;
|
|
for (int i = 0; i < system->maxMasters(); i++) {
|
|
mshr_miss_latency[access_idx].subname(i, system->getMasterName(i));
|
|
}
|
|
}
|
|
|
|
demandMshrMissLatency
|
|
.name(name() + ".demand_mshr_miss_latency")
|
|
.desc("number of demand (read+write) MSHR miss cycles")
|
|
.flags(total | nozero | nonan)
|
|
;
|
|
demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency);
|
|
for (int i = 0; i < system->maxMasters(); i++) {
|
|
demandMshrMissLatency.subname(i, system->getMasterName(i));
|
|
}
|
|
|
|
overallMshrMissLatency
|
|
.name(name() + ".overall_mshr_miss_latency")
|
|
.desc("number of overall MSHR miss cycles")
|
|
.flags(total | nozero | nonan)
|
|
;
|
|
overallMshrMissLatency =
|
|
demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency);
|
|
for (int i = 0; i < system->maxMasters(); i++) {
|
|
overallMshrMissLatency.subname(i, system->getMasterName(i));
|
|
}
|
|
|
|
// MSHR uncacheable statistics
|
|
for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
|
|
MemCmd cmd(access_idx);
|
|
const string &cstr = cmd.toString();
|
|
|
|
mshr_uncacheable[access_idx]
|
|
.init(system->maxMasters())
|
|
.name(name() + "." + cstr + "_mshr_uncacheable")
|
|
.desc("number of " + cstr + " MSHR uncacheable")
|
|
.flags(total | nozero | nonan)
|
|
;
|
|
for (int i = 0; i < system->maxMasters(); i++) {
|
|
mshr_uncacheable[access_idx].subname(i, system->getMasterName(i));
|
|
}
|
|
}
|
|
|
|
overallMshrUncacheable
|
|
.name(name() + ".overall_mshr_uncacheable_misses")
|
|
.desc("number of overall MSHR uncacheable misses")
|
|
.flags(total | nozero | nonan)
|
|
;
|
|
overallMshrUncacheable =
|
|
SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable);
|
|
for (int i = 0; i < system->maxMasters(); i++) {
|
|
overallMshrUncacheable.subname(i, system->getMasterName(i));
|
|
}
|
|
|
|
// MSHR miss latency statistics
|
|
for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
|
|
MemCmd cmd(access_idx);
|
|
const string &cstr = cmd.toString();
|
|
|
|
mshr_uncacheable_lat[access_idx]
|
|
.init(system->maxMasters())
|
|
.name(name() + "." + cstr + "_mshr_uncacheable_latency")
|
|
.desc("number of " + cstr + " MSHR uncacheable cycles")
|
|
.flags(total | nozero | nonan)
|
|
;
|
|
for (int i = 0; i < system->maxMasters(); i++) {
|
|
mshr_uncacheable_lat[access_idx].subname(i, system->getMasterName(i));
|
|
}
|
|
}
|
|
|
|
overallMshrUncacheableLatency
|
|
.name(name() + ".overall_mshr_uncacheable_latency")
|
|
.desc("number of overall MSHR uncacheable cycles")
|
|
.flags(total | nozero | nonan)
|
|
;
|
|
overallMshrUncacheableLatency =
|
|
SUM_DEMAND(mshr_uncacheable_lat) +
|
|
SUM_NON_DEMAND(mshr_uncacheable_lat);
|
|
for (int i = 0; i < system->maxMasters(); i++) {
|
|
overallMshrUncacheableLatency.subname(i, system->getMasterName(i));
|
|
}
|
|
|
|
#if 0
|
|
// MSHR access formulas
|
|
for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
|
|
MemCmd cmd(access_idx);
|
|
const string &cstr = cmd.toString();
|
|
|
|
mshrAccesses[access_idx]
|
|
.name(name() + "." + cstr + "_mshr_accesses")
|
|
.desc("number of " + cstr + " mshr accesses(hits+misses)")
|
|
.flags(total | nozero | nonan)
|
|
;
|
|
mshrAccesses[access_idx] =
|
|
mshr_hits[access_idx] + mshr_misses[access_idx]
|
|
+ mshr_uncacheable[access_idx];
|
|
}
|
|
|
|
demandMshrAccesses
|
|
.name(name() + ".demand_mshr_accesses")
|
|
.desc("number of demand (read+write) mshr accesses")
|
|
.flags(total | nozero | nonan)
|
|
;
|
|
demandMshrAccesses = demandMshrHits + demandMshrMisses;
|
|
|
|
overallMshrAccesses
|
|
.name(name() + ".overall_mshr_accesses")
|
|
.desc("number of overall (read+write) mshr accesses")
|
|
.flags(total | nozero | nonan)
|
|
;
|
|
overallMshrAccesses = overallMshrHits + overallMshrMisses
|
|
+ overallMshrUncacheable;
|
|
#endif
|
|
|
|
// MSHR miss rate formulas
|
|
for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
|
|
MemCmd cmd(access_idx);
|
|
const string &cstr = cmd.toString();
|
|
|
|
mshrMissRate[access_idx]
|
|
.name(name() + "." + cstr + "_mshr_miss_rate")
|
|
.desc("mshr miss rate for " + cstr + " accesses")
|
|
.flags(total | nozero | nonan)
|
|
;
|
|
mshrMissRate[access_idx] =
|
|
mshr_misses[access_idx] / accesses[access_idx];
|
|
|
|
for (int i = 0; i < system->maxMasters(); i++) {
|
|
mshrMissRate[access_idx].subname(i, system->getMasterName(i));
|
|
}
|
|
}
|
|
|
|
demandMshrMissRate
|
|
.name(name() + ".demand_mshr_miss_rate")
|
|
.desc("mshr miss rate for demand accesses")
|
|
.flags(total | nozero | nonan)
|
|
;
|
|
demandMshrMissRate = demandMshrMisses / demandAccesses;
|
|
for (int i = 0; i < system->maxMasters(); i++) {
|
|
demandMshrMissRate.subname(i, system->getMasterName(i));
|
|
}
|
|
|
|
overallMshrMissRate
|
|
.name(name() + ".overall_mshr_miss_rate")
|
|
.desc("mshr miss rate for overall accesses")
|
|
.flags(total | nozero | nonan)
|
|
;
|
|
overallMshrMissRate = overallMshrMisses / overallAccesses;
|
|
for (int i = 0; i < system->maxMasters(); i++) {
|
|
overallMshrMissRate.subname(i, system->getMasterName(i));
|
|
}
|
|
|
|
// mshrMiss latency formulas
|
|
for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
|
|
MemCmd cmd(access_idx);
|
|
const string &cstr = cmd.toString();
|
|
|
|
avgMshrMissLatency[access_idx]
|
|
.name(name() + "." + cstr + "_avg_mshr_miss_latency")
|
|
.desc("average " + cstr + " mshr miss latency")
|
|
.flags(total | nozero | nonan)
|
|
;
|
|
avgMshrMissLatency[access_idx] =
|
|
mshr_miss_latency[access_idx] / mshr_misses[access_idx];
|
|
|
|
for (int i = 0; i < system->maxMasters(); i++) {
|
|
avgMshrMissLatency[access_idx].subname(i, system->getMasterName(i));
|
|
}
|
|
}
|
|
|
|
demandAvgMshrMissLatency
|
|
.name(name() + ".demand_avg_mshr_miss_latency")
|
|
.desc("average overall mshr miss latency")
|
|
.flags(total | nozero | nonan)
|
|
;
|
|
demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses;
|
|
for (int i = 0; i < system->maxMasters(); i++) {
|
|
demandAvgMshrMissLatency.subname(i, system->getMasterName(i));
|
|
}
|
|
|
|
overallAvgMshrMissLatency
|
|
.name(name() + ".overall_avg_mshr_miss_latency")
|
|
.desc("average overall mshr miss latency")
|
|
.flags(total | nozero | nonan)
|
|
;
|
|
overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses;
|
|
for (int i = 0; i < system->maxMasters(); i++) {
|
|
overallAvgMshrMissLatency.subname(i, system->getMasterName(i));
|
|
}
|
|
|
|
// mshrUncacheable latency formulas
|
|
for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
|
|
MemCmd cmd(access_idx);
|
|
const string &cstr = cmd.toString();
|
|
|
|
avgMshrUncacheableLatency[access_idx]
|
|
.name(name() + "." + cstr + "_avg_mshr_uncacheable_latency")
|
|
.desc("average " + cstr + " mshr uncacheable latency")
|
|
.flags(total | nozero | nonan)
|
|
;
|
|
avgMshrUncacheableLatency[access_idx] =
|
|
mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx];
|
|
|
|
for (int i = 0; i < system->maxMasters(); i++) {
|
|
avgMshrUncacheableLatency[access_idx].subname(i, system->getMasterName(i));
|
|
}
|
|
}
|
|
|
|
overallAvgMshrUncacheableLatency
|
|
.name(name() + ".overall_avg_mshr_uncacheable_latency")
|
|
.desc("average overall mshr uncacheable latency")
|
|
.flags(total | nozero | nonan)
|
|
;
|
|
overallAvgMshrUncacheableLatency = overallMshrUncacheableLatency / overallMshrUncacheable;
|
|
for (int i = 0; i < system->maxMasters(); i++) {
|
|
overallAvgMshrUncacheableLatency.subname(i, system->getMasterName(i));
|
|
}
|
|
|
|
mshr_cap_events
|
|
.init(system->maxMasters())
|
|
.name(name() + ".mshr_cap_events")
|
|
.desc("number of times MSHR cap was activated")
|
|
.flags(total | nozero | nonan)
|
|
;
|
|
for (int i = 0; i < system->maxMasters(); i++) {
|
|
mshr_cap_events.subname(i, system->getMasterName(i));
|
|
}
|
|
|
|
//software prefetching stats
|
|
soft_prefetch_mshr_full
|
|
.init(system->maxMasters())
|
|
.name(name() + ".soft_prefetch_mshr_full")
|
|
.desc("number of mshr full events for SW prefetching instrutions")
|
|
.flags(total | nozero | nonan)
|
|
;
|
|
for (int i = 0; i < system->maxMasters(); i++) {
|
|
soft_prefetch_mshr_full.subname(i, system->getMasterName(i));
|
|
}
|
|
|
|
mshr_no_allocate_misses
|
|
.name(name() +".no_allocate_misses")
|
|
.desc("Number of misses that were no-allocate")
|
|
;
|
|
|
|
}
|
|
|
|
unsigned int
|
|
BaseCache::drain(Event *de)
|
|
{
|
|
int count = memSidePort->drain(de) + cpuSidePort->drain(de);
|
|
|
|
// Set status
|
|
if (count != 0) {
|
|
drainEvent = de;
|
|
|
|
changeState(SimObject::Draining);
|
|
return count;
|
|
}
|
|
|
|
changeState(SimObject::Drained);
|
|
return 0;
|
|
}
|