b38f67d5b7
requestTime -> time responseTime -> packet.time Make CPU and memory able to connect to the bus dev/io_device.cc: update for request and packet both having a time hand platform off to port for eventual selection of request modes dev/io_device.hh: update for request and packet both havig a time hand platform off to port for eventual selection of request modes mem/bus.hh: Add a device map struct that maps a range to a portId - Which needs work it theory it should be an interval tree - but it is a list and works fine right now Add a function called findPort which returns port for an addr range Add a deviceBlockSize function that really shouldn't exist, but it was easier than fixing the translating port mem/packet.hh: add a time to each packet mem/physical.cc: mem/physical.hh: python/m5/objects/PhysicalMemory.py: Make physical memory take a MemObject parameter of what to connect to mem/request.hh: remove requestTime/responseTime for just time in request which is requset time and the time in the packet which is responsetime python/m5/objects/BaseCPU.py: Instead of memory cpu connects to any memory object python/m5/objects/Bus.py: Fix for new bus object --HG-- extra : convert_revision : 72605e8a3fcdd9e80a41f439909ee7feb3f1fe1d
204 lines
5 KiB
C++
204 lines
5 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "dev/io_device.hh"
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#include "sim/builder.hh"
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PioPort::PioPort(PioDevice *dev, Platform *p)
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: device(dev), platform(p)
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{ }
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Tick
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PioPort::recvAtomic(Packet &pkt)
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{
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return device->recvAtomic(pkt);
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}
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void
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PioPort::recvFunctional(Packet &pkt)
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{
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device->recvAtomic(pkt);
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}
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void
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PioPort::getDeviceAddressRanges(AddrRangeList &range_list, bool &owner)
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{
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device->addressRanges(range_list, owner);
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}
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Packet *
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PioPort::recvRetry()
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{
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Packet* pkt = transmitList.front();
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transmitList.pop_front();
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return pkt;
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}
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void
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PioPort::SendEvent::process()
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{
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if (port->Port::sendTiming(packet) == Success)
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return;
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port->transmitList.push_back(&packet);
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}
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PioDevice::PioDevice(const std::string &name, Platform *p)
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: SimObject(name), platform(p)
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{
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pioPort = new PioPort(this, p);
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}
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bool
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PioPort::recvTiming(Packet &pkt)
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{
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device->recvAtomic(pkt);
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sendTiming(pkt, pkt.time-pkt.req->time);
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return Success;
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}
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PioDevice::~PioDevice()
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{
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if (pioPort)
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delete pioPort;
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}
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DmaPort::DmaPort(DmaDevice *dev)
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: device(dev)
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{ }
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bool
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DmaPort::recvTiming(Packet &pkt)
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{
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completionEvent->schedule(curTick+1);
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completionEvent = NULL;
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return Success;
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}
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DmaDevice::DmaDevice(const std::string &name, Platform *p)
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: PioDevice(name, p)
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{
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dmaPort = new DmaPort(this);
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}
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void
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DmaPort::SendEvent::process()
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{
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if (port->Port::sendTiming(packet) == Success)
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return;
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port->transmitList.push_back(&packet);
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}
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Packet *
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DmaPort::recvRetry()
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{
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Packet* pkt = transmitList.front();
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transmitList.pop_front();
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return pkt;
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}
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void
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DmaPort::dmaAction(Command cmd, DmaPort port, Addr addr, int size,
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Event *event, uint8_t *data)
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{
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assert(event);
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int prevSize = 0;
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Packet basePkt;
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Request baseReq;
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basePkt.flags = 0;
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basePkt.coherence = NULL;
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basePkt.senderState = NULL;
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basePkt.src = 0;
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basePkt.dest = 0;
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basePkt.cmd = cmd;
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basePkt.result = Unknown;
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basePkt.req = NULL;
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baseReq.nicReq = true;
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baseReq.time = curTick;
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completionEvent = event;
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for (ChunkGenerator gen(addr, size, peerBlockSize());
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!gen.done(); gen.next()) {
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Packet *pkt = new Packet(basePkt);
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Request *req = new Request(baseReq);
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pkt->addr = gen.addr();
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pkt->size = gen.size();
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pkt->req = req;
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pkt->req->paddr = pkt->addr;
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pkt->req->size = pkt->size;
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// Increment the data pointer on a write
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pkt->data = data ? data + prevSize : NULL ;
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prevSize += pkt->size;
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sendDma(*pkt);
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}
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}
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void
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DmaPort::sendDma(Packet &pkt)
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{
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// some kind of selction between access methods
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// more work is going to have to be done to make
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// switching actually work
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/* MemState state = device->platform->system->memState;
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if (state == Timing) {
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if (sendTiming(pkt) == Failure)
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transmitList.push_back(&packet);
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} else if (state == Atomic) {*/
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sendAtomic(pkt);
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completionEvent->schedule(pkt.time - pkt.req->time);
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completionEvent = NULL;
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/* } else if (state == Functional) {
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sendFunctional(pkt);
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// Is this correct???
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completionEvent->schedule(pkt.req->responseTime - pkt.req->requestTime);
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completionEvent == NULL;
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} else
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panic("Unknown memory command state.");
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*/
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}
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DmaDevice::~DmaDevice()
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{
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if (dmaPort)
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delete dmaPort;
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}
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