c274057840
Add revision 9adf9d6e2d889a483a92136c96eb8a434d360561 of NoMali-model from https://github.com/ARM-software/nomali-model. This library implements the register interface of the Mali T6xx/T7xx series GPUs, but doesn't do any rendering. It can be used to hide the effects of software rendering.
139 lines
3.4 KiB
C++
139 lines
3.4 KiB
C++
/*
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* Copyright (c) 2014-2015 ARM Limited
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* All rights reserved
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* Authors: Andreas Sandberg
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*/
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#include "jobcontrol.hh"
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#include "gpu.hh"
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#include "regutils.hh"
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namespace NoMali {
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JobControl::JobControl(GPU &_gpu)
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: GPUBlockInt(_gpu,
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RegAddr(JOB_IRQ_RAWSTAT),
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RegAddr(JOB_IRQ_CLEAR),
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RegAddr(JOB_IRQ_MASK),
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RegAddr(JOB_IRQ_STATUS))
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{
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slots.reserve(16);
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for (int i = 0; i < 16; ++i)
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slots.emplace_back(_gpu, *this, i);
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}
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JobControl::~JobControl()
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{
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}
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uint32_t
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JobControl::readReg(RegAddr addr)
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{
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if (addr >= RegAddr(JOB_SLOT0)) {
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return slots[getJobSlotNo(addr)].readReg(getJobSlotAddr(addr));
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} else {
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return GPUBlockInt::readReg(addr);
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}
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}
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void
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JobControl::writeReg(RegAddr addr, uint32_t value)
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{
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switch(addr.value) {
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case JOB_IRQ_CLEAR:
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// Update JS state for all jobs that were affected by the IRQ
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// clear
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updateJsState((value & 0xFFFF) | ((value & 0xFFFF0000) >> 16));
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// FALLTHROUGH - IRQ handling in base class
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case JOB_IRQ_RAWSTAT:
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case JOB_IRQ_MASK:
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case JOB_IRQ_STATUS:
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GPUBlockInt::writeReg(addr, value);
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break;
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default:
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if (addr >= RegAddr(JOB_SLOT0))
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slots[getJobSlotNo(addr)].writeReg(getJobSlotAddr(addr), value);
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break;
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}
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}
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uint32_t
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JobControl::readRegRaw(RegAddr addr)
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{
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if (addr >= RegAddr(JOB_SLOT0)) {
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return slots[getJobSlotNo(addr)].readRegRaw(getJobSlotAddr(addr));
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} else {
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return GPUBlockInt::readRegRaw(addr);
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}
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}
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void
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JobControl::writeRegRaw(RegAddr addr, uint32_t value)
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{
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if (addr >= RegAddr(JOB_SLOT0)) {
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slots[getJobSlotNo(addr)].writeRegRaw(getJobSlotAddr(addr), value);
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} else {
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GPUBlockInt::writeRegRaw(addr, value);
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}
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}
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void
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JobControl::jobDone(uint8_t slot)
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{
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assert(slot <= 15);
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raiseInterrupt(1 << slot);
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}
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void
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JobControl::jobFailed(uint8_t slot)
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{
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assert(slot <= 15);
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raiseInterrupt(0x10000 << slot);
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}
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void
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JobControl::updateJsState(uint16_t jobs)
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{
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// The JS_STATE register contains two bits per job slot; one bit
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// representing an active job and one bit representing the queued
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// job. We need to mask out bits of the jobs affected by this update.
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const uint32_t job_mask(jobs | (jobs << 16));
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uint16_t js_state(regs[RegAddr(JOB_IRQ_JS_STATE)] & ~job_mask);
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// Find if there is an active or active next job for all jobs in
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// the job mask.
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for (int i = 0; i < 16; ++i) {
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const JobSlot &slot(slots[i]);
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if (jobs & (1 << i)) {
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js_state |= slot.active() ? (1 << i) : 0 |
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slot.activeNext() ? (0x10000 << i) : 0;
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}
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}
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regs[RegAddr(JOB_IRQ_JS_STATE)] = js_state;
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}
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void
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JobControl::onInterrupt(int set)
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{
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gpu.intJob(set);
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}
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}
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